1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Kernel-based Virtual Machine driver for Linux 4 * 5 * This header defines architecture specific interfaces, x86 version 6 */ 7 8 #ifndef _ASM_X86_KVM_HOST_H 9 #define _ASM_X86_KVM_HOST_H 10 11 #include <linux/types.h> 12 #include <linux/mm.h> 13 #include <linux/mmu_notifier.h> 14 #include <linux/tracepoint.h> 15 #include <linux/cpumask.h> 16 #include <linux/irq_work.h> 17 #include <linux/irq.h> 18 19 #include <linux/kvm.h> 20 #include <linux/kvm_para.h> 21 #include <linux/kvm_types.h> 22 #include <linux/perf_event.h> 23 #include <linux/pvclock_gtod.h> 24 #include <linux/clocksource.h> 25 #include <linux/irqbypass.h> 26 #include <linux/hyperv.h> 27 28 #include <asm/apic.h> 29 #include <asm/pvclock-abi.h> 30 #include <asm/desc.h> 31 #include <asm/mtrr.h> 32 #include <asm/msr-index.h> 33 #include <asm/asm.h> 34 #include <asm/kvm_page_track.h> 35 #include <asm/kvm_vcpu_regs.h> 36 #include <asm/hyperv-tlfs.h> 37 38 #define KVM_MAX_VCPUS 288 39 #define KVM_SOFT_MAX_VCPUS 240 40 #define KVM_MAX_VCPU_ID 1023 41 #define KVM_USER_MEM_SLOTS 509 42 /* memory slots that are not exposed to userspace */ 43 #define KVM_PRIVATE_MEM_SLOTS 3 44 #define KVM_MEM_SLOTS_NUM (KVM_USER_MEM_SLOTS + KVM_PRIVATE_MEM_SLOTS) 45 46 #define KVM_HALT_POLL_NS_DEFAULT 200000 47 48 #define KVM_IRQCHIP_NUM_PINS KVM_IOAPIC_NUM_PINS 49 50 /* x86-specific vcpu->requests bit members */ 51 #define KVM_REQ_MIGRATE_TIMER KVM_ARCH_REQ(0) 52 #define KVM_REQ_REPORT_TPR_ACCESS KVM_ARCH_REQ(1) 53 #define KVM_REQ_TRIPLE_FAULT KVM_ARCH_REQ(2) 54 #define KVM_REQ_MMU_SYNC KVM_ARCH_REQ(3) 55 #define KVM_REQ_CLOCK_UPDATE KVM_ARCH_REQ(4) 56 #define KVM_REQ_LOAD_CR3 KVM_ARCH_REQ(5) 57 #define KVM_REQ_EVENT KVM_ARCH_REQ(6) 58 #define KVM_REQ_APF_HALT KVM_ARCH_REQ(7) 59 #define KVM_REQ_STEAL_UPDATE KVM_ARCH_REQ(8) 60 #define KVM_REQ_NMI KVM_ARCH_REQ(9) 61 #define KVM_REQ_PMU KVM_ARCH_REQ(10) 62 #define KVM_REQ_PMI KVM_ARCH_REQ(11) 63 #define KVM_REQ_SMI KVM_ARCH_REQ(12) 64 #define KVM_REQ_MASTERCLOCK_UPDATE KVM_ARCH_REQ(13) 65 #define KVM_REQ_MCLOCK_INPROGRESS \ 66 KVM_ARCH_REQ_FLAGS(14, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP) 67 #define KVM_REQ_SCAN_IOAPIC \ 68 KVM_ARCH_REQ_FLAGS(15, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP) 69 #define KVM_REQ_GLOBAL_CLOCK_UPDATE KVM_ARCH_REQ(16) 70 #define KVM_REQ_APIC_PAGE_RELOAD \ 71 KVM_ARCH_REQ_FLAGS(17, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP) 72 #define KVM_REQ_HV_CRASH KVM_ARCH_REQ(18) 73 #define KVM_REQ_IOAPIC_EOI_EXIT KVM_ARCH_REQ(19) 74 #define KVM_REQ_HV_RESET KVM_ARCH_REQ(20) 75 #define KVM_REQ_HV_EXIT KVM_ARCH_REQ(21) 76 #define KVM_REQ_HV_STIMER KVM_ARCH_REQ(22) 77 #define KVM_REQ_LOAD_EOI_EXITMAP KVM_ARCH_REQ(23) 78 #define KVM_REQ_GET_VMCS12_PAGES KVM_ARCH_REQ(24) 79 80 #define CR0_RESERVED_BITS \ 81 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \ 82 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \ 83 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG)) 84 85 #define CR4_RESERVED_BITS \ 86 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\ 87 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \ 88 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR | X86_CR4_PCIDE \ 89 | X86_CR4_OSXSAVE | X86_CR4_SMEP | X86_CR4_FSGSBASE \ 90 | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_VMXE \ 91 | X86_CR4_SMAP | X86_CR4_PKE | X86_CR4_UMIP)) 92 93 #define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR) 94 95 96 97 #define INVALID_PAGE (~(hpa_t)0) 98 #define VALID_PAGE(x) ((x) != INVALID_PAGE) 99 100 #define UNMAPPED_GVA (~(gpa_t)0) 101 102 /* KVM Hugepage definitions for x86 */ 103 enum { 104 PT_PAGE_TABLE_LEVEL = 1, 105 PT_DIRECTORY_LEVEL = 2, 106 PT_PDPE_LEVEL = 3, 107 /* set max level to the biggest one */ 108 PT_MAX_HUGEPAGE_LEVEL = PT_PDPE_LEVEL, 109 }; 110 #define KVM_NR_PAGE_SIZES (PT_MAX_HUGEPAGE_LEVEL - \ 111 PT_PAGE_TABLE_LEVEL + 1) 112 #define KVM_HPAGE_GFN_SHIFT(x) (((x) - 1) * 9) 113 #define KVM_HPAGE_SHIFT(x) (PAGE_SHIFT + KVM_HPAGE_GFN_SHIFT(x)) 114 #define KVM_HPAGE_SIZE(x) (1UL << KVM_HPAGE_SHIFT(x)) 115 #define KVM_HPAGE_MASK(x) (~(KVM_HPAGE_SIZE(x) - 1)) 116 #define KVM_PAGES_PER_HPAGE(x) (KVM_HPAGE_SIZE(x) / PAGE_SIZE) 117 118 static inline gfn_t gfn_to_index(gfn_t gfn, gfn_t base_gfn, int level) 119 { 120 /* KVM_HPAGE_GFN_SHIFT(PT_PAGE_TABLE_LEVEL) must be 0. */ 121 return (gfn >> KVM_HPAGE_GFN_SHIFT(level)) - 122 (base_gfn >> KVM_HPAGE_GFN_SHIFT(level)); 123 } 124 125 #define KVM_PERMILLE_MMU_PAGES 20 126 #define KVM_MIN_ALLOC_MMU_PAGES 64UL 127 #define KVM_MMU_HASH_SHIFT 12 128 #define KVM_NUM_MMU_PAGES (1 << KVM_MMU_HASH_SHIFT) 129 #define KVM_MIN_FREE_MMU_PAGES 5 130 #define KVM_REFILL_PAGES 25 131 #define KVM_MAX_CPUID_ENTRIES 80 132 #define KVM_NR_FIXED_MTRR_REGION 88 133 #define KVM_NR_VAR_MTRR 8 134 135 #define ASYNC_PF_PER_VCPU 64 136 137 enum kvm_reg { 138 VCPU_REGS_RAX = __VCPU_REGS_RAX, 139 VCPU_REGS_RCX = __VCPU_REGS_RCX, 140 VCPU_REGS_RDX = __VCPU_REGS_RDX, 141 VCPU_REGS_RBX = __VCPU_REGS_RBX, 142 VCPU_REGS_RSP = __VCPU_REGS_RSP, 143 VCPU_REGS_RBP = __VCPU_REGS_RBP, 144 VCPU_REGS_RSI = __VCPU_REGS_RSI, 145 VCPU_REGS_RDI = __VCPU_REGS_RDI, 146 #ifdef CONFIG_X86_64 147 VCPU_REGS_R8 = __VCPU_REGS_R8, 148 VCPU_REGS_R9 = __VCPU_REGS_R9, 149 VCPU_REGS_R10 = __VCPU_REGS_R10, 150 VCPU_REGS_R11 = __VCPU_REGS_R11, 151 VCPU_REGS_R12 = __VCPU_REGS_R12, 152 VCPU_REGS_R13 = __VCPU_REGS_R13, 153 VCPU_REGS_R14 = __VCPU_REGS_R14, 154 VCPU_REGS_R15 = __VCPU_REGS_R15, 155 #endif 156 VCPU_REGS_RIP, 157 NR_VCPU_REGS 158 }; 159 160 enum kvm_reg_ex { 161 VCPU_EXREG_PDPTR = NR_VCPU_REGS, 162 VCPU_EXREG_CR3, 163 VCPU_EXREG_RFLAGS, 164 VCPU_EXREG_SEGMENTS, 165 }; 166 167 enum { 168 VCPU_SREG_ES, 169 VCPU_SREG_CS, 170 VCPU_SREG_SS, 171 VCPU_SREG_DS, 172 VCPU_SREG_FS, 173 VCPU_SREG_GS, 174 VCPU_SREG_TR, 175 VCPU_SREG_LDTR, 176 }; 177 178 #include <asm/kvm_emulate.h> 179 180 #define KVM_NR_MEM_OBJS 40 181 182 #define KVM_NR_DB_REGS 4 183 184 #define DR6_BD (1 << 13) 185 #define DR6_BS (1 << 14) 186 #define DR6_BT (1 << 15) 187 #define DR6_RTM (1 << 16) 188 #define DR6_FIXED_1 0xfffe0ff0 189 #define DR6_INIT 0xffff0ff0 190 #define DR6_VOLATILE 0x0001e00f 191 192 #define DR7_BP_EN_MASK 0x000000ff 193 #define DR7_GE (1 << 9) 194 #define DR7_GD (1 << 13) 195 #define DR7_FIXED_1 0x00000400 196 #define DR7_VOLATILE 0xffff2bff 197 198 #define PFERR_PRESENT_BIT 0 199 #define PFERR_WRITE_BIT 1 200 #define PFERR_USER_BIT 2 201 #define PFERR_RSVD_BIT 3 202 #define PFERR_FETCH_BIT 4 203 #define PFERR_PK_BIT 5 204 #define PFERR_GUEST_FINAL_BIT 32 205 #define PFERR_GUEST_PAGE_BIT 33 206 207 #define PFERR_PRESENT_MASK (1U << PFERR_PRESENT_BIT) 208 #define PFERR_WRITE_MASK (1U << PFERR_WRITE_BIT) 209 #define PFERR_USER_MASK (1U << PFERR_USER_BIT) 210 #define PFERR_RSVD_MASK (1U << PFERR_RSVD_BIT) 211 #define PFERR_FETCH_MASK (1U << PFERR_FETCH_BIT) 212 #define PFERR_PK_MASK (1U << PFERR_PK_BIT) 213 #define PFERR_GUEST_FINAL_MASK (1ULL << PFERR_GUEST_FINAL_BIT) 214 #define PFERR_GUEST_PAGE_MASK (1ULL << PFERR_GUEST_PAGE_BIT) 215 216 #define PFERR_NESTED_GUEST_PAGE (PFERR_GUEST_PAGE_MASK | \ 217 PFERR_WRITE_MASK | \ 218 PFERR_PRESENT_MASK) 219 220 /* 221 * The mask used to denote special SPTEs, which can be either MMIO SPTEs or 222 * Access Tracking SPTEs. We use bit 62 instead of bit 63 to avoid conflicting 223 * with the SVE bit in EPT PTEs. 224 */ 225 #define SPTE_SPECIAL_MASK (1ULL << 62) 226 227 /* apic attention bits */ 228 #define KVM_APIC_CHECK_VAPIC 0 229 /* 230 * The following bit is set with PV-EOI, unset on EOI. 231 * We detect PV-EOI changes by guest by comparing 232 * this bit with PV-EOI in guest memory. 233 * See the implementation in apic_update_pv_eoi. 234 */ 235 #define KVM_APIC_PV_EOI_PENDING 1 236 237 struct kvm_kernel_irq_routing_entry; 238 239 /* 240 * We don't want allocation failures within the mmu code, so we preallocate 241 * enough memory for a single page fault in a cache. 242 */ 243 struct kvm_mmu_memory_cache { 244 int nobjs; 245 void *objects[KVM_NR_MEM_OBJS]; 246 }; 247 248 /* 249 * the pages used as guest page table on soft mmu are tracked by 250 * kvm_memory_slot.arch.gfn_track which is 16 bits, so the role bits used 251 * by indirect shadow page can not be more than 15 bits. 252 * 253 * Currently, we used 14 bits that are @level, @gpte_is_8_bytes, @quadrant, @access, 254 * @nxe, @cr0_wp, @smep_andnot_wp and @smap_andnot_wp. 255 */ 256 union kvm_mmu_page_role { 257 u32 word; 258 struct { 259 unsigned level:4; 260 unsigned gpte_is_8_bytes:1; 261 unsigned quadrant:2; 262 unsigned direct:1; 263 unsigned access:3; 264 unsigned invalid:1; 265 unsigned nxe:1; 266 unsigned cr0_wp:1; 267 unsigned smep_andnot_wp:1; 268 unsigned smap_andnot_wp:1; 269 unsigned ad_disabled:1; 270 unsigned guest_mode:1; 271 unsigned :6; 272 273 /* 274 * This is left at the top of the word so that 275 * kvm_memslots_for_spte_role can extract it with a 276 * simple shift. While there is room, give it a whole 277 * byte so it is also faster to load it from memory. 278 */ 279 unsigned smm:8; 280 }; 281 }; 282 283 union kvm_mmu_extended_role { 284 /* 285 * This structure complements kvm_mmu_page_role caching everything needed for 286 * MMU configuration. If nothing in both these structures changed, MMU 287 * re-configuration can be skipped. @valid bit is set on first usage so we don't 288 * treat all-zero structure as valid data. 289 */ 290 u32 word; 291 struct { 292 unsigned int valid:1; 293 unsigned int execonly:1; 294 unsigned int cr0_pg:1; 295 unsigned int cr4_pae:1; 296 unsigned int cr4_pse:1; 297 unsigned int cr4_pke:1; 298 unsigned int cr4_smap:1; 299 unsigned int cr4_smep:1; 300 unsigned int cr4_la57:1; 301 unsigned int maxphyaddr:6; 302 }; 303 }; 304 305 union kvm_mmu_role { 306 u64 as_u64; 307 struct { 308 union kvm_mmu_page_role base; 309 union kvm_mmu_extended_role ext; 310 }; 311 }; 312 313 struct kvm_rmap_head { 314 unsigned long val; 315 }; 316 317 struct kvm_mmu_page { 318 struct list_head link; 319 struct hlist_node hash_link; 320 bool unsync; 321 bool mmio_cached; 322 323 /* 324 * The following two entries are used to key the shadow page in the 325 * hash table. 326 */ 327 union kvm_mmu_page_role role; 328 gfn_t gfn; 329 330 u64 *spt; 331 /* hold the gfn of each spte inside spt */ 332 gfn_t *gfns; 333 int root_count; /* Currently serving as active root */ 334 unsigned int unsync_children; 335 struct kvm_rmap_head parent_ptes; /* rmap pointers to parent sptes */ 336 DECLARE_BITMAP(unsync_child_bitmap, 512); 337 338 #ifdef CONFIG_X86_32 339 /* 340 * Used out of the mmu-lock to avoid reading spte values while an 341 * update is in progress; see the comments in __get_spte_lockless(). 342 */ 343 int clear_spte_count; 344 #endif 345 346 /* Number of writes since the last time traversal visited this page. */ 347 atomic_t write_flooding_count; 348 }; 349 350 struct kvm_pio_request { 351 unsigned long linear_rip; 352 unsigned long count; 353 int in; 354 int port; 355 int size; 356 }; 357 358 #define PT64_ROOT_MAX_LEVEL 5 359 360 struct rsvd_bits_validate { 361 u64 rsvd_bits_mask[2][PT64_ROOT_MAX_LEVEL]; 362 u64 bad_mt_xwr; 363 }; 364 365 struct kvm_mmu_root_info { 366 gpa_t cr3; 367 hpa_t hpa; 368 }; 369 370 #define KVM_MMU_ROOT_INFO_INVALID \ 371 ((struct kvm_mmu_root_info) { .cr3 = INVALID_PAGE, .hpa = INVALID_PAGE }) 372 373 #define KVM_MMU_NUM_PREV_ROOTS 3 374 375 /* 376 * x86 supports 4 paging modes (5-level 64-bit, 4-level 64-bit, 3-level 32-bit, 377 * and 2-level 32-bit). The kvm_mmu structure abstracts the details of the 378 * current mmu mode. 379 */ 380 struct kvm_mmu { 381 void (*set_cr3)(struct kvm_vcpu *vcpu, unsigned long root); 382 unsigned long (*get_cr3)(struct kvm_vcpu *vcpu); 383 u64 (*get_pdptr)(struct kvm_vcpu *vcpu, int index); 384 int (*page_fault)(struct kvm_vcpu *vcpu, gva_t gva, u32 err, 385 bool prefault); 386 void (*inject_page_fault)(struct kvm_vcpu *vcpu, 387 struct x86_exception *fault); 388 gpa_t (*gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t gva, u32 access, 389 struct x86_exception *exception); 390 gpa_t (*translate_gpa)(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access, 391 struct x86_exception *exception); 392 int (*sync_page)(struct kvm_vcpu *vcpu, 393 struct kvm_mmu_page *sp); 394 void (*invlpg)(struct kvm_vcpu *vcpu, gva_t gva, hpa_t root_hpa); 395 void (*update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, 396 u64 *spte, const void *pte); 397 hpa_t root_hpa; 398 gpa_t root_cr3; 399 union kvm_mmu_role mmu_role; 400 u8 root_level; 401 u8 shadow_root_level; 402 u8 ept_ad; 403 bool direct_map; 404 struct kvm_mmu_root_info prev_roots[KVM_MMU_NUM_PREV_ROOTS]; 405 406 /* 407 * Bitmap; bit set = permission fault 408 * Byte index: page fault error code [4:1] 409 * Bit index: pte permissions in ACC_* format 410 */ 411 u8 permissions[16]; 412 413 /* 414 * The pkru_mask indicates if protection key checks are needed. It 415 * consists of 16 domains indexed by page fault error code bits [4:1], 416 * with PFEC.RSVD replaced by ACC_USER_MASK from the page tables. 417 * Each domain has 2 bits which are ANDed with AD and WD from PKRU. 418 */ 419 u32 pkru_mask; 420 421 u64 *pae_root; 422 u64 *lm_root; 423 424 /* 425 * check zero bits on shadow page table entries, these 426 * bits include not only hardware reserved bits but also 427 * the bits spte never used. 428 */ 429 struct rsvd_bits_validate shadow_zero_check; 430 431 struct rsvd_bits_validate guest_rsvd_check; 432 433 /* Can have large pages at levels 2..last_nonleaf_level-1. */ 434 u8 last_nonleaf_level; 435 436 bool nx; 437 438 u64 pdptrs[4]; /* pae */ 439 }; 440 441 struct kvm_tlb_range { 442 u64 start_gfn; 443 u64 pages; 444 }; 445 446 enum pmc_type { 447 KVM_PMC_GP = 0, 448 KVM_PMC_FIXED, 449 }; 450 451 struct kvm_pmc { 452 enum pmc_type type; 453 u8 idx; 454 u64 counter; 455 u64 eventsel; 456 struct perf_event *perf_event; 457 struct kvm_vcpu *vcpu; 458 }; 459 460 struct kvm_pmu { 461 unsigned nr_arch_gp_counters; 462 unsigned nr_arch_fixed_counters; 463 unsigned available_event_types; 464 u64 fixed_ctr_ctrl; 465 u64 global_ctrl; 466 u64 global_status; 467 u64 global_ovf_ctrl; 468 u64 counter_bitmask[2]; 469 u64 global_ctrl_mask; 470 u64 global_ovf_ctrl_mask; 471 u64 reserved_bits; 472 u8 version; 473 struct kvm_pmc gp_counters[INTEL_PMC_MAX_GENERIC]; 474 struct kvm_pmc fixed_counters[INTEL_PMC_MAX_FIXED]; 475 struct irq_work irq_work; 476 u64 reprogram_pmi; 477 }; 478 479 struct kvm_pmu_ops; 480 481 enum { 482 KVM_DEBUGREG_BP_ENABLED = 1, 483 KVM_DEBUGREG_WONT_EXIT = 2, 484 KVM_DEBUGREG_RELOAD = 4, 485 }; 486 487 struct kvm_mtrr_range { 488 u64 base; 489 u64 mask; 490 struct list_head node; 491 }; 492 493 struct kvm_mtrr { 494 struct kvm_mtrr_range var_ranges[KVM_NR_VAR_MTRR]; 495 mtrr_type fixed_ranges[KVM_NR_FIXED_MTRR_REGION]; 496 u64 deftype; 497 498 struct list_head head; 499 }; 500 501 /* Hyper-V SynIC timer */ 502 struct kvm_vcpu_hv_stimer { 503 struct hrtimer timer; 504 int index; 505 union hv_stimer_config config; 506 u64 count; 507 u64 exp_time; 508 struct hv_message msg; 509 bool msg_pending; 510 }; 511 512 /* Hyper-V synthetic interrupt controller (SynIC)*/ 513 struct kvm_vcpu_hv_synic { 514 u64 version; 515 u64 control; 516 u64 msg_page; 517 u64 evt_page; 518 atomic64_t sint[HV_SYNIC_SINT_COUNT]; 519 atomic_t sint_to_gsi[HV_SYNIC_SINT_COUNT]; 520 DECLARE_BITMAP(auto_eoi_bitmap, 256); 521 DECLARE_BITMAP(vec_bitmap, 256); 522 bool active; 523 bool dont_zero_synic_pages; 524 }; 525 526 /* Hyper-V per vcpu emulation context */ 527 struct kvm_vcpu_hv { 528 u32 vp_index; 529 u64 hv_vapic; 530 s64 runtime_offset; 531 struct kvm_vcpu_hv_synic synic; 532 struct kvm_hyperv_exit exit; 533 struct kvm_vcpu_hv_stimer stimer[HV_SYNIC_STIMER_COUNT]; 534 DECLARE_BITMAP(stimer_pending_bitmap, HV_SYNIC_STIMER_COUNT); 535 cpumask_t tlb_flush; 536 }; 537 538 struct kvm_vcpu_arch { 539 /* 540 * rip and regs accesses must go through 541 * kvm_{register,rip}_{read,write} functions. 542 */ 543 unsigned long regs[NR_VCPU_REGS]; 544 u32 regs_avail; 545 u32 regs_dirty; 546 547 unsigned long cr0; 548 unsigned long cr0_guest_owned_bits; 549 unsigned long cr2; 550 unsigned long cr3; 551 unsigned long cr4; 552 unsigned long cr4_guest_owned_bits; 553 unsigned long cr8; 554 u32 pkru; 555 u32 hflags; 556 u64 efer; 557 u64 apic_base; 558 struct kvm_lapic *apic; /* kernel irqchip context */ 559 bool apicv_active; 560 bool load_eoi_exitmap_pending; 561 DECLARE_BITMAP(ioapic_handled_vectors, 256); 562 unsigned long apic_attention; 563 int32_t apic_arb_prio; 564 int mp_state; 565 u64 ia32_misc_enable_msr; 566 u64 smbase; 567 u64 smi_count; 568 bool tpr_access_reporting; 569 u64 ia32_xss; 570 u64 microcode_version; 571 u64 arch_capabilities; 572 573 /* 574 * Paging state of the vcpu 575 * 576 * If the vcpu runs in guest mode with two level paging this still saves 577 * the paging mode of the l1 guest. This context is always used to 578 * handle faults. 579 */ 580 struct kvm_mmu *mmu; 581 582 /* Non-nested MMU for L1 */ 583 struct kvm_mmu root_mmu; 584 585 /* L1 MMU when running nested */ 586 struct kvm_mmu guest_mmu; 587 588 /* 589 * Paging state of an L2 guest (used for nested npt) 590 * 591 * This context will save all necessary information to walk page tables 592 * of the an L2 guest. This context is only initialized for page table 593 * walking and not for faulting since we never handle l2 page faults on 594 * the host. 595 */ 596 struct kvm_mmu nested_mmu; 597 598 /* 599 * Pointer to the mmu context currently used for 600 * gva_to_gpa translations. 601 */ 602 struct kvm_mmu *walk_mmu; 603 604 struct kvm_mmu_memory_cache mmu_pte_list_desc_cache; 605 struct kvm_mmu_memory_cache mmu_page_cache; 606 struct kvm_mmu_memory_cache mmu_page_header_cache; 607 608 /* 609 * QEMU userspace and the guest each have their own FPU state. 610 * In vcpu_run, we switch between the user and guest FPU contexts. 611 * While running a VCPU, the VCPU thread will have the guest FPU 612 * context. 613 * 614 * Note that while the PKRU state lives inside the fpu registers, 615 * it is switched out separately at VMENTER and VMEXIT time. The 616 * "guest_fpu" state here contains the guest FPU context, with the 617 * host PRKU bits. 618 */ 619 struct fpu *user_fpu; 620 struct fpu *guest_fpu; 621 622 u64 xcr0; 623 u64 guest_supported_xcr0; 624 u32 guest_xstate_size; 625 626 struct kvm_pio_request pio; 627 void *pio_data; 628 629 u8 event_exit_inst_len; 630 631 struct kvm_queued_exception { 632 bool pending; 633 bool injected; 634 bool has_error_code; 635 u8 nr; 636 u32 error_code; 637 unsigned long payload; 638 bool has_payload; 639 u8 nested_apf; 640 } exception; 641 642 struct kvm_queued_interrupt { 643 bool injected; 644 bool soft; 645 u8 nr; 646 } interrupt; 647 648 int halt_request; /* real mode on Intel only */ 649 650 int cpuid_nent; 651 struct kvm_cpuid_entry2 cpuid_entries[KVM_MAX_CPUID_ENTRIES]; 652 653 int maxphyaddr; 654 655 /* emulate context */ 656 657 struct x86_emulate_ctxt emulate_ctxt; 658 bool emulate_regs_need_sync_to_vcpu; 659 bool emulate_regs_need_sync_from_vcpu; 660 int (*complete_userspace_io)(struct kvm_vcpu *vcpu); 661 662 gpa_t time; 663 struct pvclock_vcpu_time_info hv_clock; 664 unsigned int hw_tsc_khz; 665 struct gfn_to_hva_cache pv_time; 666 bool pv_time_enabled; 667 /* set guest stopped flag in pvclock flags field */ 668 bool pvclock_set_guest_stopped_request; 669 670 struct { 671 u64 msr_val; 672 u64 last_steal; 673 struct gfn_to_hva_cache stime; 674 struct kvm_steal_time steal; 675 } st; 676 677 u64 tsc_offset; 678 u64 last_guest_tsc; 679 u64 last_host_tsc; 680 u64 tsc_offset_adjustment; 681 u64 this_tsc_nsec; 682 u64 this_tsc_write; 683 u64 this_tsc_generation; 684 bool tsc_catchup; 685 bool tsc_always_catchup; 686 s8 virtual_tsc_shift; 687 u32 virtual_tsc_mult; 688 u32 virtual_tsc_khz; 689 s64 ia32_tsc_adjust_msr; 690 u64 msr_ia32_power_ctl; 691 u64 tsc_scaling_ratio; 692 693 atomic_t nmi_queued; /* unprocessed asynchronous NMIs */ 694 unsigned nmi_pending; /* NMI queued after currently running handler */ 695 bool nmi_injected; /* Trying to inject an NMI this entry */ 696 bool smi_pending; /* SMI queued after currently running handler */ 697 698 struct kvm_mtrr mtrr_state; 699 u64 pat; 700 701 unsigned switch_db_regs; 702 unsigned long db[KVM_NR_DB_REGS]; 703 unsigned long dr6; 704 unsigned long dr7; 705 unsigned long eff_db[KVM_NR_DB_REGS]; 706 unsigned long guest_debug_dr7; 707 u64 msr_platform_info; 708 u64 msr_misc_features_enables; 709 710 u64 mcg_cap; 711 u64 mcg_status; 712 u64 mcg_ctl; 713 u64 mcg_ext_ctl; 714 u64 *mce_banks; 715 716 /* Cache MMIO info */ 717 u64 mmio_gva; 718 unsigned access; 719 gfn_t mmio_gfn; 720 u64 mmio_gen; 721 722 struct kvm_pmu pmu; 723 724 /* used for guest single stepping over the given code position */ 725 unsigned long singlestep_rip; 726 727 struct kvm_vcpu_hv hyperv; 728 729 cpumask_var_t wbinvd_dirty_mask; 730 731 unsigned long last_retry_eip; 732 unsigned long last_retry_addr; 733 734 struct { 735 bool halted; 736 gfn_t gfns[roundup_pow_of_two(ASYNC_PF_PER_VCPU)]; 737 struct gfn_to_hva_cache data; 738 u64 msr_val; 739 u32 id; 740 bool send_user_only; 741 u32 host_apf_reason; 742 unsigned long nested_apf_token; 743 bool delivery_as_pf_vmexit; 744 } apf; 745 746 /* OSVW MSRs (AMD only) */ 747 struct { 748 u64 length; 749 u64 status; 750 } osvw; 751 752 struct { 753 u64 msr_val; 754 struct gfn_to_hva_cache data; 755 } pv_eoi; 756 757 u64 msr_kvm_poll_control; 758 759 /* 760 * Indicate whether the access faults on its page table in guest 761 * which is set when fix page fault and used to detect unhandeable 762 * instruction. 763 */ 764 bool write_fault_to_shadow_pgtable; 765 766 /* set at EPT violation at this point */ 767 unsigned long exit_qualification; 768 769 /* pv related host specific info */ 770 struct { 771 bool pv_unhalted; 772 } pv; 773 774 int pending_ioapic_eoi; 775 int pending_external_vector; 776 777 /* GPA available */ 778 bool gpa_available; 779 gpa_t gpa_val; 780 781 /* be preempted when it's in kernel-mode(cpl=0) */ 782 bool preempted_in_kernel; 783 784 /* Flush the L1 Data cache for L1TF mitigation on VMENTER */ 785 bool l1tf_flush_l1d; 786 787 /* AMD MSRC001_0015 Hardware Configuration */ 788 u64 msr_hwcr; 789 }; 790 791 struct kvm_lpage_info { 792 int disallow_lpage; 793 }; 794 795 struct kvm_arch_memory_slot { 796 struct kvm_rmap_head *rmap[KVM_NR_PAGE_SIZES]; 797 struct kvm_lpage_info *lpage_info[KVM_NR_PAGE_SIZES - 1]; 798 unsigned short *gfn_track[KVM_PAGE_TRACK_MAX]; 799 }; 800 801 /* 802 * We use as the mode the number of bits allocated in the LDR for the 803 * logical processor ID. It happens that these are all powers of two. 804 * This makes it is very easy to detect cases where the APICs are 805 * configured for multiple modes; in that case, we cannot use the map and 806 * hence cannot use kvm_irq_delivery_to_apic_fast either. 807 */ 808 #define KVM_APIC_MODE_XAPIC_CLUSTER 4 809 #define KVM_APIC_MODE_XAPIC_FLAT 8 810 #define KVM_APIC_MODE_X2APIC 16 811 812 struct kvm_apic_map { 813 struct rcu_head rcu; 814 u8 mode; 815 u32 max_apic_id; 816 union { 817 struct kvm_lapic *xapic_flat_map[8]; 818 struct kvm_lapic *xapic_cluster_map[16][4]; 819 }; 820 struct kvm_lapic *phys_map[]; 821 }; 822 823 /* Hyper-V emulation context */ 824 struct kvm_hv { 825 struct mutex hv_lock; 826 u64 hv_guest_os_id; 827 u64 hv_hypercall; 828 u64 hv_tsc_page; 829 830 /* Hyper-v based guest crash (NT kernel bugcheck) parameters */ 831 u64 hv_crash_param[HV_X64_MSR_CRASH_PARAMS]; 832 u64 hv_crash_ctl; 833 834 HV_REFERENCE_TSC_PAGE tsc_ref; 835 836 struct idr conn_to_evt; 837 838 u64 hv_reenlightenment_control; 839 u64 hv_tsc_emulation_control; 840 u64 hv_tsc_emulation_status; 841 842 /* How many vCPUs have VP index != vCPU index */ 843 atomic_t num_mismatched_vp_indexes; 844 }; 845 846 enum kvm_irqchip_mode { 847 KVM_IRQCHIP_NONE, 848 KVM_IRQCHIP_KERNEL, /* created with KVM_CREATE_IRQCHIP */ 849 KVM_IRQCHIP_SPLIT, /* created with KVM_CAP_SPLIT_IRQCHIP */ 850 }; 851 852 struct kvm_arch { 853 unsigned long n_used_mmu_pages; 854 unsigned long n_requested_mmu_pages; 855 unsigned long n_max_mmu_pages; 856 unsigned int indirect_shadow_pages; 857 struct hlist_head mmu_page_hash[KVM_NUM_MMU_PAGES]; 858 /* 859 * Hash table of struct kvm_mmu_page. 860 */ 861 struct list_head active_mmu_pages; 862 struct kvm_page_track_notifier_node mmu_sp_tracker; 863 struct kvm_page_track_notifier_head track_notifier_head; 864 865 struct list_head assigned_dev_head; 866 struct iommu_domain *iommu_domain; 867 bool iommu_noncoherent; 868 #define __KVM_HAVE_ARCH_NONCOHERENT_DMA 869 atomic_t noncoherent_dma_count; 870 #define __KVM_HAVE_ARCH_ASSIGNED_DEVICE 871 atomic_t assigned_device_count; 872 struct kvm_pic *vpic; 873 struct kvm_ioapic *vioapic; 874 struct kvm_pit *vpit; 875 atomic_t vapics_in_nmi_mode; 876 struct mutex apic_map_lock; 877 struct kvm_apic_map *apic_map; 878 879 bool apic_access_page_done; 880 881 gpa_t wall_clock; 882 883 bool mwait_in_guest; 884 bool hlt_in_guest; 885 bool pause_in_guest; 886 bool cstate_in_guest; 887 888 unsigned long irq_sources_bitmap; 889 s64 kvmclock_offset; 890 raw_spinlock_t tsc_write_lock; 891 u64 last_tsc_nsec; 892 u64 last_tsc_write; 893 u32 last_tsc_khz; 894 u64 cur_tsc_nsec; 895 u64 cur_tsc_write; 896 u64 cur_tsc_offset; 897 u64 cur_tsc_generation; 898 int nr_vcpus_matched_tsc; 899 900 spinlock_t pvclock_gtod_sync_lock; 901 bool use_master_clock; 902 u64 master_kernel_ns; 903 u64 master_cycle_now; 904 struct delayed_work kvmclock_update_work; 905 struct delayed_work kvmclock_sync_work; 906 907 struct kvm_xen_hvm_config xen_hvm_config; 908 909 /* reads protected by irq_srcu, writes by irq_lock */ 910 struct hlist_head mask_notifier_list; 911 912 struct kvm_hv hyperv; 913 914 #ifdef CONFIG_KVM_MMU_AUDIT 915 int audit_point; 916 #endif 917 918 bool backwards_tsc_observed; 919 bool boot_vcpu_runs_old_kvmclock; 920 u32 bsp_vcpu_id; 921 922 u64 disabled_quirks; 923 924 enum kvm_irqchip_mode irqchip_mode; 925 u8 nr_reserved_ioapic_pins; 926 927 bool disabled_lapic_found; 928 929 bool x2apic_format; 930 bool x2apic_broadcast_quirk_disabled; 931 932 bool guest_can_read_msr_platform_info; 933 bool exception_payload_enabled; 934 935 struct kvm_pmu_event_filter *pmu_event_filter; 936 }; 937 938 struct kvm_vm_stat { 939 ulong mmu_shadow_zapped; 940 ulong mmu_pte_write; 941 ulong mmu_pte_updated; 942 ulong mmu_pde_zapped; 943 ulong mmu_flooded; 944 ulong mmu_recycled; 945 ulong mmu_cache_miss; 946 ulong mmu_unsync; 947 ulong remote_tlb_flush; 948 ulong lpages; 949 ulong max_mmu_page_hash_collisions; 950 }; 951 952 struct kvm_vcpu_stat { 953 u64 pf_fixed; 954 u64 pf_guest; 955 u64 tlb_flush; 956 u64 invlpg; 957 958 u64 exits; 959 u64 io_exits; 960 u64 mmio_exits; 961 u64 signal_exits; 962 u64 irq_window_exits; 963 u64 nmi_window_exits; 964 u64 l1d_flush; 965 u64 halt_exits; 966 u64 halt_successful_poll; 967 u64 halt_attempted_poll; 968 u64 halt_poll_invalid; 969 u64 halt_wakeup; 970 u64 request_irq_exits; 971 u64 irq_exits; 972 u64 host_state_reload; 973 u64 fpu_reload; 974 u64 insn_emulation; 975 u64 insn_emulation_fail; 976 u64 hypercalls; 977 u64 irq_injections; 978 u64 nmi_injections; 979 u64 req_event; 980 }; 981 982 struct x86_instruction_info; 983 984 struct msr_data { 985 bool host_initiated; 986 u32 index; 987 u64 data; 988 }; 989 990 struct kvm_lapic_irq { 991 u32 vector; 992 u16 delivery_mode; 993 u16 dest_mode; 994 bool level; 995 u16 trig_mode; 996 u32 shorthand; 997 u32 dest_id; 998 bool msi_redir_hint; 999 }; 1000 1001 struct kvm_x86_ops { 1002 int (*cpu_has_kvm_support)(void); /* __init */ 1003 int (*disabled_by_bios)(void); /* __init */ 1004 int (*hardware_enable)(void); 1005 void (*hardware_disable)(void); 1006 int (*check_processor_compatibility)(void);/* __init */ 1007 int (*hardware_setup)(void); /* __init */ 1008 void (*hardware_unsetup)(void); /* __exit */ 1009 bool (*cpu_has_accelerated_tpr)(void); 1010 bool (*has_emulated_msr)(int index); 1011 void (*cpuid_update)(struct kvm_vcpu *vcpu); 1012 1013 struct kvm *(*vm_alloc)(void); 1014 void (*vm_free)(struct kvm *); 1015 int (*vm_init)(struct kvm *kvm); 1016 void (*vm_destroy)(struct kvm *kvm); 1017 1018 /* Create, but do not attach this VCPU */ 1019 struct kvm_vcpu *(*vcpu_create)(struct kvm *kvm, unsigned id); 1020 void (*vcpu_free)(struct kvm_vcpu *vcpu); 1021 void (*vcpu_reset)(struct kvm_vcpu *vcpu, bool init_event); 1022 1023 void (*prepare_guest_switch)(struct kvm_vcpu *vcpu); 1024 void (*vcpu_load)(struct kvm_vcpu *vcpu, int cpu); 1025 void (*vcpu_put)(struct kvm_vcpu *vcpu); 1026 1027 void (*update_bp_intercept)(struct kvm_vcpu *vcpu); 1028 int (*get_msr)(struct kvm_vcpu *vcpu, struct msr_data *msr); 1029 int (*set_msr)(struct kvm_vcpu *vcpu, struct msr_data *msr); 1030 u64 (*get_segment_base)(struct kvm_vcpu *vcpu, int seg); 1031 void (*get_segment)(struct kvm_vcpu *vcpu, 1032 struct kvm_segment *var, int seg); 1033 int (*get_cpl)(struct kvm_vcpu *vcpu); 1034 void (*set_segment)(struct kvm_vcpu *vcpu, 1035 struct kvm_segment *var, int seg); 1036 void (*get_cs_db_l_bits)(struct kvm_vcpu *vcpu, int *db, int *l); 1037 void (*decache_cr0_guest_bits)(struct kvm_vcpu *vcpu); 1038 void (*decache_cr3)(struct kvm_vcpu *vcpu); 1039 void (*decache_cr4_guest_bits)(struct kvm_vcpu *vcpu); 1040 void (*set_cr0)(struct kvm_vcpu *vcpu, unsigned long cr0); 1041 void (*set_cr3)(struct kvm_vcpu *vcpu, unsigned long cr3); 1042 int (*set_cr4)(struct kvm_vcpu *vcpu, unsigned long cr4); 1043 void (*set_efer)(struct kvm_vcpu *vcpu, u64 efer); 1044 void (*get_idt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt); 1045 void (*set_idt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt); 1046 void (*get_gdt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt); 1047 void (*set_gdt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt); 1048 u64 (*get_dr6)(struct kvm_vcpu *vcpu); 1049 void (*set_dr6)(struct kvm_vcpu *vcpu, unsigned long value); 1050 void (*sync_dirty_debug_regs)(struct kvm_vcpu *vcpu); 1051 void (*set_dr7)(struct kvm_vcpu *vcpu, unsigned long value); 1052 void (*cache_reg)(struct kvm_vcpu *vcpu, enum kvm_reg reg); 1053 unsigned long (*get_rflags)(struct kvm_vcpu *vcpu); 1054 void (*set_rflags)(struct kvm_vcpu *vcpu, unsigned long rflags); 1055 1056 void (*tlb_flush)(struct kvm_vcpu *vcpu, bool invalidate_gpa); 1057 int (*tlb_remote_flush)(struct kvm *kvm); 1058 int (*tlb_remote_flush_with_range)(struct kvm *kvm, 1059 struct kvm_tlb_range *range); 1060 1061 /* 1062 * Flush any TLB entries associated with the given GVA. 1063 * Does not need to flush GPA->HPA mappings. 1064 * Can potentially get non-canonical addresses through INVLPGs, which 1065 * the implementation may choose to ignore if appropriate. 1066 */ 1067 void (*tlb_flush_gva)(struct kvm_vcpu *vcpu, gva_t addr); 1068 1069 void (*run)(struct kvm_vcpu *vcpu); 1070 int (*handle_exit)(struct kvm_vcpu *vcpu); 1071 void (*skip_emulated_instruction)(struct kvm_vcpu *vcpu); 1072 void (*set_interrupt_shadow)(struct kvm_vcpu *vcpu, int mask); 1073 u32 (*get_interrupt_shadow)(struct kvm_vcpu *vcpu); 1074 void (*patch_hypercall)(struct kvm_vcpu *vcpu, 1075 unsigned char *hypercall_addr); 1076 void (*set_irq)(struct kvm_vcpu *vcpu); 1077 void (*set_nmi)(struct kvm_vcpu *vcpu); 1078 void (*queue_exception)(struct kvm_vcpu *vcpu); 1079 void (*cancel_injection)(struct kvm_vcpu *vcpu); 1080 int (*interrupt_allowed)(struct kvm_vcpu *vcpu); 1081 int (*nmi_allowed)(struct kvm_vcpu *vcpu); 1082 bool (*get_nmi_mask)(struct kvm_vcpu *vcpu); 1083 void (*set_nmi_mask)(struct kvm_vcpu *vcpu, bool masked); 1084 void (*enable_nmi_window)(struct kvm_vcpu *vcpu); 1085 void (*enable_irq_window)(struct kvm_vcpu *vcpu); 1086 void (*update_cr8_intercept)(struct kvm_vcpu *vcpu, int tpr, int irr); 1087 bool (*get_enable_apicv)(struct kvm_vcpu *vcpu); 1088 void (*refresh_apicv_exec_ctrl)(struct kvm_vcpu *vcpu); 1089 void (*hwapic_irr_update)(struct kvm_vcpu *vcpu, int max_irr); 1090 void (*hwapic_isr_update)(struct kvm_vcpu *vcpu, int isr); 1091 bool (*guest_apic_has_interrupt)(struct kvm_vcpu *vcpu); 1092 void (*load_eoi_exitmap)(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap); 1093 void (*set_virtual_apic_mode)(struct kvm_vcpu *vcpu); 1094 void (*set_apic_access_page_addr)(struct kvm_vcpu *vcpu, hpa_t hpa); 1095 void (*deliver_posted_interrupt)(struct kvm_vcpu *vcpu, int vector); 1096 int (*sync_pir_to_irr)(struct kvm_vcpu *vcpu); 1097 int (*set_tss_addr)(struct kvm *kvm, unsigned int addr); 1098 int (*set_identity_map_addr)(struct kvm *kvm, u64 ident_addr); 1099 int (*get_tdp_level)(struct kvm_vcpu *vcpu); 1100 u64 (*get_mt_mask)(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio); 1101 int (*get_lpage_level)(void); 1102 bool (*rdtscp_supported)(void); 1103 bool (*invpcid_supported)(void); 1104 1105 void (*set_tdp_cr3)(struct kvm_vcpu *vcpu, unsigned long cr3); 1106 1107 void (*set_supported_cpuid)(u32 func, struct kvm_cpuid_entry2 *entry); 1108 1109 bool (*has_wbinvd_exit)(void); 1110 1111 u64 (*read_l1_tsc_offset)(struct kvm_vcpu *vcpu); 1112 /* Returns actual tsc_offset set in active VMCS */ 1113 u64 (*write_l1_tsc_offset)(struct kvm_vcpu *vcpu, u64 offset); 1114 1115 void (*get_exit_info)(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2); 1116 1117 int (*check_intercept)(struct kvm_vcpu *vcpu, 1118 struct x86_instruction_info *info, 1119 enum x86_intercept_stage stage); 1120 void (*handle_exit_irqoff)(struct kvm_vcpu *vcpu); 1121 bool (*mpx_supported)(void); 1122 bool (*xsaves_supported)(void); 1123 bool (*umip_emulated)(void); 1124 bool (*pt_supported)(void); 1125 1126 int (*check_nested_events)(struct kvm_vcpu *vcpu, bool external_intr); 1127 void (*request_immediate_exit)(struct kvm_vcpu *vcpu); 1128 1129 void (*sched_in)(struct kvm_vcpu *kvm, int cpu); 1130 1131 /* 1132 * Arch-specific dirty logging hooks. These hooks are only supposed to 1133 * be valid if the specific arch has hardware-accelerated dirty logging 1134 * mechanism. Currently only for PML on VMX. 1135 * 1136 * - slot_enable_log_dirty: 1137 * called when enabling log dirty mode for the slot. 1138 * - slot_disable_log_dirty: 1139 * called when disabling log dirty mode for the slot. 1140 * also called when slot is created with log dirty disabled. 1141 * - flush_log_dirty: 1142 * called before reporting dirty_bitmap to userspace. 1143 * - enable_log_dirty_pt_masked: 1144 * called when reenabling log dirty for the GFNs in the mask after 1145 * corresponding bits are cleared in slot->dirty_bitmap. 1146 */ 1147 void (*slot_enable_log_dirty)(struct kvm *kvm, 1148 struct kvm_memory_slot *slot); 1149 void (*slot_disable_log_dirty)(struct kvm *kvm, 1150 struct kvm_memory_slot *slot); 1151 void (*flush_log_dirty)(struct kvm *kvm); 1152 void (*enable_log_dirty_pt_masked)(struct kvm *kvm, 1153 struct kvm_memory_slot *slot, 1154 gfn_t offset, unsigned long mask); 1155 int (*write_log_dirty)(struct kvm_vcpu *vcpu); 1156 1157 /* pmu operations of sub-arch */ 1158 const struct kvm_pmu_ops *pmu_ops; 1159 1160 /* 1161 * Architecture specific hooks for vCPU blocking due to 1162 * HLT instruction. 1163 * Returns for .pre_block(): 1164 * - 0 means continue to block the vCPU. 1165 * - 1 means we cannot block the vCPU since some event 1166 * happens during this period, such as, 'ON' bit in 1167 * posted-interrupts descriptor is set. 1168 */ 1169 int (*pre_block)(struct kvm_vcpu *vcpu); 1170 void (*post_block)(struct kvm_vcpu *vcpu); 1171 1172 void (*vcpu_blocking)(struct kvm_vcpu *vcpu); 1173 void (*vcpu_unblocking)(struct kvm_vcpu *vcpu); 1174 1175 int (*update_pi_irte)(struct kvm *kvm, unsigned int host_irq, 1176 uint32_t guest_irq, bool set); 1177 void (*apicv_post_state_restore)(struct kvm_vcpu *vcpu); 1178 1179 int (*set_hv_timer)(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc, 1180 bool *expired); 1181 void (*cancel_hv_timer)(struct kvm_vcpu *vcpu); 1182 1183 void (*setup_mce)(struct kvm_vcpu *vcpu); 1184 1185 int (*get_nested_state)(struct kvm_vcpu *vcpu, 1186 struct kvm_nested_state __user *user_kvm_nested_state, 1187 unsigned user_data_size); 1188 int (*set_nested_state)(struct kvm_vcpu *vcpu, 1189 struct kvm_nested_state __user *user_kvm_nested_state, 1190 struct kvm_nested_state *kvm_state); 1191 void (*get_vmcs12_pages)(struct kvm_vcpu *vcpu); 1192 1193 int (*smi_allowed)(struct kvm_vcpu *vcpu); 1194 int (*pre_enter_smm)(struct kvm_vcpu *vcpu, char *smstate); 1195 int (*pre_leave_smm)(struct kvm_vcpu *vcpu, const char *smstate); 1196 int (*enable_smi_window)(struct kvm_vcpu *vcpu); 1197 1198 int (*mem_enc_op)(struct kvm *kvm, void __user *argp); 1199 int (*mem_enc_reg_region)(struct kvm *kvm, struct kvm_enc_region *argp); 1200 int (*mem_enc_unreg_region)(struct kvm *kvm, struct kvm_enc_region *argp); 1201 1202 int (*get_msr_feature)(struct kvm_msr_entry *entry); 1203 1204 int (*nested_enable_evmcs)(struct kvm_vcpu *vcpu, 1205 uint16_t *vmcs_version); 1206 uint16_t (*nested_get_evmcs_version)(struct kvm_vcpu *vcpu); 1207 1208 bool (*need_emulation_on_page_fault)(struct kvm_vcpu *vcpu); 1209 }; 1210 1211 struct kvm_arch_async_pf { 1212 u32 token; 1213 gfn_t gfn; 1214 unsigned long cr3; 1215 bool direct_map; 1216 }; 1217 1218 extern struct kvm_x86_ops *kvm_x86_ops; 1219 extern struct kmem_cache *x86_fpu_cache; 1220 1221 #define __KVM_HAVE_ARCH_VM_ALLOC 1222 static inline struct kvm *kvm_arch_alloc_vm(void) 1223 { 1224 return kvm_x86_ops->vm_alloc(); 1225 } 1226 1227 static inline void kvm_arch_free_vm(struct kvm *kvm) 1228 { 1229 return kvm_x86_ops->vm_free(kvm); 1230 } 1231 1232 #define __KVM_HAVE_ARCH_FLUSH_REMOTE_TLB 1233 static inline int kvm_arch_flush_remote_tlb(struct kvm *kvm) 1234 { 1235 if (kvm_x86_ops->tlb_remote_flush && 1236 !kvm_x86_ops->tlb_remote_flush(kvm)) 1237 return 0; 1238 else 1239 return -ENOTSUPP; 1240 } 1241 1242 int kvm_mmu_module_init(void); 1243 void kvm_mmu_module_exit(void); 1244 1245 void kvm_mmu_destroy(struct kvm_vcpu *vcpu); 1246 int kvm_mmu_create(struct kvm_vcpu *vcpu); 1247 void kvm_mmu_init_vm(struct kvm *kvm); 1248 void kvm_mmu_uninit_vm(struct kvm *kvm); 1249 void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask, 1250 u64 dirty_mask, u64 nx_mask, u64 x_mask, u64 p_mask, 1251 u64 acc_track_mask, u64 me_mask); 1252 1253 void kvm_mmu_reset_context(struct kvm_vcpu *vcpu); 1254 void kvm_mmu_slot_remove_write_access(struct kvm *kvm, 1255 struct kvm_memory_slot *memslot); 1256 void kvm_mmu_zap_collapsible_sptes(struct kvm *kvm, 1257 const struct kvm_memory_slot *memslot); 1258 void kvm_mmu_slot_leaf_clear_dirty(struct kvm *kvm, 1259 struct kvm_memory_slot *memslot); 1260 void kvm_mmu_slot_largepage_remove_write_access(struct kvm *kvm, 1261 struct kvm_memory_slot *memslot); 1262 void kvm_mmu_slot_set_dirty(struct kvm *kvm, 1263 struct kvm_memory_slot *memslot); 1264 void kvm_mmu_clear_dirty_pt_masked(struct kvm *kvm, 1265 struct kvm_memory_slot *slot, 1266 gfn_t gfn_offset, unsigned long mask); 1267 void kvm_mmu_zap_all(struct kvm *kvm); 1268 void kvm_mmu_invalidate_mmio_sptes(struct kvm *kvm, u64 gen); 1269 unsigned long kvm_mmu_calculate_default_mmu_pages(struct kvm *kvm); 1270 void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned long kvm_nr_mmu_pages); 1271 1272 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3); 1273 bool pdptrs_changed(struct kvm_vcpu *vcpu); 1274 1275 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa, 1276 const void *val, int bytes); 1277 1278 struct kvm_irq_mask_notifier { 1279 void (*func)(struct kvm_irq_mask_notifier *kimn, bool masked); 1280 int irq; 1281 struct hlist_node link; 1282 }; 1283 1284 void kvm_register_irq_mask_notifier(struct kvm *kvm, int irq, 1285 struct kvm_irq_mask_notifier *kimn); 1286 void kvm_unregister_irq_mask_notifier(struct kvm *kvm, int irq, 1287 struct kvm_irq_mask_notifier *kimn); 1288 void kvm_fire_mask_notifiers(struct kvm *kvm, unsigned irqchip, unsigned pin, 1289 bool mask); 1290 1291 extern bool tdp_enabled; 1292 1293 u64 vcpu_tsc_khz(struct kvm_vcpu *vcpu); 1294 1295 /* control of guest tsc rate supported? */ 1296 extern bool kvm_has_tsc_control; 1297 /* maximum supported tsc_khz for guests */ 1298 extern u32 kvm_max_guest_tsc_khz; 1299 /* number of bits of the fractional part of the TSC scaling ratio */ 1300 extern u8 kvm_tsc_scaling_ratio_frac_bits; 1301 /* maximum allowed value of TSC scaling ratio */ 1302 extern u64 kvm_max_tsc_scaling_ratio; 1303 /* 1ull << kvm_tsc_scaling_ratio_frac_bits */ 1304 extern u64 kvm_default_tsc_scaling_ratio; 1305 1306 extern u64 kvm_mce_cap_supported; 1307 1308 enum emulation_result { 1309 EMULATE_DONE, /* no further processing */ 1310 EMULATE_USER_EXIT, /* kvm_run ready for userspace exit */ 1311 EMULATE_FAIL, /* can't emulate this instruction */ 1312 }; 1313 1314 #define EMULTYPE_NO_DECODE (1 << 0) 1315 #define EMULTYPE_TRAP_UD (1 << 1) 1316 #define EMULTYPE_SKIP (1 << 2) 1317 #define EMULTYPE_ALLOW_RETRY (1 << 3) 1318 #define EMULTYPE_NO_UD_ON_FAIL (1 << 4) 1319 #define EMULTYPE_VMWARE (1 << 5) 1320 int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type); 1321 int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu, 1322 void *insn, int insn_len); 1323 1324 void kvm_enable_efer_bits(u64); 1325 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer); 1326 int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr); 1327 int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr); 1328 1329 struct x86_emulate_ctxt; 1330 1331 int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in); 1332 int kvm_emulate_cpuid(struct kvm_vcpu *vcpu); 1333 int kvm_emulate_halt(struct kvm_vcpu *vcpu); 1334 int kvm_vcpu_halt(struct kvm_vcpu *vcpu); 1335 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu); 1336 1337 void kvm_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg); 1338 int kvm_load_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector, int seg); 1339 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector); 1340 1341 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index, 1342 int reason, bool has_error_code, u32 error_code); 1343 1344 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0); 1345 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3); 1346 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4); 1347 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8); 1348 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val); 1349 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val); 1350 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu); 1351 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw); 1352 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l); 1353 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr); 1354 1355 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr); 1356 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr); 1357 1358 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu); 1359 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags); 1360 bool kvm_rdpmc(struct kvm_vcpu *vcpu); 1361 1362 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr); 1363 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code); 1364 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr); 1365 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code); 1366 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault); 1367 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, 1368 gfn_t gfn, void *data, int offset, int len, 1369 u32 access); 1370 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl); 1371 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr); 1372 1373 static inline int __kvm_irq_line_state(unsigned long *irq_state, 1374 int irq_source_id, int level) 1375 { 1376 /* Logical OR for level trig interrupt */ 1377 if (level) 1378 __set_bit(irq_source_id, irq_state); 1379 else 1380 __clear_bit(irq_source_id, irq_state); 1381 1382 return !!(*irq_state); 1383 } 1384 1385 #define KVM_MMU_ROOT_CURRENT BIT(0) 1386 #define KVM_MMU_ROOT_PREVIOUS(i) BIT(1+i) 1387 #define KVM_MMU_ROOTS_ALL (~0UL) 1388 1389 int kvm_pic_set_irq(struct kvm_pic *pic, int irq, int irq_source_id, int level); 1390 void kvm_pic_clear_all(struct kvm_pic *pic, int irq_source_id); 1391 1392 void kvm_inject_nmi(struct kvm_vcpu *vcpu); 1393 1394 int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn); 1395 int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva); 1396 void __kvm_mmu_free_some_pages(struct kvm_vcpu *vcpu); 1397 int kvm_mmu_load(struct kvm_vcpu *vcpu); 1398 void kvm_mmu_unload(struct kvm_vcpu *vcpu); 1399 void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu); 1400 void kvm_mmu_free_roots(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, 1401 ulong roots_to_free); 1402 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access, 1403 struct x86_exception *exception); 1404 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, 1405 struct x86_exception *exception); 1406 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, 1407 struct x86_exception *exception); 1408 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, 1409 struct x86_exception *exception); 1410 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, 1411 struct x86_exception *exception); 1412 1413 void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu); 1414 1415 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu); 1416 1417 int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t gva, u64 error_code, 1418 void *insn, int insn_len); 1419 void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva); 1420 void kvm_mmu_invpcid_gva(struct kvm_vcpu *vcpu, gva_t gva, unsigned long pcid); 1421 void kvm_mmu_new_cr3(struct kvm_vcpu *vcpu, gpa_t new_cr3, bool skip_tlb_flush); 1422 1423 void kvm_enable_tdp(void); 1424 void kvm_disable_tdp(void); 1425 1426 static inline gpa_t translate_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access, 1427 struct x86_exception *exception) 1428 { 1429 return gpa; 1430 } 1431 1432 static inline struct kvm_mmu_page *page_header(hpa_t shadow_page) 1433 { 1434 struct page *page = pfn_to_page(shadow_page >> PAGE_SHIFT); 1435 1436 return (struct kvm_mmu_page *)page_private(page); 1437 } 1438 1439 static inline u16 kvm_read_ldt(void) 1440 { 1441 u16 ldt; 1442 asm("sldt %0" : "=g"(ldt)); 1443 return ldt; 1444 } 1445 1446 static inline void kvm_load_ldt(u16 sel) 1447 { 1448 asm("lldt %0" : : "rm"(sel)); 1449 } 1450 1451 #ifdef CONFIG_X86_64 1452 static inline unsigned long read_msr(unsigned long msr) 1453 { 1454 u64 value; 1455 1456 rdmsrl(msr, value); 1457 return value; 1458 } 1459 #endif 1460 1461 static inline u32 get_rdx_init_val(void) 1462 { 1463 return 0x600; /* P6 family */ 1464 } 1465 1466 static inline void kvm_inject_gp(struct kvm_vcpu *vcpu, u32 error_code) 1467 { 1468 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code); 1469 } 1470 1471 #define TSS_IOPB_BASE_OFFSET 0x66 1472 #define TSS_BASE_SIZE 0x68 1473 #define TSS_IOPB_SIZE (65536 / 8) 1474 #define TSS_REDIRECTION_SIZE (256 / 8) 1475 #define RMODE_TSS_SIZE \ 1476 (TSS_BASE_SIZE + TSS_REDIRECTION_SIZE + TSS_IOPB_SIZE + 1) 1477 1478 enum { 1479 TASK_SWITCH_CALL = 0, 1480 TASK_SWITCH_IRET = 1, 1481 TASK_SWITCH_JMP = 2, 1482 TASK_SWITCH_GATE = 3, 1483 }; 1484 1485 #define HF_GIF_MASK (1 << 0) 1486 #define HF_HIF_MASK (1 << 1) 1487 #define HF_VINTR_MASK (1 << 2) 1488 #define HF_NMI_MASK (1 << 3) 1489 #define HF_IRET_MASK (1 << 4) 1490 #define HF_GUEST_MASK (1 << 5) /* VCPU is in guest-mode */ 1491 #define HF_SMM_MASK (1 << 6) 1492 #define HF_SMM_INSIDE_NMI_MASK (1 << 7) 1493 1494 #define __KVM_VCPU_MULTIPLE_ADDRESS_SPACE 1495 #define KVM_ADDRESS_SPACE_NUM 2 1496 1497 #define kvm_arch_vcpu_memslots_id(vcpu) ((vcpu)->arch.hflags & HF_SMM_MASK ? 1 : 0) 1498 #define kvm_memslots_for_spte_role(kvm, role) __kvm_memslots(kvm, (role).smm) 1499 1500 asmlinkage void __noreturn kvm_spurious_fault(void); 1501 1502 /* 1503 * Hardware virtualization extension instructions may fault if a 1504 * reboot turns off virtualization while processes are running. 1505 * Usually after catching the fault we just panic; during reboot 1506 * instead the instruction is ignored. 1507 */ 1508 #define ____kvm_handle_fault_on_reboot(insn, cleanup_insn) \ 1509 "666: \n\t" \ 1510 insn "\n\t" \ 1511 "jmp 668f \n\t" \ 1512 "667: \n\t" \ 1513 "call kvm_spurious_fault \n\t" \ 1514 "668: \n\t" \ 1515 ".pushsection .fixup, \"ax\" \n\t" \ 1516 "700: \n\t" \ 1517 cleanup_insn "\n\t" \ 1518 "cmpb $0, kvm_rebooting\n\t" \ 1519 "je 667b \n\t" \ 1520 "jmp 668b \n\t" \ 1521 ".popsection \n\t" \ 1522 _ASM_EXTABLE(666b, 700b) 1523 1524 #define __kvm_handle_fault_on_reboot(insn) \ 1525 ____kvm_handle_fault_on_reboot(insn, "") 1526 1527 #define KVM_ARCH_WANT_MMU_NOTIFIER 1528 int kvm_unmap_hva_range(struct kvm *kvm, unsigned long start, unsigned long end); 1529 int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end); 1530 int kvm_test_age_hva(struct kvm *kvm, unsigned long hva); 1531 int kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte); 1532 int kvm_cpu_has_injectable_intr(struct kvm_vcpu *v); 1533 int kvm_cpu_has_interrupt(struct kvm_vcpu *vcpu); 1534 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu); 1535 int kvm_cpu_get_interrupt(struct kvm_vcpu *v); 1536 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event); 1537 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu); 1538 1539 int kvm_pv_send_ipi(struct kvm *kvm, unsigned long ipi_bitmap_low, 1540 unsigned long ipi_bitmap_high, u32 min, 1541 unsigned long icr, int op_64_bit); 1542 1543 void kvm_define_shared_msr(unsigned index, u32 msr); 1544 int kvm_set_shared_msr(unsigned index, u64 val, u64 mask); 1545 1546 u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc); 1547 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc); 1548 1549 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu); 1550 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip); 1551 1552 void kvm_make_mclock_inprogress_request(struct kvm *kvm); 1553 void kvm_make_scan_ioapic_request(struct kvm *kvm); 1554 1555 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu, 1556 struct kvm_async_pf *work); 1557 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu, 1558 struct kvm_async_pf *work); 1559 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, 1560 struct kvm_async_pf *work); 1561 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu); 1562 extern bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn); 1563 1564 int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu); 1565 int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err); 1566 void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu); 1567 1568 int kvm_is_in_guest(void); 1569 1570 int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size); 1571 int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size); 1572 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu); 1573 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu); 1574 1575 bool kvm_intr_is_single_vcpu(struct kvm *kvm, struct kvm_lapic_irq *irq, 1576 struct kvm_vcpu **dest_vcpu); 1577 1578 void kvm_set_msi_irq(struct kvm *kvm, struct kvm_kernel_irq_routing_entry *e, 1579 struct kvm_lapic_irq *irq); 1580 1581 static inline void kvm_arch_vcpu_blocking(struct kvm_vcpu *vcpu) 1582 { 1583 if (kvm_x86_ops->vcpu_blocking) 1584 kvm_x86_ops->vcpu_blocking(vcpu); 1585 } 1586 1587 static inline void kvm_arch_vcpu_unblocking(struct kvm_vcpu *vcpu) 1588 { 1589 if (kvm_x86_ops->vcpu_unblocking) 1590 kvm_x86_ops->vcpu_unblocking(vcpu); 1591 } 1592 1593 static inline void kvm_arch_vcpu_block_finish(struct kvm_vcpu *vcpu) {} 1594 1595 static inline int kvm_cpu_get_apicid(int mps_cpu) 1596 { 1597 #ifdef CONFIG_X86_LOCAL_APIC 1598 return default_cpu_present_to_apicid(mps_cpu); 1599 #else 1600 WARN_ON_ONCE(1); 1601 return BAD_APICID; 1602 #endif 1603 } 1604 1605 #define put_smstate(type, buf, offset, val) \ 1606 *(type *)((buf) + (offset) - 0x7e00) = val 1607 1608 #define GET_SMSTATE(type, buf, offset) \ 1609 (*(type *)((buf) + (offset) - 0x7e00)) 1610 1611 #endif /* _ASM_X86_KVM_HOST_H */ 1612