1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Kernel-based Virtual Machine driver for Linux 4 * 5 * This header defines architecture specific interfaces, x86 version 6 */ 7 8 #ifndef _ASM_X86_KVM_HOST_H 9 #define _ASM_X86_KVM_HOST_H 10 11 #include <linux/types.h> 12 #include <linux/mm.h> 13 #include <linux/mmu_notifier.h> 14 #include <linux/tracepoint.h> 15 #include <linux/cpumask.h> 16 #include <linux/irq_work.h> 17 #include <linux/irq.h> 18 #include <linux/workqueue.h> 19 20 #include <linux/kvm.h> 21 #include <linux/kvm_para.h> 22 #include <linux/kvm_types.h> 23 #include <linux/perf_event.h> 24 #include <linux/pvclock_gtod.h> 25 #include <linux/clocksource.h> 26 #include <linux/irqbypass.h> 27 #include <linux/hyperv.h> 28 29 #include <asm/apic.h> 30 #include <asm/pvclock-abi.h> 31 #include <asm/desc.h> 32 #include <asm/mtrr.h> 33 #include <asm/msr-index.h> 34 #include <asm/asm.h> 35 #include <asm/kvm_page_track.h> 36 #include <asm/kvm_vcpu_regs.h> 37 #include <asm/hyperv-tlfs.h> 38 39 #define __KVM_HAVE_ARCH_VCPU_DEBUGFS 40 41 #define KVM_MAX_VCPUS 1024 42 43 /* 44 * In x86, the VCPU ID corresponds to the APIC ID, and APIC IDs 45 * might be larger than the actual number of VCPUs because the 46 * APIC ID encodes CPU topology information. 47 * 48 * In the worst case, we'll need less than one extra bit for the 49 * Core ID, and less than one extra bit for the Package (Die) ID, 50 * so ratio of 4 should be enough. 51 */ 52 #define KVM_VCPU_ID_RATIO 4 53 #define KVM_MAX_VCPU_IDS (KVM_MAX_VCPUS * KVM_VCPU_ID_RATIO) 54 55 /* memory slots that are not exposed to userspace */ 56 #define KVM_PRIVATE_MEM_SLOTS 3 57 58 #define KVM_HALT_POLL_NS_DEFAULT 200000 59 60 #define KVM_IRQCHIP_NUM_PINS KVM_IOAPIC_NUM_PINS 61 62 #define KVM_DIRTY_LOG_MANUAL_CAPS (KVM_DIRTY_LOG_MANUAL_PROTECT_ENABLE | \ 63 KVM_DIRTY_LOG_INITIALLY_SET) 64 65 #define KVM_BUS_LOCK_DETECTION_VALID_MODE (KVM_BUS_LOCK_DETECTION_OFF | \ 66 KVM_BUS_LOCK_DETECTION_EXIT) 67 68 /* x86-specific vcpu->requests bit members */ 69 #define KVM_REQ_MIGRATE_TIMER KVM_ARCH_REQ(0) 70 #define KVM_REQ_REPORT_TPR_ACCESS KVM_ARCH_REQ(1) 71 #define KVM_REQ_TRIPLE_FAULT KVM_ARCH_REQ(2) 72 #define KVM_REQ_MMU_SYNC KVM_ARCH_REQ(3) 73 #define KVM_REQ_CLOCK_UPDATE KVM_ARCH_REQ(4) 74 #define KVM_REQ_LOAD_MMU_PGD KVM_ARCH_REQ(5) 75 #define KVM_REQ_EVENT KVM_ARCH_REQ(6) 76 #define KVM_REQ_APF_HALT KVM_ARCH_REQ(7) 77 #define KVM_REQ_STEAL_UPDATE KVM_ARCH_REQ(8) 78 #define KVM_REQ_NMI KVM_ARCH_REQ(9) 79 #define KVM_REQ_PMU KVM_ARCH_REQ(10) 80 #define KVM_REQ_PMI KVM_ARCH_REQ(11) 81 #define KVM_REQ_SMI KVM_ARCH_REQ(12) 82 #define KVM_REQ_MASTERCLOCK_UPDATE KVM_ARCH_REQ(13) 83 #define KVM_REQ_MCLOCK_INPROGRESS \ 84 KVM_ARCH_REQ_FLAGS(14, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP) 85 #define KVM_REQ_SCAN_IOAPIC \ 86 KVM_ARCH_REQ_FLAGS(15, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP) 87 #define KVM_REQ_GLOBAL_CLOCK_UPDATE KVM_ARCH_REQ(16) 88 #define KVM_REQ_APIC_PAGE_RELOAD \ 89 KVM_ARCH_REQ_FLAGS(17, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP) 90 #define KVM_REQ_HV_CRASH KVM_ARCH_REQ(18) 91 #define KVM_REQ_IOAPIC_EOI_EXIT KVM_ARCH_REQ(19) 92 #define KVM_REQ_HV_RESET KVM_ARCH_REQ(20) 93 #define KVM_REQ_HV_EXIT KVM_ARCH_REQ(21) 94 #define KVM_REQ_HV_STIMER KVM_ARCH_REQ(22) 95 #define KVM_REQ_LOAD_EOI_EXITMAP KVM_ARCH_REQ(23) 96 #define KVM_REQ_GET_NESTED_STATE_PAGES KVM_ARCH_REQ(24) 97 #define KVM_REQ_APICV_UPDATE \ 98 KVM_ARCH_REQ_FLAGS(25, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP) 99 #define KVM_REQ_TLB_FLUSH_CURRENT KVM_ARCH_REQ(26) 100 #define KVM_REQ_TLB_FLUSH_GUEST \ 101 KVM_ARCH_REQ_FLAGS(27, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP) 102 #define KVM_REQ_APF_READY KVM_ARCH_REQ(28) 103 #define KVM_REQ_MSR_FILTER_CHANGED KVM_ARCH_REQ(29) 104 #define KVM_REQ_UPDATE_CPU_DIRTY_LOGGING \ 105 KVM_ARCH_REQ_FLAGS(30, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP) 106 #define KVM_REQ_MMU_FREE_OBSOLETE_ROOTS \ 107 KVM_ARCH_REQ_FLAGS(31, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP) 108 109 #define CR0_RESERVED_BITS \ 110 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \ 111 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \ 112 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG)) 113 114 #define CR4_RESERVED_BITS \ 115 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\ 116 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \ 117 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR | X86_CR4_PCIDE \ 118 | X86_CR4_OSXSAVE | X86_CR4_SMEP | X86_CR4_FSGSBASE \ 119 | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_VMXE \ 120 | X86_CR4_SMAP | X86_CR4_PKE | X86_CR4_UMIP)) 121 122 #define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR) 123 124 125 126 #define INVALID_PAGE (~(hpa_t)0) 127 #define VALID_PAGE(x) ((x) != INVALID_PAGE) 128 129 #define UNMAPPED_GVA (~(gpa_t)0) 130 #define INVALID_GPA (~(gpa_t)0) 131 132 /* KVM Hugepage definitions for x86 */ 133 #define KVM_MAX_HUGEPAGE_LEVEL PG_LEVEL_1G 134 #define KVM_NR_PAGE_SIZES (KVM_MAX_HUGEPAGE_LEVEL - PG_LEVEL_4K + 1) 135 #define KVM_HPAGE_GFN_SHIFT(x) (((x) - 1) * 9) 136 #define KVM_HPAGE_SHIFT(x) (PAGE_SHIFT + KVM_HPAGE_GFN_SHIFT(x)) 137 #define KVM_HPAGE_SIZE(x) (1UL << KVM_HPAGE_SHIFT(x)) 138 #define KVM_HPAGE_MASK(x) (~(KVM_HPAGE_SIZE(x) - 1)) 139 #define KVM_PAGES_PER_HPAGE(x) (KVM_HPAGE_SIZE(x) / PAGE_SIZE) 140 141 #define KVM_MEMSLOT_PAGES_TO_MMU_PAGES_RATIO 50 142 #define KVM_MIN_ALLOC_MMU_PAGES 64UL 143 #define KVM_MMU_HASH_SHIFT 12 144 #define KVM_NUM_MMU_PAGES (1 << KVM_MMU_HASH_SHIFT) 145 #define KVM_MIN_FREE_MMU_PAGES 5 146 #define KVM_REFILL_PAGES 25 147 #define KVM_MAX_CPUID_ENTRIES 256 148 #define KVM_NR_FIXED_MTRR_REGION 88 149 #define KVM_NR_VAR_MTRR 8 150 151 #define ASYNC_PF_PER_VCPU 64 152 153 enum kvm_reg { 154 VCPU_REGS_RAX = __VCPU_REGS_RAX, 155 VCPU_REGS_RCX = __VCPU_REGS_RCX, 156 VCPU_REGS_RDX = __VCPU_REGS_RDX, 157 VCPU_REGS_RBX = __VCPU_REGS_RBX, 158 VCPU_REGS_RSP = __VCPU_REGS_RSP, 159 VCPU_REGS_RBP = __VCPU_REGS_RBP, 160 VCPU_REGS_RSI = __VCPU_REGS_RSI, 161 VCPU_REGS_RDI = __VCPU_REGS_RDI, 162 #ifdef CONFIG_X86_64 163 VCPU_REGS_R8 = __VCPU_REGS_R8, 164 VCPU_REGS_R9 = __VCPU_REGS_R9, 165 VCPU_REGS_R10 = __VCPU_REGS_R10, 166 VCPU_REGS_R11 = __VCPU_REGS_R11, 167 VCPU_REGS_R12 = __VCPU_REGS_R12, 168 VCPU_REGS_R13 = __VCPU_REGS_R13, 169 VCPU_REGS_R14 = __VCPU_REGS_R14, 170 VCPU_REGS_R15 = __VCPU_REGS_R15, 171 #endif 172 VCPU_REGS_RIP, 173 NR_VCPU_REGS, 174 175 VCPU_EXREG_PDPTR = NR_VCPU_REGS, 176 VCPU_EXREG_CR0, 177 VCPU_EXREG_CR3, 178 VCPU_EXREG_CR4, 179 VCPU_EXREG_RFLAGS, 180 VCPU_EXREG_SEGMENTS, 181 VCPU_EXREG_EXIT_INFO_1, 182 VCPU_EXREG_EXIT_INFO_2, 183 }; 184 185 enum { 186 VCPU_SREG_ES, 187 VCPU_SREG_CS, 188 VCPU_SREG_SS, 189 VCPU_SREG_DS, 190 VCPU_SREG_FS, 191 VCPU_SREG_GS, 192 VCPU_SREG_TR, 193 VCPU_SREG_LDTR, 194 }; 195 196 enum exit_fastpath_completion { 197 EXIT_FASTPATH_NONE, 198 EXIT_FASTPATH_REENTER_GUEST, 199 EXIT_FASTPATH_EXIT_HANDLED, 200 }; 201 typedef enum exit_fastpath_completion fastpath_t; 202 203 struct x86_emulate_ctxt; 204 struct x86_exception; 205 enum x86_intercept; 206 enum x86_intercept_stage; 207 208 #define KVM_NR_DB_REGS 4 209 210 #define DR6_BUS_LOCK (1 << 11) 211 #define DR6_BD (1 << 13) 212 #define DR6_BS (1 << 14) 213 #define DR6_BT (1 << 15) 214 #define DR6_RTM (1 << 16) 215 /* 216 * DR6_ACTIVE_LOW combines fixed-1 and active-low bits. 217 * We can regard all the bits in DR6_FIXED_1 as active_low bits; 218 * they will never be 0 for now, but when they are defined 219 * in the future it will require no code change. 220 * 221 * DR6_ACTIVE_LOW is also used as the init/reset value for DR6. 222 */ 223 #define DR6_ACTIVE_LOW 0xffff0ff0 224 #define DR6_VOLATILE 0x0001e80f 225 #define DR6_FIXED_1 (DR6_ACTIVE_LOW & ~DR6_VOLATILE) 226 227 #define DR7_BP_EN_MASK 0x000000ff 228 #define DR7_GE (1 << 9) 229 #define DR7_GD (1 << 13) 230 #define DR7_FIXED_1 0x00000400 231 #define DR7_VOLATILE 0xffff2bff 232 233 #define KVM_GUESTDBG_VALID_MASK \ 234 (KVM_GUESTDBG_ENABLE | \ 235 KVM_GUESTDBG_SINGLESTEP | \ 236 KVM_GUESTDBG_USE_HW_BP | \ 237 KVM_GUESTDBG_USE_SW_BP | \ 238 KVM_GUESTDBG_INJECT_BP | \ 239 KVM_GUESTDBG_INJECT_DB | \ 240 KVM_GUESTDBG_BLOCKIRQ) 241 242 243 #define PFERR_PRESENT_BIT 0 244 #define PFERR_WRITE_BIT 1 245 #define PFERR_USER_BIT 2 246 #define PFERR_RSVD_BIT 3 247 #define PFERR_FETCH_BIT 4 248 #define PFERR_PK_BIT 5 249 #define PFERR_SGX_BIT 15 250 #define PFERR_GUEST_FINAL_BIT 32 251 #define PFERR_GUEST_PAGE_BIT 33 252 #define PFERR_IMPLICIT_ACCESS_BIT 48 253 254 #define PFERR_PRESENT_MASK (1U << PFERR_PRESENT_BIT) 255 #define PFERR_WRITE_MASK (1U << PFERR_WRITE_BIT) 256 #define PFERR_USER_MASK (1U << PFERR_USER_BIT) 257 #define PFERR_RSVD_MASK (1U << PFERR_RSVD_BIT) 258 #define PFERR_FETCH_MASK (1U << PFERR_FETCH_BIT) 259 #define PFERR_PK_MASK (1U << PFERR_PK_BIT) 260 #define PFERR_SGX_MASK (1U << PFERR_SGX_BIT) 261 #define PFERR_GUEST_FINAL_MASK (1ULL << PFERR_GUEST_FINAL_BIT) 262 #define PFERR_GUEST_PAGE_MASK (1ULL << PFERR_GUEST_PAGE_BIT) 263 #define PFERR_IMPLICIT_ACCESS (1ULL << PFERR_IMPLICIT_ACCESS_BIT) 264 265 #define PFERR_NESTED_GUEST_PAGE (PFERR_GUEST_PAGE_MASK | \ 266 PFERR_WRITE_MASK | \ 267 PFERR_PRESENT_MASK) 268 269 /* apic attention bits */ 270 #define KVM_APIC_CHECK_VAPIC 0 271 /* 272 * The following bit is set with PV-EOI, unset on EOI. 273 * We detect PV-EOI changes by guest by comparing 274 * this bit with PV-EOI in guest memory. 275 * See the implementation in apic_update_pv_eoi. 276 */ 277 #define KVM_APIC_PV_EOI_PENDING 1 278 279 struct kvm_kernel_irq_routing_entry; 280 281 /* 282 * kvm_mmu_page_role tracks the properties of a shadow page (where shadow page 283 * also includes TDP pages) to determine whether or not a page can be used in 284 * the given MMU context. This is a subset of the overall kvm_cpu_role to 285 * minimize the size of kvm_memory_slot.arch.gfn_track, i.e. allows allocating 286 * 2 bytes per gfn instead of 4 bytes per gfn. 287 * 288 * Upper-level shadow pages having gptes are tracked for write-protection via 289 * gfn_track. As above, gfn_track is a 16 bit counter, so KVM must not create 290 * more than 2^16-1 upper-level shadow pages at a single gfn, otherwise 291 * gfn_track will overflow and explosions will ensure. 292 * 293 * A unique shadow page (SP) for a gfn is created if and only if an existing SP 294 * cannot be reused. The ability to reuse a SP is tracked by its role, which 295 * incorporates various mode bits and properties of the SP. Roughly speaking, 296 * the number of unique SPs that can theoretically be created is 2^n, where n 297 * is the number of bits that are used to compute the role. 298 * 299 * But, even though there are 19 bits in the mask below, not all combinations 300 * of modes and flags are possible: 301 * 302 * - invalid shadow pages are not accounted, so the bits are effectively 18 303 * 304 * - quadrant will only be used if has_4_byte_gpte=1 (non-PAE paging); 305 * execonly and ad_disabled are only used for nested EPT which has 306 * has_4_byte_gpte=0. Therefore, 2 bits are always unused. 307 * 308 * - the 4 bits of level are effectively limited to the values 2/3/4/5, 309 * as 4k SPs are not tracked (allowed to go unsync). In addition non-PAE 310 * paging has exactly one upper level, making level completely redundant 311 * when has_4_byte_gpte=1. 312 * 313 * - on top of this, smep_andnot_wp and smap_andnot_wp are only set if 314 * cr0_wp=0, therefore these three bits only give rise to 5 possibilities. 315 * 316 * Therefore, the maximum number of possible upper-level shadow pages for a 317 * single gfn is a bit less than 2^13. 318 */ 319 union kvm_mmu_page_role { 320 u32 word; 321 struct { 322 unsigned level:4; 323 unsigned has_4_byte_gpte:1; 324 unsigned quadrant:2; 325 unsigned direct:1; 326 unsigned access:3; 327 unsigned invalid:1; 328 unsigned efer_nx:1; 329 unsigned cr0_wp:1; 330 unsigned smep_andnot_wp:1; 331 unsigned smap_andnot_wp:1; 332 unsigned ad_disabled:1; 333 unsigned guest_mode:1; 334 unsigned passthrough:1; 335 unsigned :5; 336 337 /* 338 * This is left at the top of the word so that 339 * kvm_memslots_for_spte_role can extract it with a 340 * simple shift. While there is room, give it a whole 341 * byte so it is also faster to load it from memory. 342 */ 343 unsigned smm:8; 344 }; 345 }; 346 347 /* 348 * kvm_mmu_extended_role complements kvm_mmu_page_role, tracking properties 349 * relevant to the current MMU configuration. When loading CR0, CR4, or EFER, 350 * including on nested transitions, if nothing in the full role changes then 351 * MMU re-configuration can be skipped. @valid bit is set on first usage so we 352 * don't treat all-zero structure as valid data. 353 * 354 * The properties that are tracked in the extended role but not the page role 355 * are for things that either (a) do not affect the validity of the shadow page 356 * or (b) are indirectly reflected in the shadow page's role. For example, 357 * CR4.PKE only affects permission checks for software walks of the guest page 358 * tables (because KVM doesn't support Protection Keys with shadow paging), and 359 * CR0.PG, CR4.PAE, and CR4.PSE are indirectly reflected in role.level. 360 * 361 * Note, SMEP and SMAP are not redundant with sm*p_andnot_wp in the page role. 362 * If CR0.WP=1, KVM can reuse shadow pages for the guest regardless of SMEP and 363 * SMAP, but the MMU's permission checks for software walks need to be SMEP and 364 * SMAP aware regardless of CR0.WP. 365 */ 366 union kvm_mmu_extended_role { 367 u32 word; 368 struct { 369 unsigned int valid:1; 370 unsigned int execonly:1; 371 unsigned int cr4_pse:1; 372 unsigned int cr4_pke:1; 373 unsigned int cr4_smap:1; 374 unsigned int cr4_smep:1; 375 unsigned int cr4_la57:1; 376 unsigned int efer_lma:1; 377 }; 378 }; 379 380 union kvm_cpu_role { 381 u64 as_u64; 382 struct { 383 union kvm_mmu_page_role base; 384 union kvm_mmu_extended_role ext; 385 }; 386 }; 387 388 struct kvm_rmap_head { 389 unsigned long val; 390 }; 391 392 struct kvm_pio_request { 393 unsigned long linear_rip; 394 unsigned long count; 395 int in; 396 int port; 397 int size; 398 }; 399 400 #define PT64_ROOT_MAX_LEVEL 5 401 402 struct rsvd_bits_validate { 403 u64 rsvd_bits_mask[2][PT64_ROOT_MAX_LEVEL]; 404 u64 bad_mt_xwr; 405 }; 406 407 struct kvm_mmu_root_info { 408 gpa_t pgd; 409 hpa_t hpa; 410 }; 411 412 #define KVM_MMU_ROOT_INFO_INVALID \ 413 ((struct kvm_mmu_root_info) { .pgd = INVALID_PAGE, .hpa = INVALID_PAGE }) 414 415 #define KVM_MMU_NUM_PREV_ROOTS 3 416 417 #define KVM_HAVE_MMU_RWLOCK 418 419 struct kvm_mmu_page; 420 struct kvm_page_fault; 421 422 /* 423 * x86 supports 4 paging modes (5-level 64-bit, 4-level 64-bit, 3-level 32-bit, 424 * and 2-level 32-bit). The kvm_mmu structure abstracts the details of the 425 * current mmu mode. 426 */ 427 struct kvm_mmu { 428 unsigned long (*get_guest_pgd)(struct kvm_vcpu *vcpu); 429 u64 (*get_pdptr)(struct kvm_vcpu *vcpu, int index); 430 int (*page_fault)(struct kvm_vcpu *vcpu, struct kvm_page_fault *fault); 431 void (*inject_page_fault)(struct kvm_vcpu *vcpu, 432 struct x86_exception *fault); 433 gpa_t (*gva_to_gpa)(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, 434 gpa_t gva_or_gpa, u64 access, 435 struct x86_exception *exception); 436 int (*sync_page)(struct kvm_vcpu *vcpu, 437 struct kvm_mmu_page *sp); 438 void (*invlpg)(struct kvm_vcpu *vcpu, gva_t gva, hpa_t root_hpa); 439 struct kvm_mmu_root_info root; 440 union kvm_cpu_role cpu_role; 441 union kvm_mmu_page_role root_role; 442 443 /* 444 * The pkru_mask indicates if protection key checks are needed. It 445 * consists of 16 domains indexed by page fault error code bits [4:1], 446 * with PFEC.RSVD replaced by ACC_USER_MASK from the page tables. 447 * Each domain has 2 bits which are ANDed with AD and WD from PKRU. 448 */ 449 u32 pkru_mask; 450 451 struct kvm_mmu_root_info prev_roots[KVM_MMU_NUM_PREV_ROOTS]; 452 453 /* 454 * Bitmap; bit set = permission fault 455 * Byte index: page fault error code [4:1] 456 * Bit index: pte permissions in ACC_* format 457 */ 458 u8 permissions[16]; 459 460 u64 *pae_root; 461 u64 *pml4_root; 462 u64 *pml5_root; 463 464 /* 465 * check zero bits on shadow page table entries, these 466 * bits include not only hardware reserved bits but also 467 * the bits spte never used. 468 */ 469 struct rsvd_bits_validate shadow_zero_check; 470 471 struct rsvd_bits_validate guest_rsvd_check; 472 473 u64 pdptrs[4]; /* pae */ 474 }; 475 476 struct kvm_tlb_range { 477 u64 start_gfn; 478 u64 pages; 479 }; 480 481 enum pmc_type { 482 KVM_PMC_GP = 0, 483 KVM_PMC_FIXED, 484 }; 485 486 struct kvm_pmc { 487 enum pmc_type type; 488 u8 idx; 489 u64 counter; 490 u64 eventsel; 491 struct perf_event *perf_event; 492 struct kvm_vcpu *vcpu; 493 /* 494 * eventsel value for general purpose counters, 495 * ctrl value for fixed counters. 496 */ 497 u64 current_config; 498 bool is_paused; 499 bool intr; 500 }; 501 502 #define KVM_PMC_MAX_FIXED 3 503 struct kvm_pmu { 504 unsigned nr_arch_gp_counters; 505 unsigned nr_arch_fixed_counters; 506 unsigned available_event_types; 507 u64 fixed_ctr_ctrl; 508 u64 global_ctrl; 509 u64 global_status; 510 u64 counter_bitmask[2]; 511 u64 global_ctrl_mask; 512 u64 global_ovf_ctrl_mask; 513 u64 reserved_bits; 514 u64 raw_event_mask; 515 u8 version; 516 struct kvm_pmc gp_counters[INTEL_PMC_MAX_GENERIC]; 517 struct kvm_pmc fixed_counters[KVM_PMC_MAX_FIXED]; 518 struct irq_work irq_work; 519 DECLARE_BITMAP(reprogram_pmi, X86_PMC_IDX_MAX); 520 DECLARE_BITMAP(all_valid_pmc_idx, X86_PMC_IDX_MAX); 521 DECLARE_BITMAP(pmc_in_use, X86_PMC_IDX_MAX); 522 523 /* 524 * The gate to release perf_events not marked in 525 * pmc_in_use only once in a vcpu time slice. 526 */ 527 bool need_cleanup; 528 529 /* 530 * The total number of programmed perf_events and it helps to avoid 531 * redundant check before cleanup if guest don't use vPMU at all. 532 */ 533 u8 event_count; 534 }; 535 536 struct kvm_pmu_ops; 537 538 enum { 539 KVM_DEBUGREG_BP_ENABLED = 1, 540 KVM_DEBUGREG_WONT_EXIT = 2, 541 }; 542 543 struct kvm_mtrr_range { 544 u64 base; 545 u64 mask; 546 struct list_head node; 547 }; 548 549 struct kvm_mtrr { 550 struct kvm_mtrr_range var_ranges[KVM_NR_VAR_MTRR]; 551 mtrr_type fixed_ranges[KVM_NR_FIXED_MTRR_REGION]; 552 u64 deftype; 553 554 struct list_head head; 555 }; 556 557 /* Hyper-V SynIC timer */ 558 struct kvm_vcpu_hv_stimer { 559 struct hrtimer timer; 560 int index; 561 union hv_stimer_config config; 562 u64 count; 563 u64 exp_time; 564 struct hv_message msg; 565 bool msg_pending; 566 }; 567 568 /* Hyper-V synthetic interrupt controller (SynIC)*/ 569 struct kvm_vcpu_hv_synic { 570 u64 version; 571 u64 control; 572 u64 msg_page; 573 u64 evt_page; 574 atomic64_t sint[HV_SYNIC_SINT_COUNT]; 575 atomic_t sint_to_gsi[HV_SYNIC_SINT_COUNT]; 576 DECLARE_BITMAP(auto_eoi_bitmap, 256); 577 DECLARE_BITMAP(vec_bitmap, 256); 578 bool active; 579 bool dont_zero_synic_pages; 580 }; 581 582 /* Hyper-V per vcpu emulation context */ 583 struct kvm_vcpu_hv { 584 struct kvm_vcpu *vcpu; 585 u32 vp_index; 586 u64 hv_vapic; 587 s64 runtime_offset; 588 struct kvm_vcpu_hv_synic synic; 589 struct kvm_hyperv_exit exit; 590 struct kvm_vcpu_hv_stimer stimer[HV_SYNIC_STIMER_COUNT]; 591 DECLARE_BITMAP(stimer_pending_bitmap, HV_SYNIC_STIMER_COUNT); 592 bool enforce_cpuid; 593 struct { 594 u32 features_eax; /* HYPERV_CPUID_FEATURES.EAX */ 595 u32 features_ebx; /* HYPERV_CPUID_FEATURES.EBX */ 596 u32 features_edx; /* HYPERV_CPUID_FEATURES.EDX */ 597 u32 enlightenments_eax; /* HYPERV_CPUID_ENLIGHTMENT_INFO.EAX */ 598 u32 enlightenments_ebx; /* HYPERV_CPUID_ENLIGHTMENT_INFO.EBX */ 599 u32 syndbg_cap_eax; /* HYPERV_CPUID_SYNDBG_PLATFORM_CAPABILITIES.EAX */ 600 } cpuid_cache; 601 }; 602 603 /* Xen HVM per vcpu emulation context */ 604 struct kvm_vcpu_xen { 605 u64 hypercall_rip; 606 u32 current_runstate; 607 u8 upcall_vector; 608 struct gfn_to_pfn_cache vcpu_info_cache; 609 struct gfn_to_pfn_cache vcpu_time_info_cache; 610 struct gfn_to_pfn_cache runstate_cache; 611 u64 last_steal; 612 u64 runstate_entry_time; 613 u64 runstate_times[4]; 614 unsigned long evtchn_pending_sel; 615 u32 vcpu_id; /* The Xen / ACPI vCPU ID */ 616 u32 timer_virq; 617 u64 timer_expires; /* In guest epoch */ 618 atomic_t timer_pending; 619 struct hrtimer timer; 620 int poll_evtchn; 621 struct timer_list poll_timer; 622 }; 623 624 struct kvm_vcpu_arch { 625 /* 626 * rip and regs accesses must go through 627 * kvm_{register,rip}_{read,write} functions. 628 */ 629 unsigned long regs[NR_VCPU_REGS]; 630 u32 regs_avail; 631 u32 regs_dirty; 632 633 unsigned long cr0; 634 unsigned long cr0_guest_owned_bits; 635 unsigned long cr2; 636 unsigned long cr3; 637 unsigned long cr4; 638 unsigned long cr4_guest_owned_bits; 639 unsigned long cr4_guest_rsvd_bits; 640 unsigned long cr8; 641 u32 host_pkru; 642 u32 pkru; 643 u32 hflags; 644 u64 efer; 645 u64 apic_base; 646 struct kvm_lapic *apic; /* kernel irqchip context */ 647 bool apicv_active; 648 bool load_eoi_exitmap_pending; 649 DECLARE_BITMAP(ioapic_handled_vectors, 256); 650 unsigned long apic_attention; 651 int32_t apic_arb_prio; 652 int mp_state; 653 u64 ia32_misc_enable_msr; 654 u64 smbase; 655 u64 smi_count; 656 bool at_instruction_boundary; 657 bool tpr_access_reporting; 658 bool xsaves_enabled; 659 bool xfd_no_write_intercept; 660 u64 ia32_xss; 661 u64 microcode_version; 662 u64 arch_capabilities; 663 u64 perf_capabilities; 664 665 /* 666 * Paging state of the vcpu 667 * 668 * If the vcpu runs in guest mode with two level paging this still saves 669 * the paging mode of the l1 guest. This context is always used to 670 * handle faults. 671 */ 672 struct kvm_mmu *mmu; 673 674 /* Non-nested MMU for L1 */ 675 struct kvm_mmu root_mmu; 676 677 /* L1 MMU when running nested */ 678 struct kvm_mmu guest_mmu; 679 680 /* 681 * Paging state of an L2 guest (used for nested npt) 682 * 683 * This context will save all necessary information to walk page tables 684 * of an L2 guest. This context is only initialized for page table 685 * walking and not for faulting since we never handle l2 page faults on 686 * the host. 687 */ 688 struct kvm_mmu nested_mmu; 689 690 /* 691 * Pointer to the mmu context currently used for 692 * gva_to_gpa translations. 693 */ 694 struct kvm_mmu *walk_mmu; 695 696 struct kvm_mmu_memory_cache mmu_pte_list_desc_cache; 697 struct kvm_mmu_memory_cache mmu_shadow_page_cache; 698 struct kvm_mmu_memory_cache mmu_gfn_array_cache; 699 struct kvm_mmu_memory_cache mmu_page_header_cache; 700 701 /* 702 * QEMU userspace and the guest each have their own FPU state. 703 * In vcpu_run, we switch between the user and guest FPU contexts. 704 * While running a VCPU, the VCPU thread will have the guest FPU 705 * context. 706 * 707 * Note that while the PKRU state lives inside the fpu registers, 708 * it is switched out separately at VMENTER and VMEXIT time. The 709 * "guest_fpstate" state here contains the guest FPU context, with the 710 * host PRKU bits. 711 */ 712 struct fpu_guest guest_fpu; 713 714 u64 xcr0; 715 716 struct kvm_pio_request pio; 717 void *pio_data; 718 void *sev_pio_data; 719 unsigned sev_pio_count; 720 721 u8 event_exit_inst_len; 722 723 struct kvm_queued_exception { 724 bool pending; 725 bool injected; 726 bool has_error_code; 727 u8 nr; 728 u32 error_code; 729 unsigned long payload; 730 bool has_payload; 731 u8 nested_apf; 732 } exception; 733 734 struct kvm_queued_interrupt { 735 bool injected; 736 bool soft; 737 u8 nr; 738 } interrupt; 739 740 int halt_request; /* real mode on Intel only */ 741 742 int cpuid_nent; 743 struct kvm_cpuid_entry2 *cpuid_entries; 744 u32 kvm_cpuid_base; 745 746 u64 reserved_gpa_bits; 747 int maxphyaddr; 748 749 /* emulate context */ 750 751 struct x86_emulate_ctxt *emulate_ctxt; 752 bool emulate_regs_need_sync_to_vcpu; 753 bool emulate_regs_need_sync_from_vcpu; 754 int (*complete_userspace_io)(struct kvm_vcpu *vcpu); 755 756 gpa_t time; 757 struct pvclock_vcpu_time_info hv_clock; 758 unsigned int hw_tsc_khz; 759 struct gfn_to_pfn_cache pv_time; 760 /* set guest stopped flag in pvclock flags field */ 761 bool pvclock_set_guest_stopped_request; 762 763 struct { 764 u8 preempted; 765 u64 msr_val; 766 u64 last_steal; 767 struct gfn_to_hva_cache cache; 768 } st; 769 770 u64 l1_tsc_offset; 771 u64 tsc_offset; /* current tsc offset */ 772 u64 last_guest_tsc; 773 u64 last_host_tsc; 774 u64 tsc_offset_adjustment; 775 u64 this_tsc_nsec; 776 u64 this_tsc_write; 777 u64 this_tsc_generation; 778 bool tsc_catchup; 779 bool tsc_always_catchup; 780 s8 virtual_tsc_shift; 781 u32 virtual_tsc_mult; 782 u32 virtual_tsc_khz; 783 s64 ia32_tsc_adjust_msr; 784 u64 msr_ia32_power_ctl; 785 u64 l1_tsc_scaling_ratio; 786 u64 tsc_scaling_ratio; /* current scaling ratio */ 787 788 atomic_t nmi_queued; /* unprocessed asynchronous NMIs */ 789 unsigned nmi_pending; /* NMI queued after currently running handler */ 790 bool nmi_injected; /* Trying to inject an NMI this entry */ 791 bool smi_pending; /* SMI queued after currently running handler */ 792 u8 handling_intr_from_guest; 793 794 struct kvm_mtrr mtrr_state; 795 u64 pat; 796 797 unsigned switch_db_regs; 798 unsigned long db[KVM_NR_DB_REGS]; 799 unsigned long dr6; 800 unsigned long dr7; 801 unsigned long eff_db[KVM_NR_DB_REGS]; 802 unsigned long guest_debug_dr7; 803 u64 msr_platform_info; 804 u64 msr_misc_features_enables; 805 806 u64 mcg_cap; 807 u64 mcg_status; 808 u64 mcg_ctl; 809 u64 mcg_ext_ctl; 810 u64 *mce_banks; 811 812 /* Cache MMIO info */ 813 u64 mmio_gva; 814 unsigned mmio_access; 815 gfn_t mmio_gfn; 816 u64 mmio_gen; 817 818 struct kvm_pmu pmu; 819 820 /* used for guest single stepping over the given code position */ 821 unsigned long singlestep_rip; 822 823 bool hyperv_enabled; 824 struct kvm_vcpu_hv *hyperv; 825 struct kvm_vcpu_xen xen; 826 827 cpumask_var_t wbinvd_dirty_mask; 828 829 unsigned long last_retry_eip; 830 unsigned long last_retry_addr; 831 832 struct { 833 bool halted; 834 gfn_t gfns[ASYNC_PF_PER_VCPU]; 835 struct gfn_to_hva_cache data; 836 u64 msr_en_val; /* MSR_KVM_ASYNC_PF_EN */ 837 u64 msr_int_val; /* MSR_KVM_ASYNC_PF_INT */ 838 u16 vec; 839 u32 id; 840 bool send_user_only; 841 u32 host_apf_flags; 842 unsigned long nested_apf_token; 843 bool delivery_as_pf_vmexit; 844 bool pageready_pending; 845 } apf; 846 847 /* OSVW MSRs (AMD only) */ 848 struct { 849 u64 length; 850 u64 status; 851 } osvw; 852 853 struct { 854 u64 msr_val; 855 struct gfn_to_hva_cache data; 856 } pv_eoi; 857 858 u64 msr_kvm_poll_control; 859 860 /* 861 * Indicates the guest is trying to write a gfn that contains one or 862 * more of the PTEs used to translate the write itself, i.e. the access 863 * is changing its own translation in the guest page tables. KVM exits 864 * to userspace if emulation of the faulting instruction fails and this 865 * flag is set, as KVM cannot make forward progress. 866 * 867 * If emulation fails for a write to guest page tables, KVM unprotects 868 * (zaps) the shadow page for the target gfn and resumes the guest to 869 * retry the non-emulatable instruction (on hardware). Unprotecting the 870 * gfn doesn't allow forward progress for a self-changing access because 871 * doing so also zaps the translation for the gfn, i.e. retrying the 872 * instruction will hit a !PRESENT fault, which results in a new shadow 873 * page and sends KVM back to square one. 874 */ 875 bool write_fault_to_shadow_pgtable; 876 877 /* set at EPT violation at this point */ 878 unsigned long exit_qualification; 879 880 /* pv related host specific info */ 881 struct { 882 bool pv_unhalted; 883 } pv; 884 885 int pending_ioapic_eoi; 886 int pending_external_vector; 887 888 /* be preempted when it's in kernel-mode(cpl=0) */ 889 bool preempted_in_kernel; 890 891 /* Flush the L1 Data cache for L1TF mitigation on VMENTER */ 892 bool l1tf_flush_l1d; 893 894 /* Host CPU on which VM-entry was most recently attempted */ 895 int last_vmentry_cpu; 896 897 /* AMD MSRC001_0015 Hardware Configuration */ 898 u64 msr_hwcr; 899 900 /* pv related cpuid info */ 901 struct { 902 /* 903 * value of the eax register in the KVM_CPUID_FEATURES CPUID 904 * leaf. 905 */ 906 u32 features; 907 908 /* 909 * indicates whether pv emulation should be disabled if features 910 * are not present in the guest's cpuid 911 */ 912 bool enforce; 913 } pv_cpuid; 914 915 /* Protected Guests */ 916 bool guest_state_protected; 917 918 /* 919 * Set when PDPTS were loaded directly by the userspace without 920 * reading the guest memory 921 */ 922 bool pdptrs_from_userspace; 923 924 #if IS_ENABLED(CONFIG_HYPERV) 925 hpa_t hv_root_tdp; 926 #endif 927 }; 928 929 struct kvm_lpage_info { 930 int disallow_lpage; 931 }; 932 933 struct kvm_arch_memory_slot { 934 struct kvm_rmap_head *rmap[KVM_NR_PAGE_SIZES]; 935 struct kvm_lpage_info *lpage_info[KVM_NR_PAGE_SIZES - 1]; 936 unsigned short *gfn_track[KVM_PAGE_TRACK_MAX]; 937 }; 938 939 /* 940 * We use as the mode the number of bits allocated in the LDR for the 941 * logical processor ID. It happens that these are all powers of two. 942 * This makes it is very easy to detect cases where the APICs are 943 * configured for multiple modes; in that case, we cannot use the map and 944 * hence cannot use kvm_irq_delivery_to_apic_fast either. 945 */ 946 #define KVM_APIC_MODE_XAPIC_CLUSTER 4 947 #define KVM_APIC_MODE_XAPIC_FLAT 8 948 #define KVM_APIC_MODE_X2APIC 16 949 950 struct kvm_apic_map { 951 struct rcu_head rcu; 952 u8 mode; 953 u32 max_apic_id; 954 union { 955 struct kvm_lapic *xapic_flat_map[8]; 956 struct kvm_lapic *xapic_cluster_map[16][4]; 957 }; 958 struct kvm_lapic *phys_map[]; 959 }; 960 961 /* Hyper-V synthetic debugger (SynDbg)*/ 962 struct kvm_hv_syndbg { 963 struct { 964 u64 control; 965 u64 status; 966 u64 send_page; 967 u64 recv_page; 968 u64 pending_page; 969 } control; 970 u64 options; 971 }; 972 973 /* Current state of Hyper-V TSC page clocksource */ 974 enum hv_tsc_page_status { 975 /* TSC page was not set up or disabled */ 976 HV_TSC_PAGE_UNSET = 0, 977 /* TSC page MSR was written by the guest, update pending */ 978 HV_TSC_PAGE_GUEST_CHANGED, 979 /* TSC page update was triggered from the host side */ 980 HV_TSC_PAGE_HOST_CHANGED, 981 /* TSC page was properly set up and is currently active */ 982 HV_TSC_PAGE_SET, 983 /* TSC page was set up with an inaccessible GPA */ 984 HV_TSC_PAGE_BROKEN, 985 }; 986 987 /* Hyper-V emulation context */ 988 struct kvm_hv { 989 struct mutex hv_lock; 990 u64 hv_guest_os_id; 991 u64 hv_hypercall; 992 u64 hv_tsc_page; 993 enum hv_tsc_page_status hv_tsc_page_status; 994 995 /* Hyper-v based guest crash (NT kernel bugcheck) parameters */ 996 u64 hv_crash_param[HV_X64_MSR_CRASH_PARAMS]; 997 u64 hv_crash_ctl; 998 999 struct ms_hyperv_tsc_page tsc_ref; 1000 1001 struct idr conn_to_evt; 1002 1003 u64 hv_reenlightenment_control; 1004 u64 hv_tsc_emulation_control; 1005 u64 hv_tsc_emulation_status; 1006 1007 /* How many vCPUs have VP index != vCPU index */ 1008 atomic_t num_mismatched_vp_indexes; 1009 1010 /* 1011 * How many SynICs use 'AutoEOI' feature 1012 * (protected by arch.apicv_update_lock) 1013 */ 1014 unsigned int synic_auto_eoi_used; 1015 1016 struct hv_partition_assist_pg *hv_pa_pg; 1017 struct kvm_hv_syndbg hv_syndbg; 1018 }; 1019 1020 struct msr_bitmap_range { 1021 u32 flags; 1022 u32 nmsrs; 1023 u32 base; 1024 unsigned long *bitmap; 1025 }; 1026 1027 /* Xen emulation context */ 1028 struct kvm_xen { 1029 u32 xen_version; 1030 bool long_mode; 1031 u8 upcall_vector; 1032 struct gfn_to_pfn_cache shinfo_cache; 1033 struct idr evtchn_ports; 1034 unsigned long poll_mask[BITS_TO_LONGS(KVM_MAX_VCPUS)]; 1035 }; 1036 1037 enum kvm_irqchip_mode { 1038 KVM_IRQCHIP_NONE, 1039 KVM_IRQCHIP_KERNEL, /* created with KVM_CREATE_IRQCHIP */ 1040 KVM_IRQCHIP_SPLIT, /* created with KVM_CAP_SPLIT_IRQCHIP */ 1041 }; 1042 1043 struct kvm_x86_msr_filter { 1044 u8 count; 1045 bool default_allow:1; 1046 struct msr_bitmap_range ranges[16]; 1047 }; 1048 1049 enum kvm_apicv_inhibit { 1050 1051 /********************************************************************/ 1052 /* INHIBITs that are relevant to both Intel's APICv and AMD's AVIC. */ 1053 /********************************************************************/ 1054 1055 /* 1056 * APIC acceleration is disabled by a module parameter 1057 * and/or not supported in hardware. 1058 */ 1059 APICV_INHIBIT_REASON_DISABLE, 1060 1061 /* 1062 * APIC acceleration is inhibited because AutoEOI feature is 1063 * being used by a HyperV guest. 1064 */ 1065 APICV_INHIBIT_REASON_HYPERV, 1066 1067 /* 1068 * APIC acceleration is inhibited because the userspace didn't yet 1069 * enable the kernel/split irqchip. 1070 */ 1071 APICV_INHIBIT_REASON_ABSENT, 1072 1073 /* APIC acceleration is inhibited because KVM_GUESTDBG_BLOCKIRQ 1074 * (out of band, debug measure of blocking all interrupts on this vCPU) 1075 * was enabled, to avoid AVIC/APICv bypassing it. 1076 */ 1077 APICV_INHIBIT_REASON_BLOCKIRQ, 1078 1079 /* 1080 * For simplicity, the APIC acceleration is inhibited 1081 * first time either APIC ID or APIC base are changed by the guest 1082 * from their reset values. 1083 */ 1084 APICV_INHIBIT_REASON_APIC_ID_MODIFIED, 1085 APICV_INHIBIT_REASON_APIC_BASE_MODIFIED, 1086 1087 /******************************************************/ 1088 /* INHIBITs that are relevant only to the AMD's AVIC. */ 1089 /******************************************************/ 1090 1091 /* 1092 * AVIC is inhibited on a vCPU because it runs a nested guest. 1093 * 1094 * This is needed because unlike APICv, the peers of this vCPU 1095 * cannot use the doorbell mechanism to signal interrupts via AVIC when 1096 * a vCPU runs nested. 1097 */ 1098 APICV_INHIBIT_REASON_NESTED, 1099 1100 /* 1101 * On SVM, the wait for the IRQ window is implemented with pending vIRQ, 1102 * which cannot be injected when the AVIC is enabled, thus AVIC 1103 * is inhibited while KVM waits for IRQ window. 1104 */ 1105 APICV_INHIBIT_REASON_IRQWIN, 1106 1107 /* 1108 * PIT (i8254) 're-inject' mode, relies on EOI intercept, 1109 * which AVIC doesn't support for edge triggered interrupts. 1110 */ 1111 APICV_INHIBIT_REASON_PIT_REINJ, 1112 1113 /* 1114 * AVIC is inhibited because the guest has x2apic in its CPUID. 1115 */ 1116 APICV_INHIBIT_REASON_X2APIC, 1117 1118 /* 1119 * AVIC is disabled because SEV doesn't support it. 1120 */ 1121 APICV_INHIBIT_REASON_SEV, 1122 }; 1123 1124 struct kvm_arch { 1125 unsigned long n_used_mmu_pages; 1126 unsigned long n_requested_mmu_pages; 1127 unsigned long n_max_mmu_pages; 1128 unsigned int indirect_shadow_pages; 1129 u8 mmu_valid_gen; 1130 struct hlist_head mmu_page_hash[KVM_NUM_MMU_PAGES]; 1131 struct list_head active_mmu_pages; 1132 struct list_head zapped_obsolete_pages; 1133 struct list_head lpage_disallowed_mmu_pages; 1134 struct kvm_page_track_notifier_node mmu_sp_tracker; 1135 struct kvm_page_track_notifier_head track_notifier_head; 1136 /* 1137 * Protects marking pages unsync during page faults, as TDP MMU page 1138 * faults only take mmu_lock for read. For simplicity, the unsync 1139 * pages lock is always taken when marking pages unsync regardless of 1140 * whether mmu_lock is held for read or write. 1141 */ 1142 spinlock_t mmu_unsync_pages_lock; 1143 1144 struct list_head assigned_dev_head; 1145 struct iommu_domain *iommu_domain; 1146 bool iommu_noncoherent; 1147 #define __KVM_HAVE_ARCH_NONCOHERENT_DMA 1148 atomic_t noncoherent_dma_count; 1149 #define __KVM_HAVE_ARCH_ASSIGNED_DEVICE 1150 atomic_t assigned_device_count; 1151 struct kvm_pic *vpic; 1152 struct kvm_ioapic *vioapic; 1153 struct kvm_pit *vpit; 1154 atomic_t vapics_in_nmi_mode; 1155 struct mutex apic_map_lock; 1156 struct kvm_apic_map __rcu *apic_map; 1157 atomic_t apic_map_dirty; 1158 1159 /* Protects apic_access_memslot_enabled and apicv_inhibit_reasons */ 1160 struct rw_semaphore apicv_update_lock; 1161 1162 bool apic_access_memslot_enabled; 1163 unsigned long apicv_inhibit_reasons; 1164 1165 gpa_t wall_clock; 1166 1167 bool mwait_in_guest; 1168 bool hlt_in_guest; 1169 bool pause_in_guest; 1170 bool cstate_in_guest; 1171 1172 unsigned long irq_sources_bitmap; 1173 s64 kvmclock_offset; 1174 1175 /* 1176 * This also protects nr_vcpus_matched_tsc which is read from a 1177 * preemption-disabled region, so it must be a raw spinlock. 1178 */ 1179 raw_spinlock_t tsc_write_lock; 1180 u64 last_tsc_nsec; 1181 u64 last_tsc_write; 1182 u32 last_tsc_khz; 1183 u64 last_tsc_offset; 1184 u64 cur_tsc_nsec; 1185 u64 cur_tsc_write; 1186 u64 cur_tsc_offset; 1187 u64 cur_tsc_generation; 1188 int nr_vcpus_matched_tsc; 1189 1190 u32 default_tsc_khz; 1191 1192 seqcount_raw_spinlock_t pvclock_sc; 1193 bool use_master_clock; 1194 u64 master_kernel_ns; 1195 u64 master_cycle_now; 1196 struct delayed_work kvmclock_update_work; 1197 struct delayed_work kvmclock_sync_work; 1198 1199 struct kvm_xen_hvm_config xen_hvm_config; 1200 1201 /* reads protected by irq_srcu, writes by irq_lock */ 1202 struct hlist_head mask_notifier_list; 1203 1204 struct kvm_hv hyperv; 1205 struct kvm_xen xen; 1206 1207 bool backwards_tsc_observed; 1208 bool boot_vcpu_runs_old_kvmclock; 1209 u32 bsp_vcpu_id; 1210 1211 u64 disabled_quirks; 1212 int cpu_dirty_logging_count; 1213 1214 enum kvm_irqchip_mode irqchip_mode; 1215 u8 nr_reserved_ioapic_pins; 1216 1217 bool disabled_lapic_found; 1218 1219 bool x2apic_format; 1220 bool x2apic_broadcast_quirk_disabled; 1221 1222 bool guest_can_read_msr_platform_info; 1223 bool exception_payload_enabled; 1224 1225 bool bus_lock_detection_enabled; 1226 bool enable_pmu; 1227 /* 1228 * If exit_on_emulation_error is set, and the in-kernel instruction 1229 * emulator fails to emulate an instruction, allow userspace 1230 * the opportunity to look at it. 1231 */ 1232 bool exit_on_emulation_error; 1233 1234 /* Deflect RDMSR and WRMSR to user space when they trigger a #GP */ 1235 u32 user_space_msr_mask; 1236 struct kvm_x86_msr_filter __rcu *msr_filter; 1237 1238 u32 hypercall_exit_enabled; 1239 1240 /* Guest can access the SGX PROVISIONKEY. */ 1241 bool sgx_provisioning_allowed; 1242 1243 struct kvm_pmu_event_filter __rcu *pmu_event_filter; 1244 struct task_struct *nx_lpage_recovery_thread; 1245 1246 #ifdef CONFIG_X86_64 1247 /* 1248 * Whether the TDP MMU is enabled for this VM. This contains a 1249 * snapshot of the TDP MMU module parameter from when the VM was 1250 * created and remains unchanged for the life of the VM. If this is 1251 * true, TDP MMU handler functions will run for various MMU 1252 * operations. 1253 */ 1254 bool tdp_mmu_enabled; 1255 1256 /* 1257 * List of struct kvm_mmu_pages being used as roots. 1258 * All struct kvm_mmu_pages in the list should have 1259 * tdp_mmu_page set. 1260 * 1261 * For reads, this list is protected by: 1262 * the MMU lock in read mode + RCU or 1263 * the MMU lock in write mode 1264 * 1265 * For writes, this list is protected by: 1266 * the MMU lock in read mode + the tdp_mmu_pages_lock or 1267 * the MMU lock in write mode 1268 * 1269 * Roots will remain in the list until their tdp_mmu_root_count 1270 * drops to zero, at which point the thread that decremented the 1271 * count to zero should removed the root from the list and clean 1272 * it up, freeing the root after an RCU grace period. 1273 */ 1274 struct list_head tdp_mmu_roots; 1275 1276 /* 1277 * List of struct kvmp_mmu_pages not being used as roots. 1278 * All struct kvm_mmu_pages in the list should have 1279 * tdp_mmu_page set and a tdp_mmu_root_count of 0. 1280 */ 1281 struct list_head tdp_mmu_pages; 1282 1283 /* 1284 * Protects accesses to the following fields when the MMU lock 1285 * is held in read mode: 1286 * - tdp_mmu_roots (above) 1287 * - tdp_mmu_pages (above) 1288 * - the link field of struct kvm_mmu_pages used by the TDP MMU 1289 * - lpage_disallowed_mmu_pages 1290 * - the lpage_disallowed_link field of struct kvm_mmu_pages used 1291 * by the TDP MMU 1292 * It is acceptable, but not necessary, to acquire this lock when 1293 * the thread holds the MMU lock in write mode. 1294 */ 1295 spinlock_t tdp_mmu_pages_lock; 1296 struct workqueue_struct *tdp_mmu_zap_wq; 1297 #endif /* CONFIG_X86_64 */ 1298 1299 /* 1300 * If set, at least one shadow root has been allocated. This flag 1301 * is used as one input when determining whether certain memslot 1302 * related allocations are necessary. 1303 */ 1304 bool shadow_root_allocated; 1305 1306 #if IS_ENABLED(CONFIG_HYPERV) 1307 hpa_t hv_root_tdp; 1308 spinlock_t hv_root_tdp_lock; 1309 #endif 1310 }; 1311 1312 struct kvm_vm_stat { 1313 struct kvm_vm_stat_generic generic; 1314 u64 mmu_shadow_zapped; 1315 u64 mmu_pte_write; 1316 u64 mmu_pde_zapped; 1317 u64 mmu_flooded; 1318 u64 mmu_recycled; 1319 u64 mmu_cache_miss; 1320 u64 mmu_unsync; 1321 union { 1322 struct { 1323 atomic64_t pages_4k; 1324 atomic64_t pages_2m; 1325 atomic64_t pages_1g; 1326 }; 1327 atomic64_t pages[KVM_NR_PAGE_SIZES]; 1328 }; 1329 u64 nx_lpage_splits; 1330 u64 max_mmu_page_hash_collisions; 1331 u64 max_mmu_rmap_size; 1332 }; 1333 1334 struct kvm_vcpu_stat { 1335 struct kvm_vcpu_stat_generic generic; 1336 u64 pf_taken; 1337 u64 pf_fixed; 1338 u64 pf_emulate; 1339 u64 pf_spurious; 1340 u64 pf_fast; 1341 u64 pf_mmio_spte_created; 1342 u64 pf_guest; 1343 u64 tlb_flush; 1344 u64 invlpg; 1345 1346 u64 exits; 1347 u64 io_exits; 1348 u64 mmio_exits; 1349 u64 signal_exits; 1350 u64 irq_window_exits; 1351 u64 nmi_window_exits; 1352 u64 l1d_flush; 1353 u64 halt_exits; 1354 u64 request_irq_exits; 1355 u64 irq_exits; 1356 u64 host_state_reload; 1357 u64 fpu_reload; 1358 u64 insn_emulation; 1359 u64 insn_emulation_fail; 1360 u64 hypercalls; 1361 u64 irq_injections; 1362 u64 nmi_injections; 1363 u64 req_event; 1364 u64 nested_run; 1365 u64 directed_yield_attempted; 1366 u64 directed_yield_successful; 1367 u64 preemption_reported; 1368 u64 preemption_other; 1369 u64 guest_mode; 1370 }; 1371 1372 struct x86_instruction_info; 1373 1374 struct msr_data { 1375 bool host_initiated; 1376 u32 index; 1377 u64 data; 1378 }; 1379 1380 struct kvm_lapic_irq { 1381 u32 vector; 1382 u16 delivery_mode; 1383 u16 dest_mode; 1384 bool level; 1385 u16 trig_mode; 1386 u32 shorthand; 1387 u32 dest_id; 1388 bool msi_redir_hint; 1389 }; 1390 1391 static inline u16 kvm_lapic_irq_dest_mode(bool dest_mode_logical) 1392 { 1393 return dest_mode_logical ? APIC_DEST_LOGICAL : APIC_DEST_PHYSICAL; 1394 } 1395 1396 struct kvm_x86_ops { 1397 const char *name; 1398 1399 int (*hardware_enable)(void); 1400 void (*hardware_disable)(void); 1401 void (*hardware_unsetup)(void); 1402 bool (*has_emulated_msr)(struct kvm *kvm, u32 index); 1403 void (*vcpu_after_set_cpuid)(struct kvm_vcpu *vcpu); 1404 1405 unsigned int vm_size; 1406 int (*vm_init)(struct kvm *kvm); 1407 void (*vm_destroy)(struct kvm *kvm); 1408 1409 /* Create, but do not attach this VCPU */ 1410 int (*vcpu_create)(struct kvm_vcpu *vcpu); 1411 void (*vcpu_free)(struct kvm_vcpu *vcpu); 1412 void (*vcpu_reset)(struct kvm_vcpu *vcpu, bool init_event); 1413 1414 void (*prepare_switch_to_guest)(struct kvm_vcpu *vcpu); 1415 void (*vcpu_load)(struct kvm_vcpu *vcpu, int cpu); 1416 void (*vcpu_put)(struct kvm_vcpu *vcpu); 1417 1418 void (*update_exception_bitmap)(struct kvm_vcpu *vcpu); 1419 int (*get_msr)(struct kvm_vcpu *vcpu, struct msr_data *msr); 1420 int (*set_msr)(struct kvm_vcpu *vcpu, struct msr_data *msr); 1421 u64 (*get_segment_base)(struct kvm_vcpu *vcpu, int seg); 1422 void (*get_segment)(struct kvm_vcpu *vcpu, 1423 struct kvm_segment *var, int seg); 1424 int (*get_cpl)(struct kvm_vcpu *vcpu); 1425 void (*set_segment)(struct kvm_vcpu *vcpu, 1426 struct kvm_segment *var, int seg); 1427 void (*get_cs_db_l_bits)(struct kvm_vcpu *vcpu, int *db, int *l); 1428 void (*set_cr0)(struct kvm_vcpu *vcpu, unsigned long cr0); 1429 void (*post_set_cr3)(struct kvm_vcpu *vcpu, unsigned long cr3); 1430 bool (*is_valid_cr4)(struct kvm_vcpu *vcpu, unsigned long cr0); 1431 void (*set_cr4)(struct kvm_vcpu *vcpu, unsigned long cr4); 1432 int (*set_efer)(struct kvm_vcpu *vcpu, u64 efer); 1433 void (*get_idt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt); 1434 void (*set_idt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt); 1435 void (*get_gdt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt); 1436 void (*set_gdt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt); 1437 void (*sync_dirty_debug_regs)(struct kvm_vcpu *vcpu); 1438 void (*set_dr7)(struct kvm_vcpu *vcpu, unsigned long value); 1439 void (*cache_reg)(struct kvm_vcpu *vcpu, enum kvm_reg reg); 1440 unsigned long (*get_rflags)(struct kvm_vcpu *vcpu); 1441 void (*set_rflags)(struct kvm_vcpu *vcpu, unsigned long rflags); 1442 bool (*get_if_flag)(struct kvm_vcpu *vcpu); 1443 1444 void (*flush_tlb_all)(struct kvm_vcpu *vcpu); 1445 void (*flush_tlb_current)(struct kvm_vcpu *vcpu); 1446 int (*tlb_remote_flush)(struct kvm *kvm); 1447 int (*tlb_remote_flush_with_range)(struct kvm *kvm, 1448 struct kvm_tlb_range *range); 1449 1450 /* 1451 * Flush any TLB entries associated with the given GVA. 1452 * Does not need to flush GPA->HPA mappings. 1453 * Can potentially get non-canonical addresses through INVLPGs, which 1454 * the implementation may choose to ignore if appropriate. 1455 */ 1456 void (*flush_tlb_gva)(struct kvm_vcpu *vcpu, gva_t addr); 1457 1458 /* 1459 * Flush any TLB entries created by the guest. Like tlb_flush_gva(), 1460 * does not need to flush GPA->HPA mappings. 1461 */ 1462 void (*flush_tlb_guest)(struct kvm_vcpu *vcpu); 1463 1464 int (*vcpu_pre_run)(struct kvm_vcpu *vcpu); 1465 enum exit_fastpath_completion (*vcpu_run)(struct kvm_vcpu *vcpu); 1466 int (*handle_exit)(struct kvm_vcpu *vcpu, 1467 enum exit_fastpath_completion exit_fastpath); 1468 int (*skip_emulated_instruction)(struct kvm_vcpu *vcpu); 1469 void (*update_emulated_instruction)(struct kvm_vcpu *vcpu); 1470 void (*set_interrupt_shadow)(struct kvm_vcpu *vcpu, int mask); 1471 u32 (*get_interrupt_shadow)(struct kvm_vcpu *vcpu); 1472 void (*patch_hypercall)(struct kvm_vcpu *vcpu, 1473 unsigned char *hypercall_addr); 1474 void (*inject_irq)(struct kvm_vcpu *vcpu); 1475 void (*inject_nmi)(struct kvm_vcpu *vcpu); 1476 void (*queue_exception)(struct kvm_vcpu *vcpu); 1477 void (*cancel_injection)(struct kvm_vcpu *vcpu); 1478 int (*interrupt_allowed)(struct kvm_vcpu *vcpu, bool for_injection); 1479 int (*nmi_allowed)(struct kvm_vcpu *vcpu, bool for_injection); 1480 bool (*get_nmi_mask)(struct kvm_vcpu *vcpu); 1481 void (*set_nmi_mask)(struct kvm_vcpu *vcpu, bool masked); 1482 void (*enable_nmi_window)(struct kvm_vcpu *vcpu); 1483 void (*enable_irq_window)(struct kvm_vcpu *vcpu); 1484 void (*update_cr8_intercept)(struct kvm_vcpu *vcpu, int tpr, int irr); 1485 bool (*check_apicv_inhibit_reasons)(enum kvm_apicv_inhibit reason); 1486 void (*refresh_apicv_exec_ctrl)(struct kvm_vcpu *vcpu); 1487 void (*hwapic_irr_update)(struct kvm_vcpu *vcpu, int max_irr); 1488 void (*hwapic_isr_update)(struct kvm_vcpu *vcpu, int isr); 1489 bool (*guest_apic_has_interrupt)(struct kvm_vcpu *vcpu); 1490 void (*load_eoi_exitmap)(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap); 1491 void (*set_virtual_apic_mode)(struct kvm_vcpu *vcpu); 1492 void (*set_apic_access_page_addr)(struct kvm_vcpu *vcpu); 1493 void (*deliver_interrupt)(struct kvm_lapic *apic, int delivery_mode, 1494 int trig_mode, int vector); 1495 int (*sync_pir_to_irr)(struct kvm_vcpu *vcpu); 1496 int (*set_tss_addr)(struct kvm *kvm, unsigned int addr); 1497 int (*set_identity_map_addr)(struct kvm *kvm, u64 ident_addr); 1498 u64 (*get_mt_mask)(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio); 1499 1500 void (*load_mmu_pgd)(struct kvm_vcpu *vcpu, hpa_t root_hpa, 1501 int root_level); 1502 1503 bool (*has_wbinvd_exit)(void); 1504 1505 u64 (*get_l2_tsc_offset)(struct kvm_vcpu *vcpu); 1506 u64 (*get_l2_tsc_multiplier)(struct kvm_vcpu *vcpu); 1507 void (*write_tsc_offset)(struct kvm_vcpu *vcpu, u64 offset); 1508 void (*write_tsc_multiplier)(struct kvm_vcpu *vcpu, u64 multiplier); 1509 1510 /* 1511 * Retrieve somewhat arbitrary exit information. Intended to 1512 * be used only from within tracepoints or error paths. 1513 */ 1514 void (*get_exit_info)(struct kvm_vcpu *vcpu, u32 *reason, 1515 u64 *info1, u64 *info2, 1516 u32 *exit_int_info, u32 *exit_int_info_err_code); 1517 1518 int (*check_intercept)(struct kvm_vcpu *vcpu, 1519 struct x86_instruction_info *info, 1520 enum x86_intercept_stage stage, 1521 struct x86_exception *exception); 1522 void (*handle_exit_irqoff)(struct kvm_vcpu *vcpu); 1523 1524 void (*request_immediate_exit)(struct kvm_vcpu *vcpu); 1525 1526 void (*sched_in)(struct kvm_vcpu *kvm, int cpu); 1527 1528 /* 1529 * Size of the CPU's dirty log buffer, i.e. VMX's PML buffer. A zero 1530 * value indicates CPU dirty logging is unsupported or disabled. 1531 */ 1532 int cpu_dirty_log_size; 1533 void (*update_cpu_dirty_logging)(struct kvm_vcpu *vcpu); 1534 1535 const struct kvm_x86_nested_ops *nested_ops; 1536 1537 void (*vcpu_blocking)(struct kvm_vcpu *vcpu); 1538 void (*vcpu_unblocking)(struct kvm_vcpu *vcpu); 1539 1540 int (*pi_update_irte)(struct kvm *kvm, unsigned int host_irq, 1541 uint32_t guest_irq, bool set); 1542 void (*pi_start_assignment)(struct kvm *kvm); 1543 void (*apicv_post_state_restore)(struct kvm_vcpu *vcpu); 1544 bool (*dy_apicv_has_pending_interrupt)(struct kvm_vcpu *vcpu); 1545 1546 int (*set_hv_timer)(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc, 1547 bool *expired); 1548 void (*cancel_hv_timer)(struct kvm_vcpu *vcpu); 1549 1550 void (*setup_mce)(struct kvm_vcpu *vcpu); 1551 1552 int (*smi_allowed)(struct kvm_vcpu *vcpu, bool for_injection); 1553 int (*enter_smm)(struct kvm_vcpu *vcpu, char *smstate); 1554 int (*leave_smm)(struct kvm_vcpu *vcpu, const char *smstate); 1555 void (*enable_smi_window)(struct kvm_vcpu *vcpu); 1556 1557 int (*mem_enc_ioctl)(struct kvm *kvm, void __user *argp); 1558 int (*mem_enc_register_region)(struct kvm *kvm, struct kvm_enc_region *argp); 1559 int (*mem_enc_unregister_region)(struct kvm *kvm, struct kvm_enc_region *argp); 1560 int (*vm_copy_enc_context_from)(struct kvm *kvm, unsigned int source_fd); 1561 int (*vm_move_enc_context_from)(struct kvm *kvm, unsigned int source_fd); 1562 void (*guest_memory_reclaimed)(struct kvm *kvm); 1563 1564 int (*get_msr_feature)(struct kvm_msr_entry *entry); 1565 1566 bool (*can_emulate_instruction)(struct kvm_vcpu *vcpu, int emul_type, 1567 void *insn, int insn_len); 1568 1569 bool (*apic_init_signal_blocked)(struct kvm_vcpu *vcpu); 1570 int (*enable_direct_tlbflush)(struct kvm_vcpu *vcpu); 1571 1572 void (*migrate_timers)(struct kvm_vcpu *vcpu); 1573 void (*msr_filter_changed)(struct kvm_vcpu *vcpu); 1574 int (*complete_emulated_msr)(struct kvm_vcpu *vcpu, int err); 1575 1576 void (*vcpu_deliver_sipi_vector)(struct kvm_vcpu *vcpu, u8 vector); 1577 1578 /* 1579 * Returns vCPU specific APICv inhibit reasons 1580 */ 1581 unsigned long (*vcpu_get_apicv_inhibit_reasons)(struct kvm_vcpu *vcpu); 1582 }; 1583 1584 struct kvm_x86_nested_ops { 1585 void (*leave_nested)(struct kvm_vcpu *vcpu); 1586 int (*check_events)(struct kvm_vcpu *vcpu); 1587 bool (*handle_page_fault_workaround)(struct kvm_vcpu *vcpu, 1588 struct x86_exception *fault); 1589 bool (*hv_timer_pending)(struct kvm_vcpu *vcpu); 1590 void (*triple_fault)(struct kvm_vcpu *vcpu); 1591 int (*get_state)(struct kvm_vcpu *vcpu, 1592 struct kvm_nested_state __user *user_kvm_nested_state, 1593 unsigned user_data_size); 1594 int (*set_state)(struct kvm_vcpu *vcpu, 1595 struct kvm_nested_state __user *user_kvm_nested_state, 1596 struct kvm_nested_state *kvm_state); 1597 bool (*get_nested_state_pages)(struct kvm_vcpu *vcpu); 1598 int (*write_log_dirty)(struct kvm_vcpu *vcpu, gpa_t l2_gpa); 1599 1600 int (*enable_evmcs)(struct kvm_vcpu *vcpu, 1601 uint16_t *vmcs_version); 1602 uint16_t (*get_evmcs_version)(struct kvm_vcpu *vcpu); 1603 }; 1604 1605 struct kvm_x86_init_ops { 1606 int (*cpu_has_kvm_support)(void); 1607 int (*disabled_by_bios)(void); 1608 int (*check_processor_compatibility)(void); 1609 int (*hardware_setup)(void); 1610 unsigned int (*handle_intel_pt_intr)(void); 1611 1612 struct kvm_x86_ops *runtime_ops; 1613 struct kvm_pmu_ops *pmu_ops; 1614 }; 1615 1616 struct kvm_arch_async_pf { 1617 u32 token; 1618 gfn_t gfn; 1619 unsigned long cr3; 1620 bool direct_map; 1621 }; 1622 1623 extern u32 __read_mostly kvm_nr_uret_msrs; 1624 extern u64 __read_mostly host_efer; 1625 extern bool __read_mostly allow_smaller_maxphyaddr; 1626 extern bool __read_mostly enable_apicv; 1627 extern struct kvm_x86_ops kvm_x86_ops; 1628 1629 #define KVM_X86_OP(func) \ 1630 DECLARE_STATIC_CALL(kvm_x86_##func, *(((struct kvm_x86_ops *)0)->func)); 1631 #define KVM_X86_OP_OPTIONAL KVM_X86_OP 1632 #define KVM_X86_OP_OPTIONAL_RET0 KVM_X86_OP 1633 #include <asm/kvm-x86-ops.h> 1634 1635 #define __KVM_HAVE_ARCH_VM_ALLOC 1636 static inline struct kvm *kvm_arch_alloc_vm(void) 1637 { 1638 return __vmalloc(kvm_x86_ops.vm_size, GFP_KERNEL_ACCOUNT | __GFP_ZERO); 1639 } 1640 1641 #define __KVM_HAVE_ARCH_VM_FREE 1642 void kvm_arch_free_vm(struct kvm *kvm); 1643 1644 #define __KVM_HAVE_ARCH_FLUSH_REMOTE_TLB 1645 static inline int kvm_arch_flush_remote_tlb(struct kvm *kvm) 1646 { 1647 if (kvm_x86_ops.tlb_remote_flush && 1648 !static_call(kvm_x86_tlb_remote_flush)(kvm)) 1649 return 0; 1650 else 1651 return -ENOTSUPP; 1652 } 1653 1654 #define kvm_arch_pmi_in_guest(vcpu) \ 1655 ((vcpu) && (vcpu)->arch.handling_intr_from_guest) 1656 1657 void kvm_mmu_x86_module_init(void); 1658 int kvm_mmu_vendor_module_init(void); 1659 void kvm_mmu_vendor_module_exit(void); 1660 1661 void kvm_mmu_destroy(struct kvm_vcpu *vcpu); 1662 int kvm_mmu_create(struct kvm_vcpu *vcpu); 1663 int kvm_mmu_init_vm(struct kvm *kvm); 1664 void kvm_mmu_uninit_vm(struct kvm *kvm); 1665 1666 void kvm_mmu_after_set_cpuid(struct kvm_vcpu *vcpu); 1667 void kvm_mmu_reset_context(struct kvm_vcpu *vcpu); 1668 void kvm_mmu_slot_remove_write_access(struct kvm *kvm, 1669 const struct kvm_memory_slot *memslot, 1670 int start_level); 1671 void kvm_mmu_slot_try_split_huge_pages(struct kvm *kvm, 1672 const struct kvm_memory_slot *memslot, 1673 int target_level); 1674 void kvm_mmu_try_split_huge_pages(struct kvm *kvm, 1675 const struct kvm_memory_slot *memslot, 1676 u64 start, u64 end, 1677 int target_level); 1678 void kvm_mmu_zap_collapsible_sptes(struct kvm *kvm, 1679 const struct kvm_memory_slot *memslot); 1680 void kvm_mmu_slot_leaf_clear_dirty(struct kvm *kvm, 1681 const struct kvm_memory_slot *memslot); 1682 void kvm_mmu_zap_all(struct kvm *kvm); 1683 void kvm_mmu_invalidate_mmio_sptes(struct kvm *kvm, u64 gen); 1684 void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned long kvm_nr_mmu_pages); 1685 1686 int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3); 1687 1688 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa, 1689 const void *val, int bytes); 1690 1691 struct kvm_irq_mask_notifier { 1692 void (*func)(struct kvm_irq_mask_notifier *kimn, bool masked); 1693 int irq; 1694 struct hlist_node link; 1695 }; 1696 1697 void kvm_register_irq_mask_notifier(struct kvm *kvm, int irq, 1698 struct kvm_irq_mask_notifier *kimn); 1699 void kvm_unregister_irq_mask_notifier(struct kvm *kvm, int irq, 1700 struct kvm_irq_mask_notifier *kimn); 1701 void kvm_fire_mask_notifiers(struct kvm *kvm, unsigned irqchip, unsigned pin, 1702 bool mask); 1703 1704 extern bool tdp_enabled; 1705 1706 u64 vcpu_tsc_khz(struct kvm_vcpu *vcpu); 1707 1708 /* control of guest tsc rate supported? */ 1709 extern bool kvm_has_tsc_control; 1710 /* maximum supported tsc_khz for guests */ 1711 extern u32 kvm_max_guest_tsc_khz; 1712 /* number of bits of the fractional part of the TSC scaling ratio */ 1713 extern u8 kvm_tsc_scaling_ratio_frac_bits; 1714 /* maximum allowed value of TSC scaling ratio */ 1715 extern u64 kvm_max_tsc_scaling_ratio; 1716 /* 1ull << kvm_tsc_scaling_ratio_frac_bits */ 1717 extern u64 kvm_default_tsc_scaling_ratio; 1718 /* bus lock detection supported? */ 1719 extern bool kvm_has_bus_lock_exit; 1720 1721 extern u64 kvm_mce_cap_supported; 1722 1723 /* 1724 * EMULTYPE_NO_DECODE - Set when re-emulating an instruction (after completing 1725 * userspace I/O) to indicate that the emulation context 1726 * should be reused as is, i.e. skip initialization of 1727 * emulation context, instruction fetch and decode. 1728 * 1729 * EMULTYPE_TRAP_UD - Set when emulating an intercepted #UD from hardware. 1730 * Indicates that only select instructions (tagged with 1731 * EmulateOnUD) should be emulated (to minimize the emulator 1732 * attack surface). See also EMULTYPE_TRAP_UD_FORCED. 1733 * 1734 * EMULTYPE_SKIP - Set when emulating solely to skip an instruction, i.e. to 1735 * decode the instruction length. For use *only* by 1736 * kvm_x86_ops.skip_emulated_instruction() implementations if 1737 * EMULTYPE_COMPLETE_USER_EXIT is not set. 1738 * 1739 * EMULTYPE_ALLOW_RETRY_PF - Set when the emulator should resume the guest to 1740 * retry native execution under certain conditions, 1741 * Can only be set in conjunction with EMULTYPE_PF. 1742 * 1743 * EMULTYPE_TRAP_UD_FORCED - Set when emulating an intercepted #UD that was 1744 * triggered by KVM's magic "force emulation" prefix, 1745 * which is opt in via module param (off by default). 1746 * Bypasses EmulateOnUD restriction despite emulating 1747 * due to an intercepted #UD (see EMULTYPE_TRAP_UD). 1748 * Used to test the full emulator from userspace. 1749 * 1750 * EMULTYPE_VMWARE_GP - Set when emulating an intercepted #GP for VMware 1751 * backdoor emulation, which is opt in via module param. 1752 * VMware backdoor emulation handles select instructions 1753 * and reinjects the #GP for all other cases. 1754 * 1755 * EMULTYPE_PF - Set when emulating MMIO by way of an intercepted #PF, in which 1756 * case the CR2/GPA value pass on the stack is valid. 1757 * 1758 * EMULTYPE_COMPLETE_USER_EXIT - Set when the emulator should update interruptibility 1759 * state and inject single-step #DBs after skipping 1760 * an instruction (after completing userspace I/O). 1761 */ 1762 #define EMULTYPE_NO_DECODE (1 << 0) 1763 #define EMULTYPE_TRAP_UD (1 << 1) 1764 #define EMULTYPE_SKIP (1 << 2) 1765 #define EMULTYPE_ALLOW_RETRY_PF (1 << 3) 1766 #define EMULTYPE_TRAP_UD_FORCED (1 << 4) 1767 #define EMULTYPE_VMWARE_GP (1 << 5) 1768 #define EMULTYPE_PF (1 << 6) 1769 #define EMULTYPE_COMPLETE_USER_EXIT (1 << 7) 1770 1771 int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type); 1772 int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu, 1773 void *insn, int insn_len); 1774 void __kvm_prepare_emulation_failure_exit(struct kvm_vcpu *vcpu, 1775 u64 *data, u8 ndata); 1776 void kvm_prepare_emulation_failure_exit(struct kvm_vcpu *vcpu); 1777 1778 void kvm_enable_efer_bits(u64); 1779 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer); 1780 int __kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data, bool host_initiated); 1781 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data); 1782 int kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data); 1783 int kvm_emulate_rdmsr(struct kvm_vcpu *vcpu); 1784 int kvm_emulate_wrmsr(struct kvm_vcpu *vcpu); 1785 int kvm_emulate_as_nop(struct kvm_vcpu *vcpu); 1786 int kvm_emulate_invd(struct kvm_vcpu *vcpu); 1787 int kvm_emulate_mwait(struct kvm_vcpu *vcpu); 1788 int kvm_handle_invalid_op(struct kvm_vcpu *vcpu); 1789 int kvm_emulate_monitor(struct kvm_vcpu *vcpu); 1790 1791 int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in); 1792 int kvm_emulate_cpuid(struct kvm_vcpu *vcpu); 1793 int kvm_emulate_halt(struct kvm_vcpu *vcpu); 1794 int kvm_emulate_halt_noskip(struct kvm_vcpu *vcpu); 1795 int kvm_emulate_ap_reset_hold(struct kvm_vcpu *vcpu); 1796 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu); 1797 1798 void kvm_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg); 1799 int kvm_load_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector, int seg); 1800 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector); 1801 1802 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index, 1803 int reason, bool has_error_code, u32 error_code); 1804 1805 void kvm_post_set_cr0(struct kvm_vcpu *vcpu, unsigned long old_cr0, unsigned long cr0); 1806 void kvm_post_set_cr4(struct kvm_vcpu *vcpu, unsigned long old_cr4, unsigned long cr4); 1807 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0); 1808 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3); 1809 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4); 1810 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8); 1811 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val); 1812 void kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val); 1813 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu); 1814 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw); 1815 int kvm_emulate_xsetbv(struct kvm_vcpu *vcpu); 1816 1817 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr); 1818 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr); 1819 1820 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu); 1821 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags); 1822 int kvm_emulate_rdpmc(struct kvm_vcpu *vcpu); 1823 1824 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr); 1825 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code); 1826 void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr, unsigned long payload); 1827 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr); 1828 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code); 1829 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault); 1830 bool kvm_inject_emulated_page_fault(struct kvm_vcpu *vcpu, 1831 struct x86_exception *fault); 1832 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl); 1833 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr); 1834 1835 static inline int __kvm_irq_line_state(unsigned long *irq_state, 1836 int irq_source_id, int level) 1837 { 1838 /* Logical OR for level trig interrupt */ 1839 if (level) 1840 __set_bit(irq_source_id, irq_state); 1841 else 1842 __clear_bit(irq_source_id, irq_state); 1843 1844 return !!(*irq_state); 1845 } 1846 1847 #define KVM_MMU_ROOT_CURRENT BIT(0) 1848 #define KVM_MMU_ROOT_PREVIOUS(i) BIT(1+i) 1849 #define KVM_MMU_ROOTS_ALL (~0UL) 1850 1851 int kvm_pic_set_irq(struct kvm_pic *pic, int irq, int irq_source_id, int level); 1852 void kvm_pic_clear_all(struct kvm_pic *pic, int irq_source_id); 1853 1854 void kvm_inject_nmi(struct kvm_vcpu *vcpu); 1855 1856 void kvm_update_dr7(struct kvm_vcpu *vcpu); 1857 1858 int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn); 1859 void kvm_mmu_free_roots(struct kvm *kvm, struct kvm_mmu *mmu, 1860 ulong roots_to_free); 1861 void kvm_mmu_free_guest_mode_roots(struct kvm *kvm, struct kvm_mmu *mmu); 1862 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, 1863 struct x86_exception *exception); 1864 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, 1865 struct x86_exception *exception); 1866 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, 1867 struct x86_exception *exception); 1868 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, 1869 struct x86_exception *exception); 1870 1871 bool kvm_apicv_activated(struct kvm *kvm); 1872 bool kvm_vcpu_apicv_activated(struct kvm_vcpu *vcpu); 1873 void kvm_vcpu_update_apicv(struct kvm_vcpu *vcpu); 1874 void __kvm_set_or_clear_apicv_inhibit(struct kvm *kvm, 1875 enum kvm_apicv_inhibit reason, bool set); 1876 void kvm_set_or_clear_apicv_inhibit(struct kvm *kvm, 1877 enum kvm_apicv_inhibit reason, bool set); 1878 1879 static inline void kvm_set_apicv_inhibit(struct kvm *kvm, 1880 enum kvm_apicv_inhibit reason) 1881 { 1882 kvm_set_or_clear_apicv_inhibit(kvm, reason, true); 1883 } 1884 1885 static inline void kvm_clear_apicv_inhibit(struct kvm *kvm, 1886 enum kvm_apicv_inhibit reason) 1887 { 1888 kvm_set_or_clear_apicv_inhibit(kvm, reason, false); 1889 } 1890 1891 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu); 1892 1893 int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, u64 error_code, 1894 void *insn, int insn_len); 1895 void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva); 1896 void kvm_mmu_invalidate_gva(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, 1897 gva_t gva, hpa_t root_hpa); 1898 void kvm_mmu_invpcid_gva(struct kvm_vcpu *vcpu, gva_t gva, unsigned long pcid); 1899 void kvm_mmu_new_pgd(struct kvm_vcpu *vcpu, gpa_t new_pgd); 1900 1901 void kvm_configure_mmu(bool enable_tdp, int tdp_forced_root_level, 1902 int tdp_max_root_level, int tdp_huge_page_level); 1903 1904 static inline u16 kvm_read_ldt(void) 1905 { 1906 u16 ldt; 1907 asm("sldt %0" : "=g"(ldt)); 1908 return ldt; 1909 } 1910 1911 static inline void kvm_load_ldt(u16 sel) 1912 { 1913 asm("lldt %0" : : "rm"(sel)); 1914 } 1915 1916 #ifdef CONFIG_X86_64 1917 static inline unsigned long read_msr(unsigned long msr) 1918 { 1919 u64 value; 1920 1921 rdmsrl(msr, value); 1922 return value; 1923 } 1924 #endif 1925 1926 static inline void kvm_inject_gp(struct kvm_vcpu *vcpu, u32 error_code) 1927 { 1928 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code); 1929 } 1930 1931 #define TSS_IOPB_BASE_OFFSET 0x66 1932 #define TSS_BASE_SIZE 0x68 1933 #define TSS_IOPB_SIZE (65536 / 8) 1934 #define TSS_REDIRECTION_SIZE (256 / 8) 1935 #define RMODE_TSS_SIZE \ 1936 (TSS_BASE_SIZE + TSS_REDIRECTION_SIZE + TSS_IOPB_SIZE + 1) 1937 1938 enum { 1939 TASK_SWITCH_CALL = 0, 1940 TASK_SWITCH_IRET = 1, 1941 TASK_SWITCH_JMP = 2, 1942 TASK_SWITCH_GATE = 3, 1943 }; 1944 1945 #define HF_GIF_MASK (1 << 0) 1946 #define HF_NMI_MASK (1 << 3) 1947 #define HF_IRET_MASK (1 << 4) 1948 #define HF_GUEST_MASK (1 << 5) /* VCPU is in guest-mode */ 1949 #define HF_SMM_MASK (1 << 6) 1950 #define HF_SMM_INSIDE_NMI_MASK (1 << 7) 1951 1952 #define __KVM_VCPU_MULTIPLE_ADDRESS_SPACE 1953 #define KVM_ADDRESS_SPACE_NUM 2 1954 1955 #define kvm_arch_vcpu_memslots_id(vcpu) ((vcpu)->arch.hflags & HF_SMM_MASK ? 1 : 0) 1956 #define kvm_memslots_for_spte_role(kvm, role) __kvm_memslots(kvm, (role).smm) 1957 1958 #define KVM_ARCH_WANT_MMU_NOTIFIER 1959 1960 int kvm_cpu_has_injectable_intr(struct kvm_vcpu *v); 1961 int kvm_cpu_has_interrupt(struct kvm_vcpu *vcpu); 1962 int kvm_cpu_has_extint(struct kvm_vcpu *v); 1963 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu); 1964 int kvm_cpu_get_interrupt(struct kvm_vcpu *v); 1965 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event); 1966 1967 int kvm_pv_send_ipi(struct kvm *kvm, unsigned long ipi_bitmap_low, 1968 unsigned long ipi_bitmap_high, u32 min, 1969 unsigned long icr, int op_64_bit); 1970 1971 int kvm_add_user_return_msr(u32 msr); 1972 int kvm_find_user_return_msr(u32 msr); 1973 int kvm_set_user_return_msr(unsigned index, u64 val, u64 mask); 1974 1975 static inline bool kvm_is_supported_user_return_msr(u32 msr) 1976 { 1977 return kvm_find_user_return_msr(msr) >= 0; 1978 } 1979 1980 u64 kvm_scale_tsc(u64 tsc, u64 ratio); 1981 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc); 1982 u64 kvm_calc_nested_tsc_offset(u64 l1_offset, u64 l2_offset, u64 l2_multiplier); 1983 u64 kvm_calc_nested_tsc_multiplier(u64 l1_multiplier, u64 l2_multiplier); 1984 1985 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu); 1986 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip); 1987 1988 void kvm_make_scan_ioapic_request(struct kvm *kvm); 1989 void kvm_make_scan_ioapic_request_mask(struct kvm *kvm, 1990 unsigned long *vcpu_bitmap); 1991 1992 bool kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu, 1993 struct kvm_async_pf *work); 1994 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu, 1995 struct kvm_async_pf *work); 1996 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, 1997 struct kvm_async_pf *work); 1998 void kvm_arch_async_page_present_queued(struct kvm_vcpu *vcpu); 1999 bool kvm_arch_can_dequeue_async_page_present(struct kvm_vcpu *vcpu); 2000 extern bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn); 2001 2002 int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu); 2003 int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err); 2004 void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu); 2005 2006 void __user *__x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, 2007 u32 size); 2008 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu); 2009 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu); 2010 2011 bool kvm_intr_is_single_vcpu(struct kvm *kvm, struct kvm_lapic_irq *irq, 2012 struct kvm_vcpu **dest_vcpu); 2013 2014 void kvm_set_msi_irq(struct kvm *kvm, struct kvm_kernel_irq_routing_entry *e, 2015 struct kvm_lapic_irq *irq); 2016 2017 static inline bool kvm_irq_is_postable(struct kvm_lapic_irq *irq) 2018 { 2019 /* We can only post Fixed and LowPrio IRQs */ 2020 return (irq->delivery_mode == APIC_DM_FIXED || 2021 irq->delivery_mode == APIC_DM_LOWEST); 2022 } 2023 2024 static inline void kvm_arch_vcpu_blocking(struct kvm_vcpu *vcpu) 2025 { 2026 static_call_cond(kvm_x86_vcpu_blocking)(vcpu); 2027 } 2028 2029 static inline void kvm_arch_vcpu_unblocking(struct kvm_vcpu *vcpu) 2030 { 2031 static_call_cond(kvm_x86_vcpu_unblocking)(vcpu); 2032 } 2033 2034 static inline int kvm_cpu_get_apicid(int mps_cpu) 2035 { 2036 #ifdef CONFIG_X86_LOCAL_APIC 2037 return default_cpu_present_to_apicid(mps_cpu); 2038 #else 2039 WARN_ON_ONCE(1); 2040 return BAD_APICID; 2041 #endif 2042 } 2043 2044 #define put_smstate(type, buf, offset, val) \ 2045 *(type *)((buf) + (offset) - 0x7e00) = val 2046 2047 #define GET_SMSTATE(type, buf, offset) \ 2048 (*(type *)((buf) + (offset) - 0x7e00)) 2049 2050 int kvm_cpu_dirty_log_size(void); 2051 2052 int memslot_rmap_alloc(struct kvm_memory_slot *slot, unsigned long npages); 2053 2054 #define KVM_CLOCK_VALID_FLAGS \ 2055 (KVM_CLOCK_TSC_STABLE | KVM_CLOCK_REALTIME | KVM_CLOCK_HOST_TSC) 2056 2057 #define KVM_X86_VALID_QUIRKS \ 2058 (KVM_X86_QUIRK_LINT0_REENABLED | \ 2059 KVM_X86_QUIRK_CD_NW_CLEARED | \ 2060 KVM_X86_QUIRK_LAPIC_MMIO_HOLE | \ 2061 KVM_X86_QUIRK_OUT_7E_INC_RIP | \ 2062 KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT | \ 2063 KVM_X86_QUIRK_FIX_HYPERCALL_INSN) 2064 2065 #endif /* _ASM_X86_KVM_HOST_H */ 2066