1 /* 2 * Kernel-based Virtual Machine driver for Linux 3 * 4 * This header defines architecture specific interfaces, x86 version 5 * 6 * This work is licensed under the terms of the GNU GPL, version 2. See 7 * the COPYING file in the top-level directory. 8 * 9 */ 10 11 #ifndef _ASM_X86_KVM_HOST_H 12 #define _ASM_X86_KVM_HOST_H 13 14 #include <linux/types.h> 15 #include <linux/mm.h> 16 #include <linux/mmu_notifier.h> 17 #include <linux/tracepoint.h> 18 #include <linux/cpumask.h> 19 #include <linux/irq_work.h> 20 #include <linux/irq.h> 21 22 #include <linux/kvm.h> 23 #include <linux/kvm_para.h> 24 #include <linux/kvm_types.h> 25 #include <linux/perf_event.h> 26 #include <linux/pvclock_gtod.h> 27 #include <linux/clocksource.h> 28 #include <linux/irqbypass.h> 29 #include <linux/hyperv.h> 30 31 #include <asm/apic.h> 32 #include <asm/pvclock-abi.h> 33 #include <asm/desc.h> 34 #include <asm/mtrr.h> 35 #include <asm/msr-index.h> 36 #include <asm/asm.h> 37 #include <asm/kvm_page_track.h> 38 #include <asm/kvm_vcpu_regs.h> 39 #include <asm/hyperv-tlfs.h> 40 41 #define KVM_MAX_VCPUS 288 42 #define KVM_SOFT_MAX_VCPUS 240 43 #define KVM_MAX_VCPU_ID 1023 44 #define KVM_USER_MEM_SLOTS 509 45 /* memory slots that are not exposed to userspace */ 46 #define KVM_PRIVATE_MEM_SLOTS 3 47 #define KVM_MEM_SLOTS_NUM (KVM_USER_MEM_SLOTS + KVM_PRIVATE_MEM_SLOTS) 48 49 #define KVM_HALT_POLL_NS_DEFAULT 200000 50 51 #define KVM_IRQCHIP_NUM_PINS KVM_IOAPIC_NUM_PINS 52 53 /* x86-specific vcpu->requests bit members */ 54 #define KVM_REQ_MIGRATE_TIMER KVM_ARCH_REQ(0) 55 #define KVM_REQ_REPORT_TPR_ACCESS KVM_ARCH_REQ(1) 56 #define KVM_REQ_TRIPLE_FAULT KVM_ARCH_REQ(2) 57 #define KVM_REQ_MMU_SYNC KVM_ARCH_REQ(3) 58 #define KVM_REQ_CLOCK_UPDATE KVM_ARCH_REQ(4) 59 #define KVM_REQ_LOAD_CR3 KVM_ARCH_REQ(5) 60 #define KVM_REQ_EVENT KVM_ARCH_REQ(6) 61 #define KVM_REQ_APF_HALT KVM_ARCH_REQ(7) 62 #define KVM_REQ_STEAL_UPDATE KVM_ARCH_REQ(8) 63 #define KVM_REQ_NMI KVM_ARCH_REQ(9) 64 #define KVM_REQ_PMU KVM_ARCH_REQ(10) 65 #define KVM_REQ_PMI KVM_ARCH_REQ(11) 66 #define KVM_REQ_SMI KVM_ARCH_REQ(12) 67 #define KVM_REQ_MASTERCLOCK_UPDATE KVM_ARCH_REQ(13) 68 #define KVM_REQ_MCLOCK_INPROGRESS \ 69 KVM_ARCH_REQ_FLAGS(14, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP) 70 #define KVM_REQ_SCAN_IOAPIC \ 71 KVM_ARCH_REQ_FLAGS(15, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP) 72 #define KVM_REQ_GLOBAL_CLOCK_UPDATE KVM_ARCH_REQ(16) 73 #define KVM_REQ_APIC_PAGE_RELOAD \ 74 KVM_ARCH_REQ_FLAGS(17, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP) 75 #define KVM_REQ_HV_CRASH KVM_ARCH_REQ(18) 76 #define KVM_REQ_IOAPIC_EOI_EXIT KVM_ARCH_REQ(19) 77 #define KVM_REQ_HV_RESET KVM_ARCH_REQ(20) 78 #define KVM_REQ_HV_EXIT KVM_ARCH_REQ(21) 79 #define KVM_REQ_HV_STIMER KVM_ARCH_REQ(22) 80 #define KVM_REQ_LOAD_EOI_EXITMAP KVM_ARCH_REQ(23) 81 #define KVM_REQ_GET_VMCS12_PAGES KVM_ARCH_REQ(24) 82 83 #define CR0_RESERVED_BITS \ 84 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \ 85 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \ 86 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG)) 87 88 #define CR4_RESERVED_BITS \ 89 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\ 90 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \ 91 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR | X86_CR4_PCIDE \ 92 | X86_CR4_OSXSAVE | X86_CR4_SMEP | X86_CR4_FSGSBASE \ 93 | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_VMXE \ 94 | X86_CR4_SMAP | X86_CR4_PKE | X86_CR4_UMIP)) 95 96 #define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR) 97 98 99 100 #define INVALID_PAGE (~(hpa_t)0) 101 #define VALID_PAGE(x) ((x) != INVALID_PAGE) 102 103 #define UNMAPPED_GVA (~(gpa_t)0) 104 105 /* KVM Hugepage definitions for x86 */ 106 enum { 107 PT_PAGE_TABLE_LEVEL = 1, 108 PT_DIRECTORY_LEVEL = 2, 109 PT_PDPE_LEVEL = 3, 110 /* set max level to the biggest one */ 111 PT_MAX_HUGEPAGE_LEVEL = PT_PDPE_LEVEL, 112 }; 113 #define KVM_NR_PAGE_SIZES (PT_MAX_HUGEPAGE_LEVEL - \ 114 PT_PAGE_TABLE_LEVEL + 1) 115 #define KVM_HPAGE_GFN_SHIFT(x) (((x) - 1) * 9) 116 #define KVM_HPAGE_SHIFT(x) (PAGE_SHIFT + KVM_HPAGE_GFN_SHIFT(x)) 117 #define KVM_HPAGE_SIZE(x) (1UL << KVM_HPAGE_SHIFT(x)) 118 #define KVM_HPAGE_MASK(x) (~(KVM_HPAGE_SIZE(x) - 1)) 119 #define KVM_PAGES_PER_HPAGE(x) (KVM_HPAGE_SIZE(x) / PAGE_SIZE) 120 121 static inline gfn_t gfn_to_index(gfn_t gfn, gfn_t base_gfn, int level) 122 { 123 /* KVM_HPAGE_GFN_SHIFT(PT_PAGE_TABLE_LEVEL) must be 0. */ 124 return (gfn >> KVM_HPAGE_GFN_SHIFT(level)) - 125 (base_gfn >> KVM_HPAGE_GFN_SHIFT(level)); 126 } 127 128 #define KVM_PERMILLE_MMU_PAGES 20 129 #define KVM_MIN_ALLOC_MMU_PAGES 64UL 130 #define KVM_MMU_HASH_SHIFT 12 131 #define KVM_NUM_MMU_PAGES (1 << KVM_MMU_HASH_SHIFT) 132 #define KVM_MIN_FREE_MMU_PAGES 5 133 #define KVM_REFILL_PAGES 25 134 #define KVM_MAX_CPUID_ENTRIES 80 135 #define KVM_NR_FIXED_MTRR_REGION 88 136 #define KVM_NR_VAR_MTRR 8 137 138 #define ASYNC_PF_PER_VCPU 64 139 140 enum kvm_reg { 141 VCPU_REGS_RAX = __VCPU_REGS_RAX, 142 VCPU_REGS_RCX = __VCPU_REGS_RCX, 143 VCPU_REGS_RDX = __VCPU_REGS_RDX, 144 VCPU_REGS_RBX = __VCPU_REGS_RBX, 145 VCPU_REGS_RSP = __VCPU_REGS_RSP, 146 VCPU_REGS_RBP = __VCPU_REGS_RBP, 147 VCPU_REGS_RSI = __VCPU_REGS_RSI, 148 VCPU_REGS_RDI = __VCPU_REGS_RDI, 149 #ifdef CONFIG_X86_64 150 VCPU_REGS_R8 = __VCPU_REGS_R8, 151 VCPU_REGS_R9 = __VCPU_REGS_R9, 152 VCPU_REGS_R10 = __VCPU_REGS_R10, 153 VCPU_REGS_R11 = __VCPU_REGS_R11, 154 VCPU_REGS_R12 = __VCPU_REGS_R12, 155 VCPU_REGS_R13 = __VCPU_REGS_R13, 156 VCPU_REGS_R14 = __VCPU_REGS_R14, 157 VCPU_REGS_R15 = __VCPU_REGS_R15, 158 #endif 159 VCPU_REGS_RIP, 160 NR_VCPU_REGS 161 }; 162 163 enum kvm_reg_ex { 164 VCPU_EXREG_PDPTR = NR_VCPU_REGS, 165 VCPU_EXREG_CR3, 166 VCPU_EXREG_RFLAGS, 167 VCPU_EXREG_SEGMENTS, 168 }; 169 170 enum { 171 VCPU_SREG_ES, 172 VCPU_SREG_CS, 173 VCPU_SREG_SS, 174 VCPU_SREG_DS, 175 VCPU_SREG_FS, 176 VCPU_SREG_GS, 177 VCPU_SREG_TR, 178 VCPU_SREG_LDTR, 179 }; 180 181 #include <asm/kvm_emulate.h> 182 183 #define KVM_NR_MEM_OBJS 40 184 185 #define KVM_NR_DB_REGS 4 186 187 #define DR6_BD (1 << 13) 188 #define DR6_BS (1 << 14) 189 #define DR6_BT (1 << 15) 190 #define DR6_RTM (1 << 16) 191 #define DR6_FIXED_1 0xfffe0ff0 192 #define DR6_INIT 0xffff0ff0 193 #define DR6_VOLATILE 0x0001e00f 194 195 #define DR7_BP_EN_MASK 0x000000ff 196 #define DR7_GE (1 << 9) 197 #define DR7_GD (1 << 13) 198 #define DR7_FIXED_1 0x00000400 199 #define DR7_VOLATILE 0xffff2bff 200 201 #define PFERR_PRESENT_BIT 0 202 #define PFERR_WRITE_BIT 1 203 #define PFERR_USER_BIT 2 204 #define PFERR_RSVD_BIT 3 205 #define PFERR_FETCH_BIT 4 206 #define PFERR_PK_BIT 5 207 #define PFERR_GUEST_FINAL_BIT 32 208 #define PFERR_GUEST_PAGE_BIT 33 209 210 #define PFERR_PRESENT_MASK (1U << PFERR_PRESENT_BIT) 211 #define PFERR_WRITE_MASK (1U << PFERR_WRITE_BIT) 212 #define PFERR_USER_MASK (1U << PFERR_USER_BIT) 213 #define PFERR_RSVD_MASK (1U << PFERR_RSVD_BIT) 214 #define PFERR_FETCH_MASK (1U << PFERR_FETCH_BIT) 215 #define PFERR_PK_MASK (1U << PFERR_PK_BIT) 216 #define PFERR_GUEST_FINAL_MASK (1ULL << PFERR_GUEST_FINAL_BIT) 217 #define PFERR_GUEST_PAGE_MASK (1ULL << PFERR_GUEST_PAGE_BIT) 218 219 #define PFERR_NESTED_GUEST_PAGE (PFERR_GUEST_PAGE_MASK | \ 220 PFERR_WRITE_MASK | \ 221 PFERR_PRESENT_MASK) 222 223 /* 224 * The mask used to denote special SPTEs, which can be either MMIO SPTEs or 225 * Access Tracking SPTEs. We use bit 62 instead of bit 63 to avoid conflicting 226 * with the SVE bit in EPT PTEs. 227 */ 228 #define SPTE_SPECIAL_MASK (1ULL << 62) 229 230 /* apic attention bits */ 231 #define KVM_APIC_CHECK_VAPIC 0 232 /* 233 * The following bit is set with PV-EOI, unset on EOI. 234 * We detect PV-EOI changes by guest by comparing 235 * this bit with PV-EOI in guest memory. 236 * See the implementation in apic_update_pv_eoi. 237 */ 238 #define KVM_APIC_PV_EOI_PENDING 1 239 240 struct kvm_kernel_irq_routing_entry; 241 242 /* 243 * We don't want allocation failures within the mmu code, so we preallocate 244 * enough memory for a single page fault in a cache. 245 */ 246 struct kvm_mmu_memory_cache { 247 int nobjs; 248 void *objects[KVM_NR_MEM_OBJS]; 249 }; 250 251 /* 252 * the pages used as guest page table on soft mmu are tracked by 253 * kvm_memory_slot.arch.gfn_track which is 16 bits, so the role bits used 254 * by indirect shadow page can not be more than 15 bits. 255 * 256 * Currently, we used 14 bits that are @level, @gpte_is_8_bytes, @quadrant, @access, 257 * @nxe, @cr0_wp, @smep_andnot_wp and @smap_andnot_wp. 258 */ 259 union kvm_mmu_page_role { 260 u32 word; 261 struct { 262 unsigned level:4; 263 unsigned gpte_is_8_bytes:1; 264 unsigned quadrant:2; 265 unsigned direct:1; 266 unsigned access:3; 267 unsigned invalid:1; 268 unsigned nxe:1; 269 unsigned cr0_wp:1; 270 unsigned smep_andnot_wp:1; 271 unsigned smap_andnot_wp:1; 272 unsigned ad_disabled:1; 273 unsigned guest_mode:1; 274 unsigned :6; 275 276 /* 277 * This is left at the top of the word so that 278 * kvm_memslots_for_spte_role can extract it with a 279 * simple shift. While there is room, give it a whole 280 * byte so it is also faster to load it from memory. 281 */ 282 unsigned smm:8; 283 }; 284 }; 285 286 union kvm_mmu_extended_role { 287 /* 288 * This structure complements kvm_mmu_page_role caching everything needed for 289 * MMU configuration. If nothing in both these structures changed, MMU 290 * re-configuration can be skipped. @valid bit is set on first usage so we don't 291 * treat all-zero structure as valid data. 292 */ 293 u32 word; 294 struct { 295 unsigned int valid:1; 296 unsigned int execonly:1; 297 unsigned int cr0_pg:1; 298 unsigned int cr4_pae:1; 299 unsigned int cr4_pse:1; 300 unsigned int cr4_pke:1; 301 unsigned int cr4_smap:1; 302 unsigned int cr4_smep:1; 303 unsigned int cr4_la57:1; 304 unsigned int maxphyaddr:6; 305 }; 306 }; 307 308 union kvm_mmu_role { 309 u64 as_u64; 310 struct { 311 union kvm_mmu_page_role base; 312 union kvm_mmu_extended_role ext; 313 }; 314 }; 315 316 struct kvm_rmap_head { 317 unsigned long val; 318 }; 319 320 struct kvm_mmu_page { 321 struct list_head link; 322 struct hlist_node hash_link; 323 bool unsync; 324 bool mmio_cached; 325 326 /* 327 * The following two entries are used to key the shadow page in the 328 * hash table. 329 */ 330 union kvm_mmu_page_role role; 331 gfn_t gfn; 332 333 u64 *spt; 334 /* hold the gfn of each spte inside spt */ 335 gfn_t *gfns; 336 int root_count; /* Currently serving as active root */ 337 unsigned int unsync_children; 338 struct kvm_rmap_head parent_ptes; /* rmap pointers to parent sptes */ 339 DECLARE_BITMAP(unsync_child_bitmap, 512); 340 341 #ifdef CONFIG_X86_32 342 /* 343 * Used out of the mmu-lock to avoid reading spte values while an 344 * update is in progress; see the comments in __get_spte_lockless(). 345 */ 346 int clear_spte_count; 347 #endif 348 349 /* Number of writes since the last time traversal visited this page. */ 350 atomic_t write_flooding_count; 351 }; 352 353 struct kvm_pio_request { 354 unsigned long linear_rip; 355 unsigned long count; 356 int in; 357 int port; 358 int size; 359 }; 360 361 #define PT64_ROOT_MAX_LEVEL 5 362 363 struct rsvd_bits_validate { 364 u64 rsvd_bits_mask[2][PT64_ROOT_MAX_LEVEL]; 365 u64 bad_mt_xwr; 366 }; 367 368 struct kvm_mmu_root_info { 369 gpa_t cr3; 370 hpa_t hpa; 371 }; 372 373 #define KVM_MMU_ROOT_INFO_INVALID \ 374 ((struct kvm_mmu_root_info) { .cr3 = INVALID_PAGE, .hpa = INVALID_PAGE }) 375 376 #define KVM_MMU_NUM_PREV_ROOTS 3 377 378 /* 379 * x86 supports 4 paging modes (5-level 64-bit, 4-level 64-bit, 3-level 32-bit, 380 * and 2-level 32-bit). The kvm_mmu structure abstracts the details of the 381 * current mmu mode. 382 */ 383 struct kvm_mmu { 384 void (*set_cr3)(struct kvm_vcpu *vcpu, unsigned long root); 385 unsigned long (*get_cr3)(struct kvm_vcpu *vcpu); 386 u64 (*get_pdptr)(struct kvm_vcpu *vcpu, int index); 387 int (*page_fault)(struct kvm_vcpu *vcpu, gva_t gva, u32 err, 388 bool prefault); 389 void (*inject_page_fault)(struct kvm_vcpu *vcpu, 390 struct x86_exception *fault); 391 gpa_t (*gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t gva, u32 access, 392 struct x86_exception *exception); 393 gpa_t (*translate_gpa)(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access, 394 struct x86_exception *exception); 395 int (*sync_page)(struct kvm_vcpu *vcpu, 396 struct kvm_mmu_page *sp); 397 void (*invlpg)(struct kvm_vcpu *vcpu, gva_t gva, hpa_t root_hpa); 398 void (*update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, 399 u64 *spte, const void *pte); 400 hpa_t root_hpa; 401 gpa_t root_cr3; 402 union kvm_mmu_role mmu_role; 403 u8 root_level; 404 u8 shadow_root_level; 405 u8 ept_ad; 406 bool direct_map; 407 struct kvm_mmu_root_info prev_roots[KVM_MMU_NUM_PREV_ROOTS]; 408 409 /* 410 * Bitmap; bit set = permission fault 411 * Byte index: page fault error code [4:1] 412 * Bit index: pte permissions in ACC_* format 413 */ 414 u8 permissions[16]; 415 416 /* 417 * The pkru_mask indicates if protection key checks are needed. It 418 * consists of 16 domains indexed by page fault error code bits [4:1], 419 * with PFEC.RSVD replaced by ACC_USER_MASK from the page tables. 420 * Each domain has 2 bits which are ANDed with AD and WD from PKRU. 421 */ 422 u32 pkru_mask; 423 424 u64 *pae_root; 425 u64 *lm_root; 426 427 /* 428 * check zero bits on shadow page table entries, these 429 * bits include not only hardware reserved bits but also 430 * the bits spte never used. 431 */ 432 struct rsvd_bits_validate shadow_zero_check; 433 434 struct rsvd_bits_validate guest_rsvd_check; 435 436 /* Can have large pages at levels 2..last_nonleaf_level-1. */ 437 u8 last_nonleaf_level; 438 439 bool nx; 440 441 u64 pdptrs[4]; /* pae */ 442 }; 443 444 struct kvm_tlb_range { 445 u64 start_gfn; 446 u64 pages; 447 }; 448 449 enum pmc_type { 450 KVM_PMC_GP = 0, 451 KVM_PMC_FIXED, 452 }; 453 454 struct kvm_pmc { 455 enum pmc_type type; 456 u8 idx; 457 u64 counter; 458 u64 eventsel; 459 struct perf_event *perf_event; 460 struct kvm_vcpu *vcpu; 461 }; 462 463 struct kvm_pmu { 464 unsigned nr_arch_gp_counters; 465 unsigned nr_arch_fixed_counters; 466 unsigned available_event_types; 467 u64 fixed_ctr_ctrl; 468 u64 global_ctrl; 469 u64 global_status; 470 u64 global_ovf_ctrl; 471 u64 counter_bitmask[2]; 472 u64 global_ctrl_mask; 473 u64 global_ovf_ctrl_mask; 474 u64 reserved_bits; 475 u8 version; 476 struct kvm_pmc gp_counters[INTEL_PMC_MAX_GENERIC]; 477 struct kvm_pmc fixed_counters[INTEL_PMC_MAX_FIXED]; 478 struct irq_work irq_work; 479 u64 reprogram_pmi; 480 }; 481 482 struct kvm_pmu_ops; 483 484 enum { 485 KVM_DEBUGREG_BP_ENABLED = 1, 486 KVM_DEBUGREG_WONT_EXIT = 2, 487 KVM_DEBUGREG_RELOAD = 4, 488 }; 489 490 struct kvm_mtrr_range { 491 u64 base; 492 u64 mask; 493 struct list_head node; 494 }; 495 496 struct kvm_mtrr { 497 struct kvm_mtrr_range var_ranges[KVM_NR_VAR_MTRR]; 498 mtrr_type fixed_ranges[KVM_NR_FIXED_MTRR_REGION]; 499 u64 deftype; 500 501 struct list_head head; 502 }; 503 504 /* Hyper-V SynIC timer */ 505 struct kvm_vcpu_hv_stimer { 506 struct hrtimer timer; 507 int index; 508 union hv_stimer_config config; 509 u64 count; 510 u64 exp_time; 511 struct hv_message msg; 512 bool msg_pending; 513 }; 514 515 /* Hyper-V synthetic interrupt controller (SynIC)*/ 516 struct kvm_vcpu_hv_synic { 517 u64 version; 518 u64 control; 519 u64 msg_page; 520 u64 evt_page; 521 atomic64_t sint[HV_SYNIC_SINT_COUNT]; 522 atomic_t sint_to_gsi[HV_SYNIC_SINT_COUNT]; 523 DECLARE_BITMAP(auto_eoi_bitmap, 256); 524 DECLARE_BITMAP(vec_bitmap, 256); 525 bool active; 526 bool dont_zero_synic_pages; 527 }; 528 529 /* Hyper-V per vcpu emulation context */ 530 struct kvm_vcpu_hv { 531 u32 vp_index; 532 u64 hv_vapic; 533 s64 runtime_offset; 534 struct kvm_vcpu_hv_synic synic; 535 struct kvm_hyperv_exit exit; 536 struct kvm_vcpu_hv_stimer stimer[HV_SYNIC_STIMER_COUNT]; 537 DECLARE_BITMAP(stimer_pending_bitmap, HV_SYNIC_STIMER_COUNT); 538 cpumask_t tlb_flush; 539 }; 540 541 struct kvm_vcpu_arch { 542 /* 543 * rip and regs accesses must go through 544 * kvm_{register,rip}_{read,write} functions. 545 */ 546 unsigned long regs[NR_VCPU_REGS]; 547 u32 regs_avail; 548 u32 regs_dirty; 549 550 unsigned long cr0; 551 unsigned long cr0_guest_owned_bits; 552 unsigned long cr2; 553 unsigned long cr3; 554 unsigned long cr4; 555 unsigned long cr4_guest_owned_bits; 556 unsigned long cr8; 557 u32 pkru; 558 u32 hflags; 559 u64 efer; 560 u64 apic_base; 561 struct kvm_lapic *apic; /* kernel irqchip context */ 562 bool apicv_active; 563 bool load_eoi_exitmap_pending; 564 DECLARE_BITMAP(ioapic_handled_vectors, 256); 565 unsigned long apic_attention; 566 int32_t apic_arb_prio; 567 int mp_state; 568 u64 ia32_misc_enable_msr; 569 u64 smbase; 570 u64 smi_count; 571 bool tpr_access_reporting; 572 u64 ia32_xss; 573 u64 microcode_version; 574 u64 arch_capabilities; 575 576 /* 577 * Paging state of the vcpu 578 * 579 * If the vcpu runs in guest mode with two level paging this still saves 580 * the paging mode of the l1 guest. This context is always used to 581 * handle faults. 582 */ 583 struct kvm_mmu *mmu; 584 585 /* Non-nested MMU for L1 */ 586 struct kvm_mmu root_mmu; 587 588 /* L1 MMU when running nested */ 589 struct kvm_mmu guest_mmu; 590 591 /* 592 * Paging state of an L2 guest (used for nested npt) 593 * 594 * This context will save all necessary information to walk page tables 595 * of the an L2 guest. This context is only initialized for page table 596 * walking and not for faulting since we never handle l2 page faults on 597 * the host. 598 */ 599 struct kvm_mmu nested_mmu; 600 601 /* 602 * Pointer to the mmu context currently used for 603 * gva_to_gpa translations. 604 */ 605 struct kvm_mmu *walk_mmu; 606 607 struct kvm_mmu_memory_cache mmu_pte_list_desc_cache; 608 struct kvm_mmu_memory_cache mmu_page_cache; 609 struct kvm_mmu_memory_cache mmu_page_header_cache; 610 611 /* 612 * QEMU userspace and the guest each have their own FPU state. 613 * In vcpu_run, we switch between the user, maintained in the 614 * task_struct struct, and guest FPU contexts. While running a VCPU, 615 * the VCPU thread will have the guest FPU context. 616 * 617 * Note that while the PKRU state lives inside the fpu registers, 618 * it is switched out separately at VMENTER and VMEXIT time. The 619 * "guest_fpu" state here contains the guest FPU context, with the 620 * host PRKU bits. 621 */ 622 struct fpu *guest_fpu; 623 624 u64 xcr0; 625 u64 guest_supported_xcr0; 626 u32 guest_xstate_size; 627 628 struct kvm_pio_request pio; 629 void *pio_data; 630 631 u8 event_exit_inst_len; 632 633 struct kvm_queued_exception { 634 bool pending; 635 bool injected; 636 bool has_error_code; 637 u8 nr; 638 u32 error_code; 639 unsigned long payload; 640 bool has_payload; 641 u8 nested_apf; 642 } exception; 643 644 struct kvm_queued_interrupt { 645 bool injected; 646 bool soft; 647 u8 nr; 648 } interrupt; 649 650 int halt_request; /* real mode on Intel only */ 651 652 int cpuid_nent; 653 struct kvm_cpuid_entry2 cpuid_entries[KVM_MAX_CPUID_ENTRIES]; 654 655 int maxphyaddr; 656 657 /* emulate context */ 658 659 struct x86_emulate_ctxt emulate_ctxt; 660 bool emulate_regs_need_sync_to_vcpu; 661 bool emulate_regs_need_sync_from_vcpu; 662 int (*complete_userspace_io)(struct kvm_vcpu *vcpu); 663 664 gpa_t time; 665 struct pvclock_vcpu_time_info hv_clock; 666 unsigned int hw_tsc_khz; 667 struct gfn_to_hva_cache pv_time; 668 bool pv_time_enabled; 669 /* set guest stopped flag in pvclock flags field */ 670 bool pvclock_set_guest_stopped_request; 671 672 struct { 673 u64 msr_val; 674 u64 last_steal; 675 struct gfn_to_hva_cache stime; 676 struct kvm_steal_time steal; 677 } st; 678 679 u64 tsc_offset; 680 u64 last_guest_tsc; 681 u64 last_host_tsc; 682 u64 tsc_offset_adjustment; 683 u64 this_tsc_nsec; 684 u64 this_tsc_write; 685 u64 this_tsc_generation; 686 bool tsc_catchup; 687 bool tsc_always_catchup; 688 s8 virtual_tsc_shift; 689 u32 virtual_tsc_mult; 690 u32 virtual_tsc_khz; 691 s64 ia32_tsc_adjust_msr; 692 u64 tsc_scaling_ratio; 693 694 atomic_t nmi_queued; /* unprocessed asynchronous NMIs */ 695 unsigned nmi_pending; /* NMI queued after currently running handler */ 696 bool nmi_injected; /* Trying to inject an NMI this entry */ 697 bool smi_pending; /* SMI queued after currently running handler */ 698 699 struct kvm_mtrr mtrr_state; 700 u64 pat; 701 702 unsigned switch_db_regs; 703 unsigned long db[KVM_NR_DB_REGS]; 704 unsigned long dr6; 705 unsigned long dr7; 706 unsigned long eff_db[KVM_NR_DB_REGS]; 707 unsigned long guest_debug_dr7; 708 u64 msr_platform_info; 709 u64 msr_misc_features_enables; 710 711 u64 mcg_cap; 712 u64 mcg_status; 713 u64 mcg_ctl; 714 u64 mcg_ext_ctl; 715 u64 *mce_banks; 716 717 /* Cache MMIO info */ 718 u64 mmio_gva; 719 unsigned access; 720 gfn_t mmio_gfn; 721 u64 mmio_gen; 722 723 struct kvm_pmu pmu; 724 725 /* used for guest single stepping over the given code position */ 726 unsigned long singlestep_rip; 727 728 struct kvm_vcpu_hv hyperv; 729 730 cpumask_var_t wbinvd_dirty_mask; 731 732 unsigned long last_retry_eip; 733 unsigned long last_retry_addr; 734 735 struct { 736 bool halted; 737 gfn_t gfns[roundup_pow_of_two(ASYNC_PF_PER_VCPU)]; 738 struct gfn_to_hva_cache data; 739 u64 msr_val; 740 u32 id; 741 bool send_user_only; 742 u32 host_apf_reason; 743 unsigned long nested_apf_token; 744 bool delivery_as_pf_vmexit; 745 } apf; 746 747 /* OSVW MSRs (AMD only) */ 748 struct { 749 u64 length; 750 u64 status; 751 } osvw; 752 753 struct { 754 u64 msr_val; 755 struct gfn_to_hva_cache data; 756 } pv_eoi; 757 758 /* 759 * Indicate whether the access faults on its page table in guest 760 * which is set when fix page fault and used to detect unhandeable 761 * instruction. 762 */ 763 bool write_fault_to_shadow_pgtable; 764 765 /* set at EPT violation at this point */ 766 unsigned long exit_qualification; 767 768 /* pv related host specific info */ 769 struct { 770 bool pv_unhalted; 771 } pv; 772 773 int pending_ioapic_eoi; 774 int pending_external_vector; 775 776 /* GPA available */ 777 bool gpa_available; 778 gpa_t gpa_val; 779 780 /* be preempted when it's in kernel-mode(cpl=0) */ 781 bool preempted_in_kernel; 782 783 /* Flush the L1 Data cache for L1TF mitigation on VMENTER */ 784 bool l1tf_flush_l1d; 785 786 /* AMD MSRC001_0015 Hardware Configuration */ 787 u64 msr_hwcr; 788 }; 789 790 struct kvm_lpage_info { 791 int disallow_lpage; 792 }; 793 794 struct kvm_arch_memory_slot { 795 struct kvm_rmap_head *rmap[KVM_NR_PAGE_SIZES]; 796 struct kvm_lpage_info *lpage_info[KVM_NR_PAGE_SIZES - 1]; 797 unsigned short *gfn_track[KVM_PAGE_TRACK_MAX]; 798 }; 799 800 /* 801 * We use as the mode the number of bits allocated in the LDR for the 802 * logical processor ID. It happens that these are all powers of two. 803 * This makes it is very easy to detect cases where the APICs are 804 * configured for multiple modes; in that case, we cannot use the map and 805 * hence cannot use kvm_irq_delivery_to_apic_fast either. 806 */ 807 #define KVM_APIC_MODE_XAPIC_CLUSTER 4 808 #define KVM_APIC_MODE_XAPIC_FLAT 8 809 #define KVM_APIC_MODE_X2APIC 16 810 811 struct kvm_apic_map { 812 struct rcu_head rcu; 813 u8 mode; 814 u32 max_apic_id; 815 union { 816 struct kvm_lapic *xapic_flat_map[8]; 817 struct kvm_lapic *xapic_cluster_map[16][4]; 818 }; 819 struct kvm_lapic *phys_map[]; 820 }; 821 822 /* Hyper-V emulation context */ 823 struct kvm_hv { 824 struct mutex hv_lock; 825 u64 hv_guest_os_id; 826 u64 hv_hypercall; 827 u64 hv_tsc_page; 828 829 /* Hyper-v based guest crash (NT kernel bugcheck) parameters */ 830 u64 hv_crash_param[HV_X64_MSR_CRASH_PARAMS]; 831 u64 hv_crash_ctl; 832 833 HV_REFERENCE_TSC_PAGE tsc_ref; 834 835 struct idr conn_to_evt; 836 837 u64 hv_reenlightenment_control; 838 u64 hv_tsc_emulation_control; 839 u64 hv_tsc_emulation_status; 840 841 /* How many vCPUs have VP index != vCPU index */ 842 atomic_t num_mismatched_vp_indexes; 843 }; 844 845 enum kvm_irqchip_mode { 846 KVM_IRQCHIP_NONE, 847 KVM_IRQCHIP_KERNEL, /* created with KVM_CREATE_IRQCHIP */ 848 KVM_IRQCHIP_SPLIT, /* created with KVM_CAP_SPLIT_IRQCHIP */ 849 }; 850 851 struct kvm_arch { 852 unsigned long n_used_mmu_pages; 853 unsigned long n_requested_mmu_pages; 854 unsigned long n_max_mmu_pages; 855 unsigned int indirect_shadow_pages; 856 struct hlist_head mmu_page_hash[KVM_NUM_MMU_PAGES]; 857 /* 858 * Hash table of struct kvm_mmu_page. 859 */ 860 struct list_head active_mmu_pages; 861 struct kvm_page_track_notifier_node mmu_sp_tracker; 862 struct kvm_page_track_notifier_head track_notifier_head; 863 864 struct list_head assigned_dev_head; 865 struct iommu_domain *iommu_domain; 866 bool iommu_noncoherent; 867 #define __KVM_HAVE_ARCH_NONCOHERENT_DMA 868 atomic_t noncoherent_dma_count; 869 #define __KVM_HAVE_ARCH_ASSIGNED_DEVICE 870 atomic_t assigned_device_count; 871 struct kvm_pic *vpic; 872 struct kvm_ioapic *vioapic; 873 struct kvm_pit *vpit; 874 atomic_t vapics_in_nmi_mode; 875 struct mutex apic_map_lock; 876 struct kvm_apic_map *apic_map; 877 878 bool apic_access_page_done; 879 880 gpa_t wall_clock; 881 882 bool mwait_in_guest; 883 bool hlt_in_guest; 884 bool pause_in_guest; 885 886 unsigned long irq_sources_bitmap; 887 s64 kvmclock_offset; 888 raw_spinlock_t tsc_write_lock; 889 u64 last_tsc_nsec; 890 u64 last_tsc_write; 891 u32 last_tsc_khz; 892 u64 cur_tsc_nsec; 893 u64 cur_tsc_write; 894 u64 cur_tsc_offset; 895 u64 cur_tsc_generation; 896 int nr_vcpus_matched_tsc; 897 898 spinlock_t pvclock_gtod_sync_lock; 899 bool use_master_clock; 900 u64 master_kernel_ns; 901 u64 master_cycle_now; 902 struct delayed_work kvmclock_update_work; 903 struct delayed_work kvmclock_sync_work; 904 905 struct kvm_xen_hvm_config xen_hvm_config; 906 907 /* reads protected by irq_srcu, writes by irq_lock */ 908 struct hlist_head mask_notifier_list; 909 910 struct kvm_hv hyperv; 911 912 #ifdef CONFIG_KVM_MMU_AUDIT 913 int audit_point; 914 #endif 915 916 bool backwards_tsc_observed; 917 bool boot_vcpu_runs_old_kvmclock; 918 u32 bsp_vcpu_id; 919 920 u64 disabled_quirks; 921 922 enum kvm_irqchip_mode irqchip_mode; 923 u8 nr_reserved_ioapic_pins; 924 925 bool disabled_lapic_found; 926 927 bool x2apic_format; 928 bool x2apic_broadcast_quirk_disabled; 929 930 bool guest_can_read_msr_platform_info; 931 bool exception_payload_enabled; 932 }; 933 934 struct kvm_vm_stat { 935 ulong mmu_shadow_zapped; 936 ulong mmu_pte_write; 937 ulong mmu_pte_updated; 938 ulong mmu_pde_zapped; 939 ulong mmu_flooded; 940 ulong mmu_recycled; 941 ulong mmu_cache_miss; 942 ulong mmu_unsync; 943 ulong remote_tlb_flush; 944 ulong lpages; 945 ulong max_mmu_page_hash_collisions; 946 }; 947 948 struct kvm_vcpu_stat { 949 u64 pf_fixed; 950 u64 pf_guest; 951 u64 tlb_flush; 952 u64 invlpg; 953 954 u64 exits; 955 u64 io_exits; 956 u64 mmio_exits; 957 u64 signal_exits; 958 u64 irq_window_exits; 959 u64 nmi_window_exits; 960 u64 l1d_flush; 961 u64 halt_exits; 962 u64 halt_successful_poll; 963 u64 halt_attempted_poll; 964 u64 halt_poll_invalid; 965 u64 halt_wakeup; 966 u64 request_irq_exits; 967 u64 irq_exits; 968 u64 host_state_reload; 969 u64 fpu_reload; 970 u64 insn_emulation; 971 u64 insn_emulation_fail; 972 u64 hypercalls; 973 u64 irq_injections; 974 u64 nmi_injections; 975 u64 req_event; 976 }; 977 978 struct x86_instruction_info; 979 980 struct msr_data { 981 bool host_initiated; 982 u32 index; 983 u64 data; 984 }; 985 986 struct kvm_lapic_irq { 987 u32 vector; 988 u16 delivery_mode; 989 u16 dest_mode; 990 bool level; 991 u16 trig_mode; 992 u32 shorthand; 993 u32 dest_id; 994 bool msi_redir_hint; 995 }; 996 997 struct kvm_x86_ops { 998 int (*cpu_has_kvm_support)(void); /* __init */ 999 int (*disabled_by_bios)(void); /* __init */ 1000 int (*hardware_enable)(void); 1001 void (*hardware_disable)(void); 1002 void (*check_processor_compatibility)(void *rtn); 1003 int (*hardware_setup)(void); /* __init */ 1004 void (*hardware_unsetup)(void); /* __exit */ 1005 bool (*cpu_has_accelerated_tpr)(void); 1006 bool (*has_emulated_msr)(int index); 1007 void (*cpuid_update)(struct kvm_vcpu *vcpu); 1008 1009 struct kvm *(*vm_alloc)(void); 1010 void (*vm_free)(struct kvm *); 1011 int (*vm_init)(struct kvm *kvm); 1012 void (*vm_destroy)(struct kvm *kvm); 1013 1014 /* Create, but do not attach this VCPU */ 1015 struct kvm_vcpu *(*vcpu_create)(struct kvm *kvm, unsigned id); 1016 void (*vcpu_free)(struct kvm_vcpu *vcpu); 1017 void (*vcpu_reset)(struct kvm_vcpu *vcpu, bool init_event); 1018 1019 void (*prepare_guest_switch)(struct kvm_vcpu *vcpu); 1020 void (*vcpu_load)(struct kvm_vcpu *vcpu, int cpu); 1021 void (*vcpu_put)(struct kvm_vcpu *vcpu); 1022 1023 void (*update_bp_intercept)(struct kvm_vcpu *vcpu); 1024 int (*get_msr)(struct kvm_vcpu *vcpu, struct msr_data *msr); 1025 int (*set_msr)(struct kvm_vcpu *vcpu, struct msr_data *msr); 1026 u64 (*get_segment_base)(struct kvm_vcpu *vcpu, int seg); 1027 void (*get_segment)(struct kvm_vcpu *vcpu, 1028 struct kvm_segment *var, int seg); 1029 int (*get_cpl)(struct kvm_vcpu *vcpu); 1030 void (*set_segment)(struct kvm_vcpu *vcpu, 1031 struct kvm_segment *var, int seg); 1032 void (*get_cs_db_l_bits)(struct kvm_vcpu *vcpu, int *db, int *l); 1033 void (*decache_cr0_guest_bits)(struct kvm_vcpu *vcpu); 1034 void (*decache_cr3)(struct kvm_vcpu *vcpu); 1035 void (*decache_cr4_guest_bits)(struct kvm_vcpu *vcpu); 1036 void (*set_cr0)(struct kvm_vcpu *vcpu, unsigned long cr0); 1037 void (*set_cr3)(struct kvm_vcpu *vcpu, unsigned long cr3); 1038 int (*set_cr4)(struct kvm_vcpu *vcpu, unsigned long cr4); 1039 void (*set_efer)(struct kvm_vcpu *vcpu, u64 efer); 1040 void (*get_idt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt); 1041 void (*set_idt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt); 1042 void (*get_gdt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt); 1043 void (*set_gdt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt); 1044 u64 (*get_dr6)(struct kvm_vcpu *vcpu); 1045 void (*set_dr6)(struct kvm_vcpu *vcpu, unsigned long value); 1046 void (*sync_dirty_debug_regs)(struct kvm_vcpu *vcpu); 1047 void (*set_dr7)(struct kvm_vcpu *vcpu, unsigned long value); 1048 void (*cache_reg)(struct kvm_vcpu *vcpu, enum kvm_reg reg); 1049 unsigned long (*get_rflags)(struct kvm_vcpu *vcpu); 1050 void (*set_rflags)(struct kvm_vcpu *vcpu, unsigned long rflags); 1051 1052 void (*tlb_flush)(struct kvm_vcpu *vcpu, bool invalidate_gpa); 1053 int (*tlb_remote_flush)(struct kvm *kvm); 1054 int (*tlb_remote_flush_with_range)(struct kvm *kvm, 1055 struct kvm_tlb_range *range); 1056 1057 /* 1058 * Flush any TLB entries associated with the given GVA. 1059 * Does not need to flush GPA->HPA mappings. 1060 * Can potentially get non-canonical addresses through INVLPGs, which 1061 * the implementation may choose to ignore if appropriate. 1062 */ 1063 void (*tlb_flush_gva)(struct kvm_vcpu *vcpu, gva_t addr); 1064 1065 void (*run)(struct kvm_vcpu *vcpu); 1066 int (*handle_exit)(struct kvm_vcpu *vcpu); 1067 void (*skip_emulated_instruction)(struct kvm_vcpu *vcpu); 1068 void (*set_interrupt_shadow)(struct kvm_vcpu *vcpu, int mask); 1069 u32 (*get_interrupt_shadow)(struct kvm_vcpu *vcpu); 1070 void (*patch_hypercall)(struct kvm_vcpu *vcpu, 1071 unsigned char *hypercall_addr); 1072 void (*set_irq)(struct kvm_vcpu *vcpu); 1073 void (*set_nmi)(struct kvm_vcpu *vcpu); 1074 void (*queue_exception)(struct kvm_vcpu *vcpu); 1075 void (*cancel_injection)(struct kvm_vcpu *vcpu); 1076 int (*interrupt_allowed)(struct kvm_vcpu *vcpu); 1077 int (*nmi_allowed)(struct kvm_vcpu *vcpu); 1078 bool (*get_nmi_mask)(struct kvm_vcpu *vcpu); 1079 void (*set_nmi_mask)(struct kvm_vcpu *vcpu, bool masked); 1080 void (*enable_nmi_window)(struct kvm_vcpu *vcpu); 1081 void (*enable_irq_window)(struct kvm_vcpu *vcpu); 1082 void (*update_cr8_intercept)(struct kvm_vcpu *vcpu, int tpr, int irr); 1083 bool (*get_enable_apicv)(struct kvm_vcpu *vcpu); 1084 void (*refresh_apicv_exec_ctrl)(struct kvm_vcpu *vcpu); 1085 void (*hwapic_irr_update)(struct kvm_vcpu *vcpu, int max_irr); 1086 void (*hwapic_isr_update)(struct kvm_vcpu *vcpu, int isr); 1087 bool (*guest_apic_has_interrupt)(struct kvm_vcpu *vcpu); 1088 void (*load_eoi_exitmap)(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap); 1089 void (*set_virtual_apic_mode)(struct kvm_vcpu *vcpu); 1090 void (*set_apic_access_page_addr)(struct kvm_vcpu *vcpu, hpa_t hpa); 1091 void (*deliver_posted_interrupt)(struct kvm_vcpu *vcpu, int vector); 1092 int (*sync_pir_to_irr)(struct kvm_vcpu *vcpu); 1093 int (*set_tss_addr)(struct kvm *kvm, unsigned int addr); 1094 int (*set_identity_map_addr)(struct kvm *kvm, u64 ident_addr); 1095 int (*get_tdp_level)(struct kvm_vcpu *vcpu); 1096 u64 (*get_mt_mask)(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio); 1097 int (*get_lpage_level)(void); 1098 bool (*rdtscp_supported)(void); 1099 bool (*invpcid_supported)(void); 1100 1101 void (*set_tdp_cr3)(struct kvm_vcpu *vcpu, unsigned long cr3); 1102 1103 void (*set_supported_cpuid)(u32 func, struct kvm_cpuid_entry2 *entry); 1104 1105 bool (*has_wbinvd_exit)(void); 1106 1107 u64 (*read_l1_tsc_offset)(struct kvm_vcpu *vcpu); 1108 /* Returns actual tsc_offset set in active VMCS */ 1109 u64 (*write_l1_tsc_offset)(struct kvm_vcpu *vcpu, u64 offset); 1110 1111 void (*get_exit_info)(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2); 1112 1113 int (*check_intercept)(struct kvm_vcpu *vcpu, 1114 struct x86_instruction_info *info, 1115 enum x86_intercept_stage stage); 1116 void (*handle_external_intr)(struct kvm_vcpu *vcpu); 1117 bool (*mpx_supported)(void); 1118 bool (*xsaves_supported)(void); 1119 bool (*umip_emulated)(void); 1120 bool (*pt_supported)(void); 1121 1122 int (*check_nested_events)(struct kvm_vcpu *vcpu, bool external_intr); 1123 void (*request_immediate_exit)(struct kvm_vcpu *vcpu); 1124 1125 void (*sched_in)(struct kvm_vcpu *kvm, int cpu); 1126 1127 /* 1128 * Arch-specific dirty logging hooks. These hooks are only supposed to 1129 * be valid if the specific arch has hardware-accelerated dirty logging 1130 * mechanism. Currently only for PML on VMX. 1131 * 1132 * - slot_enable_log_dirty: 1133 * called when enabling log dirty mode for the slot. 1134 * - slot_disable_log_dirty: 1135 * called when disabling log dirty mode for the slot. 1136 * also called when slot is created with log dirty disabled. 1137 * - flush_log_dirty: 1138 * called before reporting dirty_bitmap to userspace. 1139 * - enable_log_dirty_pt_masked: 1140 * called when reenabling log dirty for the GFNs in the mask after 1141 * corresponding bits are cleared in slot->dirty_bitmap. 1142 */ 1143 void (*slot_enable_log_dirty)(struct kvm *kvm, 1144 struct kvm_memory_slot *slot); 1145 void (*slot_disable_log_dirty)(struct kvm *kvm, 1146 struct kvm_memory_slot *slot); 1147 void (*flush_log_dirty)(struct kvm *kvm); 1148 void (*enable_log_dirty_pt_masked)(struct kvm *kvm, 1149 struct kvm_memory_slot *slot, 1150 gfn_t offset, unsigned long mask); 1151 int (*write_log_dirty)(struct kvm_vcpu *vcpu); 1152 1153 /* pmu operations of sub-arch */ 1154 const struct kvm_pmu_ops *pmu_ops; 1155 1156 /* 1157 * Architecture specific hooks for vCPU blocking due to 1158 * HLT instruction. 1159 * Returns for .pre_block(): 1160 * - 0 means continue to block the vCPU. 1161 * - 1 means we cannot block the vCPU since some event 1162 * happens during this period, such as, 'ON' bit in 1163 * posted-interrupts descriptor is set. 1164 */ 1165 int (*pre_block)(struct kvm_vcpu *vcpu); 1166 void (*post_block)(struct kvm_vcpu *vcpu); 1167 1168 void (*vcpu_blocking)(struct kvm_vcpu *vcpu); 1169 void (*vcpu_unblocking)(struct kvm_vcpu *vcpu); 1170 1171 int (*update_pi_irte)(struct kvm *kvm, unsigned int host_irq, 1172 uint32_t guest_irq, bool set); 1173 void (*apicv_post_state_restore)(struct kvm_vcpu *vcpu); 1174 1175 int (*set_hv_timer)(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc, 1176 bool *expired); 1177 void (*cancel_hv_timer)(struct kvm_vcpu *vcpu); 1178 1179 void (*setup_mce)(struct kvm_vcpu *vcpu); 1180 1181 int (*get_nested_state)(struct kvm_vcpu *vcpu, 1182 struct kvm_nested_state __user *user_kvm_nested_state, 1183 unsigned user_data_size); 1184 int (*set_nested_state)(struct kvm_vcpu *vcpu, 1185 struct kvm_nested_state __user *user_kvm_nested_state, 1186 struct kvm_nested_state *kvm_state); 1187 void (*get_vmcs12_pages)(struct kvm_vcpu *vcpu); 1188 1189 int (*smi_allowed)(struct kvm_vcpu *vcpu); 1190 int (*pre_enter_smm)(struct kvm_vcpu *vcpu, char *smstate); 1191 int (*pre_leave_smm)(struct kvm_vcpu *vcpu, const char *smstate); 1192 int (*enable_smi_window)(struct kvm_vcpu *vcpu); 1193 1194 int (*mem_enc_op)(struct kvm *kvm, void __user *argp); 1195 int (*mem_enc_reg_region)(struct kvm *kvm, struct kvm_enc_region *argp); 1196 int (*mem_enc_unreg_region)(struct kvm *kvm, struct kvm_enc_region *argp); 1197 1198 int (*get_msr_feature)(struct kvm_msr_entry *entry); 1199 1200 int (*nested_enable_evmcs)(struct kvm_vcpu *vcpu, 1201 uint16_t *vmcs_version); 1202 uint16_t (*nested_get_evmcs_version)(struct kvm_vcpu *vcpu); 1203 1204 bool (*need_emulation_on_page_fault)(struct kvm_vcpu *vcpu); 1205 }; 1206 1207 struct kvm_arch_async_pf { 1208 u32 token; 1209 gfn_t gfn; 1210 unsigned long cr3; 1211 bool direct_map; 1212 }; 1213 1214 extern struct kvm_x86_ops *kvm_x86_ops; 1215 extern struct kmem_cache *x86_fpu_cache; 1216 1217 #define __KVM_HAVE_ARCH_VM_ALLOC 1218 static inline struct kvm *kvm_arch_alloc_vm(void) 1219 { 1220 return kvm_x86_ops->vm_alloc(); 1221 } 1222 1223 static inline void kvm_arch_free_vm(struct kvm *kvm) 1224 { 1225 return kvm_x86_ops->vm_free(kvm); 1226 } 1227 1228 #define __KVM_HAVE_ARCH_FLUSH_REMOTE_TLB 1229 static inline int kvm_arch_flush_remote_tlb(struct kvm *kvm) 1230 { 1231 if (kvm_x86_ops->tlb_remote_flush && 1232 !kvm_x86_ops->tlb_remote_flush(kvm)) 1233 return 0; 1234 else 1235 return -ENOTSUPP; 1236 } 1237 1238 int kvm_mmu_module_init(void); 1239 void kvm_mmu_module_exit(void); 1240 1241 void kvm_mmu_destroy(struct kvm_vcpu *vcpu); 1242 int kvm_mmu_create(struct kvm_vcpu *vcpu); 1243 void kvm_mmu_init_vm(struct kvm *kvm); 1244 void kvm_mmu_uninit_vm(struct kvm *kvm); 1245 void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask, 1246 u64 dirty_mask, u64 nx_mask, u64 x_mask, u64 p_mask, 1247 u64 acc_track_mask, u64 me_mask); 1248 1249 void kvm_mmu_reset_context(struct kvm_vcpu *vcpu); 1250 void kvm_mmu_slot_remove_write_access(struct kvm *kvm, 1251 struct kvm_memory_slot *memslot); 1252 void kvm_mmu_zap_collapsible_sptes(struct kvm *kvm, 1253 const struct kvm_memory_slot *memslot); 1254 void kvm_mmu_slot_leaf_clear_dirty(struct kvm *kvm, 1255 struct kvm_memory_slot *memslot); 1256 void kvm_mmu_slot_largepage_remove_write_access(struct kvm *kvm, 1257 struct kvm_memory_slot *memslot); 1258 void kvm_mmu_slot_set_dirty(struct kvm *kvm, 1259 struct kvm_memory_slot *memslot); 1260 void kvm_mmu_clear_dirty_pt_masked(struct kvm *kvm, 1261 struct kvm_memory_slot *slot, 1262 gfn_t gfn_offset, unsigned long mask); 1263 void kvm_mmu_zap_all(struct kvm *kvm); 1264 void kvm_mmu_invalidate_mmio_sptes(struct kvm *kvm, u64 gen); 1265 unsigned long kvm_mmu_calculate_default_mmu_pages(struct kvm *kvm); 1266 void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned long kvm_nr_mmu_pages); 1267 1268 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3); 1269 bool pdptrs_changed(struct kvm_vcpu *vcpu); 1270 1271 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa, 1272 const void *val, int bytes); 1273 1274 struct kvm_irq_mask_notifier { 1275 void (*func)(struct kvm_irq_mask_notifier *kimn, bool masked); 1276 int irq; 1277 struct hlist_node link; 1278 }; 1279 1280 void kvm_register_irq_mask_notifier(struct kvm *kvm, int irq, 1281 struct kvm_irq_mask_notifier *kimn); 1282 void kvm_unregister_irq_mask_notifier(struct kvm *kvm, int irq, 1283 struct kvm_irq_mask_notifier *kimn); 1284 void kvm_fire_mask_notifiers(struct kvm *kvm, unsigned irqchip, unsigned pin, 1285 bool mask); 1286 1287 extern bool tdp_enabled; 1288 1289 u64 vcpu_tsc_khz(struct kvm_vcpu *vcpu); 1290 1291 /* control of guest tsc rate supported? */ 1292 extern bool kvm_has_tsc_control; 1293 /* maximum supported tsc_khz for guests */ 1294 extern u32 kvm_max_guest_tsc_khz; 1295 /* number of bits of the fractional part of the TSC scaling ratio */ 1296 extern u8 kvm_tsc_scaling_ratio_frac_bits; 1297 /* maximum allowed value of TSC scaling ratio */ 1298 extern u64 kvm_max_tsc_scaling_ratio; 1299 /* 1ull << kvm_tsc_scaling_ratio_frac_bits */ 1300 extern u64 kvm_default_tsc_scaling_ratio; 1301 1302 extern u64 kvm_mce_cap_supported; 1303 1304 enum emulation_result { 1305 EMULATE_DONE, /* no further processing */ 1306 EMULATE_USER_EXIT, /* kvm_run ready for userspace exit */ 1307 EMULATE_FAIL, /* can't emulate this instruction */ 1308 }; 1309 1310 #define EMULTYPE_NO_DECODE (1 << 0) 1311 #define EMULTYPE_TRAP_UD (1 << 1) 1312 #define EMULTYPE_SKIP (1 << 2) 1313 #define EMULTYPE_ALLOW_RETRY (1 << 3) 1314 #define EMULTYPE_NO_UD_ON_FAIL (1 << 4) 1315 #define EMULTYPE_VMWARE (1 << 5) 1316 int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type); 1317 int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu, 1318 void *insn, int insn_len); 1319 1320 void kvm_enable_efer_bits(u64); 1321 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer); 1322 int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr); 1323 int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr); 1324 1325 struct x86_emulate_ctxt; 1326 1327 int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in); 1328 int kvm_emulate_cpuid(struct kvm_vcpu *vcpu); 1329 int kvm_emulate_halt(struct kvm_vcpu *vcpu); 1330 int kvm_vcpu_halt(struct kvm_vcpu *vcpu); 1331 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu); 1332 1333 void kvm_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg); 1334 int kvm_load_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector, int seg); 1335 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector); 1336 1337 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index, 1338 int reason, bool has_error_code, u32 error_code); 1339 1340 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0); 1341 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3); 1342 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4); 1343 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8); 1344 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val); 1345 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val); 1346 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu); 1347 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw); 1348 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l); 1349 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr); 1350 1351 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr); 1352 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr); 1353 1354 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu); 1355 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags); 1356 bool kvm_rdpmc(struct kvm_vcpu *vcpu); 1357 1358 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr); 1359 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code); 1360 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr); 1361 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code); 1362 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault); 1363 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, 1364 gfn_t gfn, void *data, int offset, int len, 1365 u32 access); 1366 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl); 1367 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr); 1368 1369 static inline int __kvm_irq_line_state(unsigned long *irq_state, 1370 int irq_source_id, int level) 1371 { 1372 /* Logical OR for level trig interrupt */ 1373 if (level) 1374 __set_bit(irq_source_id, irq_state); 1375 else 1376 __clear_bit(irq_source_id, irq_state); 1377 1378 return !!(*irq_state); 1379 } 1380 1381 #define KVM_MMU_ROOT_CURRENT BIT(0) 1382 #define KVM_MMU_ROOT_PREVIOUS(i) BIT(1+i) 1383 #define KVM_MMU_ROOTS_ALL (~0UL) 1384 1385 int kvm_pic_set_irq(struct kvm_pic *pic, int irq, int irq_source_id, int level); 1386 void kvm_pic_clear_all(struct kvm_pic *pic, int irq_source_id); 1387 1388 void kvm_inject_nmi(struct kvm_vcpu *vcpu); 1389 1390 int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn); 1391 int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva); 1392 void __kvm_mmu_free_some_pages(struct kvm_vcpu *vcpu); 1393 int kvm_mmu_load(struct kvm_vcpu *vcpu); 1394 void kvm_mmu_unload(struct kvm_vcpu *vcpu); 1395 void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu); 1396 void kvm_mmu_free_roots(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, 1397 ulong roots_to_free); 1398 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access, 1399 struct x86_exception *exception); 1400 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, 1401 struct x86_exception *exception); 1402 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, 1403 struct x86_exception *exception); 1404 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, 1405 struct x86_exception *exception); 1406 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, 1407 struct x86_exception *exception); 1408 1409 void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu); 1410 1411 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu); 1412 1413 int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t gva, u64 error_code, 1414 void *insn, int insn_len); 1415 void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva); 1416 void kvm_mmu_invpcid_gva(struct kvm_vcpu *vcpu, gva_t gva, unsigned long pcid); 1417 void kvm_mmu_new_cr3(struct kvm_vcpu *vcpu, gpa_t new_cr3, bool skip_tlb_flush); 1418 1419 void kvm_enable_tdp(void); 1420 void kvm_disable_tdp(void); 1421 1422 static inline gpa_t translate_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access, 1423 struct x86_exception *exception) 1424 { 1425 return gpa; 1426 } 1427 1428 static inline struct kvm_mmu_page *page_header(hpa_t shadow_page) 1429 { 1430 struct page *page = pfn_to_page(shadow_page >> PAGE_SHIFT); 1431 1432 return (struct kvm_mmu_page *)page_private(page); 1433 } 1434 1435 static inline u16 kvm_read_ldt(void) 1436 { 1437 u16 ldt; 1438 asm("sldt %0" : "=g"(ldt)); 1439 return ldt; 1440 } 1441 1442 static inline void kvm_load_ldt(u16 sel) 1443 { 1444 asm("lldt %0" : : "rm"(sel)); 1445 } 1446 1447 #ifdef CONFIG_X86_64 1448 static inline unsigned long read_msr(unsigned long msr) 1449 { 1450 u64 value; 1451 1452 rdmsrl(msr, value); 1453 return value; 1454 } 1455 #endif 1456 1457 static inline u32 get_rdx_init_val(void) 1458 { 1459 return 0x600; /* P6 family */ 1460 } 1461 1462 static inline void kvm_inject_gp(struct kvm_vcpu *vcpu, u32 error_code) 1463 { 1464 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code); 1465 } 1466 1467 #define TSS_IOPB_BASE_OFFSET 0x66 1468 #define TSS_BASE_SIZE 0x68 1469 #define TSS_IOPB_SIZE (65536 / 8) 1470 #define TSS_REDIRECTION_SIZE (256 / 8) 1471 #define RMODE_TSS_SIZE \ 1472 (TSS_BASE_SIZE + TSS_REDIRECTION_SIZE + TSS_IOPB_SIZE + 1) 1473 1474 enum { 1475 TASK_SWITCH_CALL = 0, 1476 TASK_SWITCH_IRET = 1, 1477 TASK_SWITCH_JMP = 2, 1478 TASK_SWITCH_GATE = 3, 1479 }; 1480 1481 #define HF_GIF_MASK (1 << 0) 1482 #define HF_HIF_MASK (1 << 1) 1483 #define HF_VINTR_MASK (1 << 2) 1484 #define HF_NMI_MASK (1 << 3) 1485 #define HF_IRET_MASK (1 << 4) 1486 #define HF_GUEST_MASK (1 << 5) /* VCPU is in guest-mode */ 1487 #define HF_SMM_MASK (1 << 6) 1488 #define HF_SMM_INSIDE_NMI_MASK (1 << 7) 1489 1490 #define __KVM_VCPU_MULTIPLE_ADDRESS_SPACE 1491 #define KVM_ADDRESS_SPACE_NUM 2 1492 1493 #define kvm_arch_vcpu_memslots_id(vcpu) ((vcpu)->arch.hflags & HF_SMM_MASK ? 1 : 0) 1494 #define kvm_memslots_for_spte_role(kvm, role) __kvm_memslots(kvm, (role).smm) 1495 1496 /* 1497 * Hardware virtualization extension instructions may fault if a 1498 * reboot turns off virtualization while processes are running. 1499 * Trap the fault and ignore the instruction if that happens. 1500 */ 1501 asmlinkage void kvm_spurious_fault(void); 1502 1503 #define ____kvm_handle_fault_on_reboot(insn, cleanup_insn) \ 1504 "666: " insn "\n\t" \ 1505 "668: \n\t" \ 1506 ".pushsection .fixup, \"ax\" \n" \ 1507 "667: \n\t" \ 1508 cleanup_insn "\n\t" \ 1509 "cmpb $0, kvm_rebooting \n\t" \ 1510 "jne 668b \n\t" \ 1511 __ASM_SIZE(push) " $666b \n\t" \ 1512 "jmp kvm_spurious_fault \n\t" \ 1513 ".popsection \n\t" \ 1514 _ASM_EXTABLE(666b, 667b) 1515 1516 #define __kvm_handle_fault_on_reboot(insn) \ 1517 ____kvm_handle_fault_on_reboot(insn, "") 1518 1519 #define KVM_ARCH_WANT_MMU_NOTIFIER 1520 int kvm_unmap_hva_range(struct kvm *kvm, unsigned long start, unsigned long end); 1521 int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end); 1522 int kvm_test_age_hva(struct kvm *kvm, unsigned long hva); 1523 int kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte); 1524 int kvm_cpu_has_injectable_intr(struct kvm_vcpu *v); 1525 int kvm_cpu_has_interrupt(struct kvm_vcpu *vcpu); 1526 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu); 1527 int kvm_cpu_get_interrupt(struct kvm_vcpu *v); 1528 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event); 1529 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu); 1530 1531 int kvm_pv_send_ipi(struct kvm *kvm, unsigned long ipi_bitmap_low, 1532 unsigned long ipi_bitmap_high, u32 min, 1533 unsigned long icr, int op_64_bit); 1534 1535 u64 kvm_get_arch_capabilities(void); 1536 void kvm_define_shared_msr(unsigned index, u32 msr); 1537 int kvm_set_shared_msr(unsigned index, u64 val, u64 mask); 1538 1539 u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc); 1540 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc); 1541 1542 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu); 1543 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip); 1544 1545 void kvm_make_mclock_inprogress_request(struct kvm *kvm); 1546 void kvm_make_scan_ioapic_request(struct kvm *kvm); 1547 1548 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu, 1549 struct kvm_async_pf *work); 1550 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu, 1551 struct kvm_async_pf *work); 1552 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, 1553 struct kvm_async_pf *work); 1554 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu); 1555 extern bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn); 1556 1557 int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu); 1558 int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err); 1559 void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu); 1560 1561 int kvm_is_in_guest(void); 1562 1563 int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size); 1564 int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size); 1565 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu); 1566 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu); 1567 1568 bool kvm_intr_is_single_vcpu(struct kvm *kvm, struct kvm_lapic_irq *irq, 1569 struct kvm_vcpu **dest_vcpu); 1570 1571 void kvm_set_msi_irq(struct kvm *kvm, struct kvm_kernel_irq_routing_entry *e, 1572 struct kvm_lapic_irq *irq); 1573 1574 static inline void kvm_arch_vcpu_blocking(struct kvm_vcpu *vcpu) 1575 { 1576 if (kvm_x86_ops->vcpu_blocking) 1577 kvm_x86_ops->vcpu_blocking(vcpu); 1578 } 1579 1580 static inline void kvm_arch_vcpu_unblocking(struct kvm_vcpu *vcpu) 1581 { 1582 if (kvm_x86_ops->vcpu_unblocking) 1583 kvm_x86_ops->vcpu_unblocking(vcpu); 1584 } 1585 1586 static inline void kvm_arch_vcpu_block_finish(struct kvm_vcpu *vcpu) {} 1587 1588 static inline int kvm_cpu_get_apicid(int mps_cpu) 1589 { 1590 #ifdef CONFIG_X86_LOCAL_APIC 1591 return default_cpu_present_to_apicid(mps_cpu); 1592 #else 1593 WARN_ON_ONCE(1); 1594 return BAD_APICID; 1595 #endif 1596 } 1597 1598 #define put_smstate(type, buf, offset, val) \ 1599 *(type *)((buf) + (offset) - 0x7e00) = val 1600 1601 #define GET_SMSTATE(type, buf, offset) \ 1602 (*(type *)((buf) + (offset) - 0x7e00)) 1603 1604 #endif /* _ASM_X86_KVM_HOST_H */ 1605