1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Kernel-based Virtual Machine driver for Linux 4 * 5 * This header defines architecture specific interfaces, x86 version 6 */ 7 8 #ifndef _ASM_X86_KVM_HOST_H 9 #define _ASM_X86_KVM_HOST_H 10 11 #include <linux/types.h> 12 #include <linux/mm.h> 13 #include <linux/mmu_notifier.h> 14 #include <linux/tracepoint.h> 15 #include <linux/cpumask.h> 16 #include <linux/irq_work.h> 17 #include <linux/irq.h> 18 19 #include <linux/kvm.h> 20 #include <linux/kvm_para.h> 21 #include <linux/kvm_types.h> 22 #include <linux/perf_event.h> 23 #include <linux/pvclock_gtod.h> 24 #include <linux/clocksource.h> 25 #include <linux/irqbypass.h> 26 #include <linux/hyperv.h> 27 28 #include <asm/apic.h> 29 #include <asm/pvclock-abi.h> 30 #include <asm/desc.h> 31 #include <asm/mtrr.h> 32 #include <asm/msr-index.h> 33 #include <asm/asm.h> 34 #include <asm/kvm_page_track.h> 35 #include <asm/kvm_vcpu_regs.h> 36 #include <asm/hyperv-tlfs.h> 37 38 #define __KVM_HAVE_ARCH_VCPU_DEBUGFS 39 40 #define KVM_MAX_VCPUS 288 41 #define KVM_SOFT_MAX_VCPUS 240 42 #define KVM_MAX_VCPU_ID 1023 43 #define KVM_USER_MEM_SLOTS 509 44 /* memory slots that are not exposed to userspace */ 45 #define KVM_PRIVATE_MEM_SLOTS 3 46 #define KVM_MEM_SLOTS_NUM (KVM_USER_MEM_SLOTS + KVM_PRIVATE_MEM_SLOTS) 47 48 #define KVM_HALT_POLL_NS_DEFAULT 200000 49 50 #define KVM_IRQCHIP_NUM_PINS KVM_IOAPIC_NUM_PINS 51 52 /* x86-specific vcpu->requests bit members */ 53 #define KVM_REQ_MIGRATE_TIMER KVM_ARCH_REQ(0) 54 #define KVM_REQ_REPORT_TPR_ACCESS KVM_ARCH_REQ(1) 55 #define KVM_REQ_TRIPLE_FAULT KVM_ARCH_REQ(2) 56 #define KVM_REQ_MMU_SYNC KVM_ARCH_REQ(3) 57 #define KVM_REQ_CLOCK_UPDATE KVM_ARCH_REQ(4) 58 #define KVM_REQ_LOAD_CR3 KVM_ARCH_REQ(5) 59 #define KVM_REQ_EVENT KVM_ARCH_REQ(6) 60 #define KVM_REQ_APF_HALT KVM_ARCH_REQ(7) 61 #define KVM_REQ_STEAL_UPDATE KVM_ARCH_REQ(8) 62 #define KVM_REQ_NMI KVM_ARCH_REQ(9) 63 #define KVM_REQ_PMU KVM_ARCH_REQ(10) 64 #define KVM_REQ_PMI KVM_ARCH_REQ(11) 65 #define KVM_REQ_SMI KVM_ARCH_REQ(12) 66 #define KVM_REQ_MASTERCLOCK_UPDATE KVM_ARCH_REQ(13) 67 #define KVM_REQ_MCLOCK_INPROGRESS \ 68 KVM_ARCH_REQ_FLAGS(14, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP) 69 #define KVM_REQ_SCAN_IOAPIC \ 70 KVM_ARCH_REQ_FLAGS(15, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP) 71 #define KVM_REQ_GLOBAL_CLOCK_UPDATE KVM_ARCH_REQ(16) 72 #define KVM_REQ_APIC_PAGE_RELOAD \ 73 KVM_ARCH_REQ_FLAGS(17, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP) 74 #define KVM_REQ_HV_CRASH KVM_ARCH_REQ(18) 75 #define KVM_REQ_IOAPIC_EOI_EXIT KVM_ARCH_REQ(19) 76 #define KVM_REQ_HV_RESET KVM_ARCH_REQ(20) 77 #define KVM_REQ_HV_EXIT KVM_ARCH_REQ(21) 78 #define KVM_REQ_HV_STIMER KVM_ARCH_REQ(22) 79 #define KVM_REQ_LOAD_EOI_EXITMAP KVM_ARCH_REQ(23) 80 #define KVM_REQ_GET_VMCS12_PAGES KVM_ARCH_REQ(24) 81 82 #define CR0_RESERVED_BITS \ 83 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \ 84 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \ 85 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG)) 86 87 #define CR4_RESERVED_BITS \ 88 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\ 89 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \ 90 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR | X86_CR4_PCIDE \ 91 | X86_CR4_OSXSAVE | X86_CR4_SMEP | X86_CR4_FSGSBASE \ 92 | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_VMXE \ 93 | X86_CR4_SMAP | X86_CR4_PKE | X86_CR4_UMIP)) 94 95 #define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR) 96 97 98 99 #define INVALID_PAGE (~(hpa_t)0) 100 #define VALID_PAGE(x) ((x) != INVALID_PAGE) 101 102 #define UNMAPPED_GVA (~(gpa_t)0) 103 104 /* KVM Hugepage definitions for x86 */ 105 enum { 106 PT_PAGE_TABLE_LEVEL = 1, 107 PT_DIRECTORY_LEVEL = 2, 108 PT_PDPE_LEVEL = 3, 109 /* set max level to the biggest one */ 110 PT_MAX_HUGEPAGE_LEVEL = PT_PDPE_LEVEL, 111 }; 112 #define KVM_NR_PAGE_SIZES (PT_MAX_HUGEPAGE_LEVEL - \ 113 PT_PAGE_TABLE_LEVEL + 1) 114 #define KVM_HPAGE_GFN_SHIFT(x) (((x) - 1) * 9) 115 #define KVM_HPAGE_SHIFT(x) (PAGE_SHIFT + KVM_HPAGE_GFN_SHIFT(x)) 116 #define KVM_HPAGE_SIZE(x) (1UL << KVM_HPAGE_SHIFT(x)) 117 #define KVM_HPAGE_MASK(x) (~(KVM_HPAGE_SIZE(x) - 1)) 118 #define KVM_PAGES_PER_HPAGE(x) (KVM_HPAGE_SIZE(x) / PAGE_SIZE) 119 120 static inline gfn_t gfn_to_index(gfn_t gfn, gfn_t base_gfn, int level) 121 { 122 /* KVM_HPAGE_GFN_SHIFT(PT_PAGE_TABLE_LEVEL) must be 0. */ 123 return (gfn >> KVM_HPAGE_GFN_SHIFT(level)) - 124 (base_gfn >> KVM_HPAGE_GFN_SHIFT(level)); 125 } 126 127 #define KVM_PERMILLE_MMU_PAGES 20 128 #define KVM_MIN_ALLOC_MMU_PAGES 64UL 129 #define KVM_MMU_HASH_SHIFT 12 130 #define KVM_NUM_MMU_PAGES (1 << KVM_MMU_HASH_SHIFT) 131 #define KVM_MIN_FREE_MMU_PAGES 5 132 #define KVM_REFILL_PAGES 25 133 #define KVM_MAX_CPUID_ENTRIES 80 134 #define KVM_NR_FIXED_MTRR_REGION 88 135 #define KVM_NR_VAR_MTRR 8 136 137 #define ASYNC_PF_PER_VCPU 64 138 139 enum kvm_reg { 140 VCPU_REGS_RAX = __VCPU_REGS_RAX, 141 VCPU_REGS_RCX = __VCPU_REGS_RCX, 142 VCPU_REGS_RDX = __VCPU_REGS_RDX, 143 VCPU_REGS_RBX = __VCPU_REGS_RBX, 144 VCPU_REGS_RSP = __VCPU_REGS_RSP, 145 VCPU_REGS_RBP = __VCPU_REGS_RBP, 146 VCPU_REGS_RSI = __VCPU_REGS_RSI, 147 VCPU_REGS_RDI = __VCPU_REGS_RDI, 148 #ifdef CONFIG_X86_64 149 VCPU_REGS_R8 = __VCPU_REGS_R8, 150 VCPU_REGS_R9 = __VCPU_REGS_R9, 151 VCPU_REGS_R10 = __VCPU_REGS_R10, 152 VCPU_REGS_R11 = __VCPU_REGS_R11, 153 VCPU_REGS_R12 = __VCPU_REGS_R12, 154 VCPU_REGS_R13 = __VCPU_REGS_R13, 155 VCPU_REGS_R14 = __VCPU_REGS_R14, 156 VCPU_REGS_R15 = __VCPU_REGS_R15, 157 #endif 158 VCPU_REGS_RIP, 159 NR_VCPU_REGS, 160 161 VCPU_EXREG_PDPTR = NR_VCPU_REGS, 162 VCPU_EXREG_CR3, 163 VCPU_EXREG_RFLAGS, 164 VCPU_EXREG_SEGMENTS, 165 }; 166 167 enum { 168 VCPU_SREG_ES, 169 VCPU_SREG_CS, 170 VCPU_SREG_SS, 171 VCPU_SREG_DS, 172 VCPU_SREG_FS, 173 VCPU_SREG_GS, 174 VCPU_SREG_TR, 175 VCPU_SREG_LDTR, 176 }; 177 178 #include <asm/kvm_emulate.h> 179 180 #define KVM_NR_MEM_OBJS 40 181 182 #define KVM_NR_DB_REGS 4 183 184 #define DR6_BD (1 << 13) 185 #define DR6_BS (1 << 14) 186 #define DR6_BT (1 << 15) 187 #define DR6_RTM (1 << 16) 188 #define DR6_FIXED_1 0xfffe0ff0 189 #define DR6_INIT 0xffff0ff0 190 #define DR6_VOLATILE 0x0001e00f 191 192 #define DR7_BP_EN_MASK 0x000000ff 193 #define DR7_GE (1 << 9) 194 #define DR7_GD (1 << 13) 195 #define DR7_FIXED_1 0x00000400 196 #define DR7_VOLATILE 0xffff2bff 197 198 #define PFERR_PRESENT_BIT 0 199 #define PFERR_WRITE_BIT 1 200 #define PFERR_USER_BIT 2 201 #define PFERR_RSVD_BIT 3 202 #define PFERR_FETCH_BIT 4 203 #define PFERR_PK_BIT 5 204 #define PFERR_GUEST_FINAL_BIT 32 205 #define PFERR_GUEST_PAGE_BIT 33 206 207 #define PFERR_PRESENT_MASK (1U << PFERR_PRESENT_BIT) 208 #define PFERR_WRITE_MASK (1U << PFERR_WRITE_BIT) 209 #define PFERR_USER_MASK (1U << PFERR_USER_BIT) 210 #define PFERR_RSVD_MASK (1U << PFERR_RSVD_BIT) 211 #define PFERR_FETCH_MASK (1U << PFERR_FETCH_BIT) 212 #define PFERR_PK_MASK (1U << PFERR_PK_BIT) 213 #define PFERR_GUEST_FINAL_MASK (1ULL << PFERR_GUEST_FINAL_BIT) 214 #define PFERR_GUEST_PAGE_MASK (1ULL << PFERR_GUEST_PAGE_BIT) 215 216 #define PFERR_NESTED_GUEST_PAGE (PFERR_GUEST_PAGE_MASK | \ 217 PFERR_WRITE_MASK | \ 218 PFERR_PRESENT_MASK) 219 220 /* apic attention bits */ 221 #define KVM_APIC_CHECK_VAPIC 0 222 /* 223 * The following bit is set with PV-EOI, unset on EOI. 224 * We detect PV-EOI changes by guest by comparing 225 * this bit with PV-EOI in guest memory. 226 * See the implementation in apic_update_pv_eoi. 227 */ 228 #define KVM_APIC_PV_EOI_PENDING 1 229 230 struct kvm_kernel_irq_routing_entry; 231 232 /* 233 * We don't want allocation failures within the mmu code, so we preallocate 234 * enough memory for a single page fault in a cache. 235 */ 236 struct kvm_mmu_memory_cache { 237 int nobjs; 238 void *objects[KVM_NR_MEM_OBJS]; 239 }; 240 241 /* 242 * the pages used as guest page table on soft mmu are tracked by 243 * kvm_memory_slot.arch.gfn_track which is 16 bits, so the role bits used 244 * by indirect shadow page can not be more than 15 bits. 245 * 246 * Currently, we used 14 bits that are @level, @gpte_is_8_bytes, @quadrant, @access, 247 * @nxe, @cr0_wp, @smep_andnot_wp and @smap_andnot_wp. 248 */ 249 union kvm_mmu_page_role { 250 u32 word; 251 struct { 252 unsigned level:4; 253 unsigned gpte_is_8_bytes:1; 254 unsigned quadrant:2; 255 unsigned direct:1; 256 unsigned access:3; 257 unsigned invalid:1; 258 unsigned nxe:1; 259 unsigned cr0_wp:1; 260 unsigned smep_andnot_wp:1; 261 unsigned smap_andnot_wp:1; 262 unsigned ad_disabled:1; 263 unsigned guest_mode:1; 264 unsigned :6; 265 266 /* 267 * This is left at the top of the word so that 268 * kvm_memslots_for_spte_role can extract it with a 269 * simple shift. While there is room, give it a whole 270 * byte so it is also faster to load it from memory. 271 */ 272 unsigned smm:8; 273 }; 274 }; 275 276 union kvm_mmu_extended_role { 277 /* 278 * This structure complements kvm_mmu_page_role caching everything needed for 279 * MMU configuration. If nothing in both these structures changed, MMU 280 * re-configuration can be skipped. @valid bit is set on first usage so we don't 281 * treat all-zero structure as valid data. 282 */ 283 u32 word; 284 struct { 285 unsigned int valid:1; 286 unsigned int execonly:1; 287 unsigned int cr0_pg:1; 288 unsigned int cr4_pae:1; 289 unsigned int cr4_pse:1; 290 unsigned int cr4_pke:1; 291 unsigned int cr4_smap:1; 292 unsigned int cr4_smep:1; 293 unsigned int cr4_la57:1; 294 unsigned int maxphyaddr:6; 295 }; 296 }; 297 298 union kvm_mmu_role { 299 u64 as_u64; 300 struct { 301 union kvm_mmu_page_role base; 302 union kvm_mmu_extended_role ext; 303 }; 304 }; 305 306 struct kvm_rmap_head { 307 unsigned long val; 308 }; 309 310 struct kvm_mmu_page { 311 struct list_head link; 312 struct hlist_node hash_link; 313 struct list_head lpage_disallowed_link; 314 315 bool unsync; 316 u8 mmu_valid_gen; 317 bool mmio_cached; 318 bool lpage_disallowed; /* Can't be replaced by an equiv large page */ 319 320 /* 321 * The following two entries are used to key the shadow page in the 322 * hash table. 323 */ 324 union kvm_mmu_page_role role; 325 gfn_t gfn; 326 327 u64 *spt; 328 /* hold the gfn of each spte inside spt */ 329 gfn_t *gfns; 330 int root_count; /* Currently serving as active root */ 331 unsigned int unsync_children; 332 struct kvm_rmap_head parent_ptes; /* rmap pointers to parent sptes */ 333 DECLARE_BITMAP(unsync_child_bitmap, 512); 334 335 #ifdef CONFIG_X86_32 336 /* 337 * Used out of the mmu-lock to avoid reading spte values while an 338 * update is in progress; see the comments in __get_spte_lockless(). 339 */ 340 int clear_spte_count; 341 #endif 342 343 /* Number of writes since the last time traversal visited this page. */ 344 atomic_t write_flooding_count; 345 }; 346 347 struct kvm_pio_request { 348 unsigned long linear_rip; 349 unsigned long count; 350 int in; 351 int port; 352 int size; 353 }; 354 355 #define PT64_ROOT_MAX_LEVEL 5 356 357 struct rsvd_bits_validate { 358 u64 rsvd_bits_mask[2][PT64_ROOT_MAX_LEVEL]; 359 u64 bad_mt_xwr; 360 }; 361 362 struct kvm_mmu_root_info { 363 gpa_t cr3; 364 hpa_t hpa; 365 }; 366 367 #define KVM_MMU_ROOT_INFO_INVALID \ 368 ((struct kvm_mmu_root_info) { .cr3 = INVALID_PAGE, .hpa = INVALID_PAGE }) 369 370 #define KVM_MMU_NUM_PREV_ROOTS 3 371 372 /* 373 * x86 supports 4 paging modes (5-level 64-bit, 4-level 64-bit, 3-level 32-bit, 374 * and 2-level 32-bit). The kvm_mmu structure abstracts the details of the 375 * current mmu mode. 376 */ 377 struct kvm_mmu { 378 void (*set_cr3)(struct kvm_vcpu *vcpu, unsigned long root); 379 unsigned long (*get_cr3)(struct kvm_vcpu *vcpu); 380 u64 (*get_pdptr)(struct kvm_vcpu *vcpu, int index); 381 int (*page_fault)(struct kvm_vcpu *vcpu, gva_t gva, u32 err, 382 bool prefault); 383 void (*inject_page_fault)(struct kvm_vcpu *vcpu, 384 struct x86_exception *fault); 385 gpa_t (*gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t gva, u32 access, 386 struct x86_exception *exception); 387 gpa_t (*translate_gpa)(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access, 388 struct x86_exception *exception); 389 int (*sync_page)(struct kvm_vcpu *vcpu, 390 struct kvm_mmu_page *sp); 391 void (*invlpg)(struct kvm_vcpu *vcpu, gva_t gva, hpa_t root_hpa); 392 void (*update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, 393 u64 *spte, const void *pte); 394 hpa_t root_hpa; 395 gpa_t root_cr3; 396 union kvm_mmu_role mmu_role; 397 u8 root_level; 398 u8 shadow_root_level; 399 u8 ept_ad; 400 bool direct_map; 401 struct kvm_mmu_root_info prev_roots[KVM_MMU_NUM_PREV_ROOTS]; 402 403 /* 404 * Bitmap; bit set = permission fault 405 * Byte index: page fault error code [4:1] 406 * Bit index: pte permissions in ACC_* format 407 */ 408 u8 permissions[16]; 409 410 /* 411 * The pkru_mask indicates if protection key checks are needed. It 412 * consists of 16 domains indexed by page fault error code bits [4:1], 413 * with PFEC.RSVD replaced by ACC_USER_MASK from the page tables. 414 * Each domain has 2 bits which are ANDed with AD and WD from PKRU. 415 */ 416 u32 pkru_mask; 417 418 u64 *pae_root; 419 u64 *lm_root; 420 421 /* 422 * check zero bits on shadow page table entries, these 423 * bits include not only hardware reserved bits but also 424 * the bits spte never used. 425 */ 426 struct rsvd_bits_validate shadow_zero_check; 427 428 struct rsvd_bits_validate guest_rsvd_check; 429 430 /* Can have large pages at levels 2..last_nonleaf_level-1. */ 431 u8 last_nonleaf_level; 432 433 bool nx; 434 435 u64 pdptrs[4]; /* pae */ 436 }; 437 438 struct kvm_tlb_range { 439 u64 start_gfn; 440 u64 pages; 441 }; 442 443 enum pmc_type { 444 KVM_PMC_GP = 0, 445 KVM_PMC_FIXED, 446 }; 447 448 struct kvm_pmc { 449 enum pmc_type type; 450 u8 idx; 451 u64 counter; 452 u64 eventsel; 453 struct perf_event *perf_event; 454 struct kvm_vcpu *vcpu; 455 /* 456 * eventsel value for general purpose counters, 457 * ctrl value for fixed counters. 458 */ 459 u64 current_config; 460 }; 461 462 struct kvm_pmu { 463 unsigned nr_arch_gp_counters; 464 unsigned nr_arch_fixed_counters; 465 unsigned available_event_types; 466 u64 fixed_ctr_ctrl; 467 u64 global_ctrl; 468 u64 global_status; 469 u64 global_ovf_ctrl; 470 u64 counter_bitmask[2]; 471 u64 global_ctrl_mask; 472 u64 global_ovf_ctrl_mask; 473 u64 reserved_bits; 474 u8 version; 475 struct kvm_pmc gp_counters[INTEL_PMC_MAX_GENERIC]; 476 struct kvm_pmc fixed_counters[INTEL_PMC_MAX_FIXED]; 477 struct irq_work irq_work; 478 DECLARE_BITMAP(reprogram_pmi, X86_PMC_IDX_MAX); 479 DECLARE_BITMAP(all_valid_pmc_idx, X86_PMC_IDX_MAX); 480 DECLARE_BITMAP(pmc_in_use, X86_PMC_IDX_MAX); 481 482 /* 483 * The gate to release perf_events not marked in 484 * pmc_in_use only once in a vcpu time slice. 485 */ 486 bool need_cleanup; 487 488 /* 489 * The total number of programmed perf_events and it helps to avoid 490 * redundant check before cleanup if guest don't use vPMU at all. 491 */ 492 u8 event_count; 493 }; 494 495 struct kvm_pmu_ops; 496 497 enum { 498 KVM_DEBUGREG_BP_ENABLED = 1, 499 KVM_DEBUGREG_WONT_EXIT = 2, 500 KVM_DEBUGREG_RELOAD = 4, 501 }; 502 503 struct kvm_mtrr_range { 504 u64 base; 505 u64 mask; 506 struct list_head node; 507 }; 508 509 struct kvm_mtrr { 510 struct kvm_mtrr_range var_ranges[KVM_NR_VAR_MTRR]; 511 mtrr_type fixed_ranges[KVM_NR_FIXED_MTRR_REGION]; 512 u64 deftype; 513 514 struct list_head head; 515 }; 516 517 /* Hyper-V SynIC timer */ 518 struct kvm_vcpu_hv_stimer { 519 struct hrtimer timer; 520 int index; 521 union hv_stimer_config config; 522 u64 count; 523 u64 exp_time; 524 struct hv_message msg; 525 bool msg_pending; 526 }; 527 528 /* Hyper-V synthetic interrupt controller (SynIC)*/ 529 struct kvm_vcpu_hv_synic { 530 u64 version; 531 u64 control; 532 u64 msg_page; 533 u64 evt_page; 534 atomic64_t sint[HV_SYNIC_SINT_COUNT]; 535 atomic_t sint_to_gsi[HV_SYNIC_SINT_COUNT]; 536 DECLARE_BITMAP(auto_eoi_bitmap, 256); 537 DECLARE_BITMAP(vec_bitmap, 256); 538 bool active; 539 bool dont_zero_synic_pages; 540 }; 541 542 /* Hyper-V per vcpu emulation context */ 543 struct kvm_vcpu_hv { 544 u32 vp_index; 545 u64 hv_vapic; 546 s64 runtime_offset; 547 struct kvm_vcpu_hv_synic synic; 548 struct kvm_hyperv_exit exit; 549 struct kvm_vcpu_hv_stimer stimer[HV_SYNIC_STIMER_COUNT]; 550 DECLARE_BITMAP(stimer_pending_bitmap, HV_SYNIC_STIMER_COUNT); 551 cpumask_t tlb_flush; 552 }; 553 554 struct kvm_vcpu_arch { 555 /* 556 * rip and regs accesses must go through 557 * kvm_{register,rip}_{read,write} functions. 558 */ 559 unsigned long regs[NR_VCPU_REGS]; 560 u32 regs_avail; 561 u32 regs_dirty; 562 563 unsigned long cr0; 564 unsigned long cr0_guest_owned_bits; 565 unsigned long cr2; 566 unsigned long cr3; 567 unsigned long cr4; 568 unsigned long cr4_guest_owned_bits; 569 unsigned long cr8; 570 u32 pkru; 571 u32 hflags; 572 u64 efer; 573 u64 apic_base; 574 struct kvm_lapic *apic; /* kernel irqchip context */ 575 bool apicv_active; 576 bool load_eoi_exitmap_pending; 577 DECLARE_BITMAP(ioapic_handled_vectors, 256); 578 unsigned long apic_attention; 579 int32_t apic_arb_prio; 580 int mp_state; 581 u64 ia32_misc_enable_msr; 582 u64 smbase; 583 u64 smi_count; 584 bool tpr_access_reporting; 585 bool xsaves_enabled; 586 u64 ia32_xss; 587 u64 microcode_version; 588 u64 arch_capabilities; 589 590 /* 591 * Paging state of the vcpu 592 * 593 * If the vcpu runs in guest mode with two level paging this still saves 594 * the paging mode of the l1 guest. This context is always used to 595 * handle faults. 596 */ 597 struct kvm_mmu *mmu; 598 599 /* Non-nested MMU for L1 */ 600 struct kvm_mmu root_mmu; 601 602 /* L1 MMU when running nested */ 603 struct kvm_mmu guest_mmu; 604 605 /* 606 * Paging state of an L2 guest (used for nested npt) 607 * 608 * This context will save all necessary information to walk page tables 609 * of the an L2 guest. This context is only initialized for page table 610 * walking and not for faulting since we never handle l2 page faults on 611 * the host. 612 */ 613 struct kvm_mmu nested_mmu; 614 615 /* 616 * Pointer to the mmu context currently used for 617 * gva_to_gpa translations. 618 */ 619 struct kvm_mmu *walk_mmu; 620 621 struct kvm_mmu_memory_cache mmu_pte_list_desc_cache; 622 struct kvm_mmu_memory_cache mmu_page_cache; 623 struct kvm_mmu_memory_cache mmu_page_header_cache; 624 625 /* 626 * QEMU userspace and the guest each have their own FPU state. 627 * In vcpu_run, we switch between the user and guest FPU contexts. 628 * While running a VCPU, the VCPU thread will have the guest FPU 629 * context. 630 * 631 * Note that while the PKRU state lives inside the fpu registers, 632 * it is switched out separately at VMENTER and VMEXIT time. The 633 * "guest_fpu" state here contains the guest FPU context, with the 634 * host PRKU bits. 635 */ 636 struct fpu *user_fpu; 637 struct fpu *guest_fpu; 638 639 u64 xcr0; 640 u64 guest_supported_xcr0; 641 u32 guest_xstate_size; 642 643 struct kvm_pio_request pio; 644 void *pio_data; 645 646 u8 event_exit_inst_len; 647 648 struct kvm_queued_exception { 649 bool pending; 650 bool injected; 651 bool has_error_code; 652 u8 nr; 653 u32 error_code; 654 unsigned long payload; 655 bool has_payload; 656 u8 nested_apf; 657 } exception; 658 659 struct kvm_queued_interrupt { 660 bool injected; 661 bool soft; 662 u8 nr; 663 } interrupt; 664 665 int halt_request; /* real mode on Intel only */ 666 667 int cpuid_nent; 668 struct kvm_cpuid_entry2 cpuid_entries[KVM_MAX_CPUID_ENTRIES]; 669 670 int maxphyaddr; 671 672 /* emulate context */ 673 674 struct x86_emulate_ctxt emulate_ctxt; 675 bool emulate_regs_need_sync_to_vcpu; 676 bool emulate_regs_need_sync_from_vcpu; 677 int (*complete_userspace_io)(struct kvm_vcpu *vcpu); 678 679 gpa_t time; 680 struct pvclock_vcpu_time_info hv_clock; 681 unsigned int hw_tsc_khz; 682 struct gfn_to_hva_cache pv_time; 683 bool pv_time_enabled; 684 /* set guest stopped flag in pvclock flags field */ 685 bool pvclock_set_guest_stopped_request; 686 687 struct { 688 u64 msr_val; 689 u64 last_steal; 690 struct gfn_to_hva_cache stime; 691 struct kvm_steal_time steal; 692 } st; 693 694 u64 tsc_offset; 695 u64 last_guest_tsc; 696 u64 last_host_tsc; 697 u64 tsc_offset_adjustment; 698 u64 this_tsc_nsec; 699 u64 this_tsc_write; 700 u64 this_tsc_generation; 701 bool tsc_catchup; 702 bool tsc_always_catchup; 703 s8 virtual_tsc_shift; 704 u32 virtual_tsc_mult; 705 u32 virtual_tsc_khz; 706 s64 ia32_tsc_adjust_msr; 707 u64 msr_ia32_power_ctl; 708 u64 tsc_scaling_ratio; 709 710 atomic_t nmi_queued; /* unprocessed asynchronous NMIs */ 711 unsigned nmi_pending; /* NMI queued after currently running handler */ 712 bool nmi_injected; /* Trying to inject an NMI this entry */ 713 bool smi_pending; /* SMI queued after currently running handler */ 714 715 struct kvm_mtrr mtrr_state; 716 u64 pat; 717 718 unsigned switch_db_regs; 719 unsigned long db[KVM_NR_DB_REGS]; 720 unsigned long dr6; 721 unsigned long dr7; 722 unsigned long eff_db[KVM_NR_DB_REGS]; 723 unsigned long guest_debug_dr7; 724 u64 msr_platform_info; 725 u64 msr_misc_features_enables; 726 727 u64 mcg_cap; 728 u64 mcg_status; 729 u64 mcg_ctl; 730 u64 mcg_ext_ctl; 731 u64 *mce_banks; 732 733 /* Cache MMIO info */ 734 u64 mmio_gva; 735 unsigned mmio_access; 736 gfn_t mmio_gfn; 737 u64 mmio_gen; 738 739 struct kvm_pmu pmu; 740 741 /* used for guest single stepping over the given code position */ 742 unsigned long singlestep_rip; 743 744 struct kvm_vcpu_hv hyperv; 745 746 cpumask_var_t wbinvd_dirty_mask; 747 748 unsigned long last_retry_eip; 749 unsigned long last_retry_addr; 750 751 struct { 752 bool halted; 753 gfn_t gfns[roundup_pow_of_two(ASYNC_PF_PER_VCPU)]; 754 struct gfn_to_hva_cache data; 755 u64 msr_val; 756 u32 id; 757 bool send_user_only; 758 u32 host_apf_reason; 759 unsigned long nested_apf_token; 760 bool delivery_as_pf_vmexit; 761 } apf; 762 763 /* OSVW MSRs (AMD only) */ 764 struct { 765 u64 length; 766 u64 status; 767 } osvw; 768 769 struct { 770 u64 msr_val; 771 struct gfn_to_hva_cache data; 772 } pv_eoi; 773 774 u64 msr_kvm_poll_control; 775 776 /* 777 * Indicate whether the access faults on its page table in guest 778 * which is set when fix page fault and used to detect unhandeable 779 * instruction. 780 */ 781 bool write_fault_to_shadow_pgtable; 782 783 /* set at EPT violation at this point */ 784 unsigned long exit_qualification; 785 786 /* pv related host specific info */ 787 struct { 788 bool pv_unhalted; 789 } pv; 790 791 int pending_ioapic_eoi; 792 int pending_external_vector; 793 794 /* GPA available */ 795 bool gpa_available; 796 gpa_t gpa_val; 797 798 /* be preempted when it's in kernel-mode(cpl=0) */ 799 bool preempted_in_kernel; 800 801 /* Flush the L1 Data cache for L1TF mitigation on VMENTER */ 802 bool l1tf_flush_l1d; 803 804 /* AMD MSRC001_0015 Hardware Configuration */ 805 u64 msr_hwcr; 806 }; 807 808 struct kvm_lpage_info { 809 int disallow_lpage; 810 }; 811 812 struct kvm_arch_memory_slot { 813 struct kvm_rmap_head *rmap[KVM_NR_PAGE_SIZES]; 814 struct kvm_lpage_info *lpage_info[KVM_NR_PAGE_SIZES - 1]; 815 unsigned short *gfn_track[KVM_PAGE_TRACK_MAX]; 816 }; 817 818 /* 819 * We use as the mode the number of bits allocated in the LDR for the 820 * logical processor ID. It happens that these are all powers of two. 821 * This makes it is very easy to detect cases where the APICs are 822 * configured for multiple modes; in that case, we cannot use the map and 823 * hence cannot use kvm_irq_delivery_to_apic_fast either. 824 */ 825 #define KVM_APIC_MODE_XAPIC_CLUSTER 4 826 #define KVM_APIC_MODE_XAPIC_FLAT 8 827 #define KVM_APIC_MODE_X2APIC 16 828 829 struct kvm_apic_map { 830 struct rcu_head rcu; 831 u8 mode; 832 u32 max_apic_id; 833 union { 834 struct kvm_lapic *xapic_flat_map[8]; 835 struct kvm_lapic *xapic_cluster_map[16][4]; 836 }; 837 struct kvm_lapic *phys_map[]; 838 }; 839 840 /* Hyper-V emulation context */ 841 struct kvm_hv { 842 struct mutex hv_lock; 843 u64 hv_guest_os_id; 844 u64 hv_hypercall; 845 u64 hv_tsc_page; 846 847 /* Hyper-v based guest crash (NT kernel bugcheck) parameters */ 848 u64 hv_crash_param[HV_X64_MSR_CRASH_PARAMS]; 849 u64 hv_crash_ctl; 850 851 HV_REFERENCE_TSC_PAGE tsc_ref; 852 853 struct idr conn_to_evt; 854 855 u64 hv_reenlightenment_control; 856 u64 hv_tsc_emulation_control; 857 u64 hv_tsc_emulation_status; 858 859 /* How many vCPUs have VP index != vCPU index */ 860 atomic_t num_mismatched_vp_indexes; 861 862 struct hv_partition_assist_pg *hv_pa_pg; 863 }; 864 865 enum kvm_irqchip_mode { 866 KVM_IRQCHIP_NONE, 867 KVM_IRQCHIP_KERNEL, /* created with KVM_CREATE_IRQCHIP */ 868 KVM_IRQCHIP_SPLIT, /* created with KVM_CAP_SPLIT_IRQCHIP */ 869 }; 870 871 struct kvm_arch { 872 unsigned long n_used_mmu_pages; 873 unsigned long n_requested_mmu_pages; 874 unsigned long n_max_mmu_pages; 875 unsigned int indirect_shadow_pages; 876 u8 mmu_valid_gen; 877 struct hlist_head mmu_page_hash[KVM_NUM_MMU_PAGES]; 878 /* 879 * Hash table of struct kvm_mmu_page. 880 */ 881 struct list_head active_mmu_pages; 882 struct list_head zapped_obsolete_pages; 883 struct list_head lpage_disallowed_mmu_pages; 884 struct kvm_page_track_notifier_node mmu_sp_tracker; 885 struct kvm_page_track_notifier_head track_notifier_head; 886 887 struct list_head assigned_dev_head; 888 struct iommu_domain *iommu_domain; 889 bool iommu_noncoherent; 890 #define __KVM_HAVE_ARCH_NONCOHERENT_DMA 891 atomic_t noncoherent_dma_count; 892 #define __KVM_HAVE_ARCH_ASSIGNED_DEVICE 893 atomic_t assigned_device_count; 894 struct kvm_pic *vpic; 895 struct kvm_ioapic *vioapic; 896 struct kvm_pit *vpit; 897 atomic_t vapics_in_nmi_mode; 898 struct mutex apic_map_lock; 899 struct kvm_apic_map *apic_map; 900 901 bool apic_access_page_done; 902 903 gpa_t wall_clock; 904 905 bool mwait_in_guest; 906 bool hlt_in_guest; 907 bool pause_in_guest; 908 bool cstate_in_guest; 909 910 unsigned long irq_sources_bitmap; 911 s64 kvmclock_offset; 912 raw_spinlock_t tsc_write_lock; 913 u64 last_tsc_nsec; 914 u64 last_tsc_write; 915 u32 last_tsc_khz; 916 u64 cur_tsc_nsec; 917 u64 cur_tsc_write; 918 u64 cur_tsc_offset; 919 u64 cur_tsc_generation; 920 int nr_vcpus_matched_tsc; 921 922 spinlock_t pvclock_gtod_sync_lock; 923 bool use_master_clock; 924 u64 master_kernel_ns; 925 u64 master_cycle_now; 926 struct delayed_work kvmclock_update_work; 927 struct delayed_work kvmclock_sync_work; 928 929 struct kvm_xen_hvm_config xen_hvm_config; 930 931 /* reads protected by irq_srcu, writes by irq_lock */ 932 struct hlist_head mask_notifier_list; 933 934 struct kvm_hv hyperv; 935 936 #ifdef CONFIG_KVM_MMU_AUDIT 937 int audit_point; 938 #endif 939 940 bool backwards_tsc_observed; 941 bool boot_vcpu_runs_old_kvmclock; 942 u32 bsp_vcpu_id; 943 944 u64 disabled_quirks; 945 946 enum kvm_irqchip_mode irqchip_mode; 947 u8 nr_reserved_ioapic_pins; 948 949 bool disabled_lapic_found; 950 951 bool x2apic_format; 952 bool x2apic_broadcast_quirk_disabled; 953 954 bool guest_can_read_msr_platform_info; 955 bool exception_payload_enabled; 956 957 struct kvm_pmu_event_filter *pmu_event_filter; 958 struct task_struct *nx_lpage_recovery_thread; 959 }; 960 961 struct kvm_vm_stat { 962 ulong mmu_shadow_zapped; 963 ulong mmu_pte_write; 964 ulong mmu_pte_updated; 965 ulong mmu_pde_zapped; 966 ulong mmu_flooded; 967 ulong mmu_recycled; 968 ulong mmu_cache_miss; 969 ulong mmu_unsync; 970 ulong remote_tlb_flush; 971 ulong lpages; 972 ulong nx_lpage_splits; 973 ulong max_mmu_page_hash_collisions; 974 }; 975 976 struct kvm_vcpu_stat { 977 u64 pf_fixed; 978 u64 pf_guest; 979 u64 tlb_flush; 980 u64 invlpg; 981 982 u64 exits; 983 u64 io_exits; 984 u64 mmio_exits; 985 u64 signal_exits; 986 u64 irq_window_exits; 987 u64 nmi_window_exits; 988 u64 l1d_flush; 989 u64 halt_exits; 990 u64 halt_successful_poll; 991 u64 halt_attempted_poll; 992 u64 halt_poll_invalid; 993 u64 halt_wakeup; 994 u64 request_irq_exits; 995 u64 irq_exits; 996 u64 host_state_reload; 997 u64 fpu_reload; 998 u64 insn_emulation; 999 u64 insn_emulation_fail; 1000 u64 hypercalls; 1001 u64 irq_injections; 1002 u64 nmi_injections; 1003 u64 req_event; 1004 }; 1005 1006 struct x86_instruction_info; 1007 1008 struct msr_data { 1009 bool host_initiated; 1010 u32 index; 1011 u64 data; 1012 }; 1013 1014 struct kvm_lapic_irq { 1015 u32 vector; 1016 u16 delivery_mode; 1017 u16 dest_mode; 1018 bool level; 1019 u16 trig_mode; 1020 u32 shorthand; 1021 u32 dest_id; 1022 bool msi_redir_hint; 1023 }; 1024 1025 struct kvm_x86_ops { 1026 int (*cpu_has_kvm_support)(void); /* __init */ 1027 int (*disabled_by_bios)(void); /* __init */ 1028 int (*hardware_enable)(void); 1029 void (*hardware_disable)(void); 1030 int (*check_processor_compatibility)(void);/* __init */ 1031 int (*hardware_setup)(void); /* __init */ 1032 void (*hardware_unsetup)(void); /* __exit */ 1033 bool (*cpu_has_accelerated_tpr)(void); 1034 bool (*has_emulated_msr)(int index); 1035 void (*cpuid_update)(struct kvm_vcpu *vcpu); 1036 1037 struct kvm *(*vm_alloc)(void); 1038 void (*vm_free)(struct kvm *); 1039 int (*vm_init)(struct kvm *kvm); 1040 void (*vm_destroy)(struct kvm *kvm); 1041 1042 /* Create, but do not attach this VCPU */ 1043 struct kvm_vcpu *(*vcpu_create)(struct kvm *kvm, unsigned id); 1044 void (*vcpu_free)(struct kvm_vcpu *vcpu); 1045 void (*vcpu_reset)(struct kvm_vcpu *vcpu, bool init_event); 1046 1047 void (*prepare_guest_switch)(struct kvm_vcpu *vcpu); 1048 void (*vcpu_load)(struct kvm_vcpu *vcpu, int cpu); 1049 void (*vcpu_put)(struct kvm_vcpu *vcpu); 1050 1051 void (*update_bp_intercept)(struct kvm_vcpu *vcpu); 1052 int (*get_msr)(struct kvm_vcpu *vcpu, struct msr_data *msr); 1053 int (*set_msr)(struct kvm_vcpu *vcpu, struct msr_data *msr); 1054 u64 (*get_segment_base)(struct kvm_vcpu *vcpu, int seg); 1055 void (*get_segment)(struct kvm_vcpu *vcpu, 1056 struct kvm_segment *var, int seg); 1057 int (*get_cpl)(struct kvm_vcpu *vcpu); 1058 void (*set_segment)(struct kvm_vcpu *vcpu, 1059 struct kvm_segment *var, int seg); 1060 void (*get_cs_db_l_bits)(struct kvm_vcpu *vcpu, int *db, int *l); 1061 void (*decache_cr0_guest_bits)(struct kvm_vcpu *vcpu); 1062 void (*decache_cr4_guest_bits)(struct kvm_vcpu *vcpu); 1063 void (*set_cr0)(struct kvm_vcpu *vcpu, unsigned long cr0); 1064 void (*set_cr3)(struct kvm_vcpu *vcpu, unsigned long cr3); 1065 int (*set_cr4)(struct kvm_vcpu *vcpu, unsigned long cr4); 1066 void (*set_efer)(struct kvm_vcpu *vcpu, u64 efer); 1067 void (*get_idt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt); 1068 void (*set_idt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt); 1069 void (*get_gdt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt); 1070 void (*set_gdt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt); 1071 u64 (*get_dr6)(struct kvm_vcpu *vcpu); 1072 void (*set_dr6)(struct kvm_vcpu *vcpu, unsigned long value); 1073 void (*sync_dirty_debug_regs)(struct kvm_vcpu *vcpu); 1074 void (*set_dr7)(struct kvm_vcpu *vcpu, unsigned long value); 1075 void (*cache_reg)(struct kvm_vcpu *vcpu, enum kvm_reg reg); 1076 unsigned long (*get_rflags)(struct kvm_vcpu *vcpu); 1077 void (*set_rflags)(struct kvm_vcpu *vcpu, unsigned long rflags); 1078 1079 void (*tlb_flush)(struct kvm_vcpu *vcpu, bool invalidate_gpa); 1080 int (*tlb_remote_flush)(struct kvm *kvm); 1081 int (*tlb_remote_flush_with_range)(struct kvm *kvm, 1082 struct kvm_tlb_range *range); 1083 1084 /* 1085 * Flush any TLB entries associated with the given GVA. 1086 * Does not need to flush GPA->HPA mappings. 1087 * Can potentially get non-canonical addresses through INVLPGs, which 1088 * the implementation may choose to ignore if appropriate. 1089 */ 1090 void (*tlb_flush_gva)(struct kvm_vcpu *vcpu, gva_t addr); 1091 1092 void (*run)(struct kvm_vcpu *vcpu); 1093 int (*handle_exit)(struct kvm_vcpu *vcpu); 1094 int (*skip_emulated_instruction)(struct kvm_vcpu *vcpu); 1095 void (*set_interrupt_shadow)(struct kvm_vcpu *vcpu, int mask); 1096 u32 (*get_interrupt_shadow)(struct kvm_vcpu *vcpu); 1097 void (*patch_hypercall)(struct kvm_vcpu *vcpu, 1098 unsigned char *hypercall_addr); 1099 void (*set_irq)(struct kvm_vcpu *vcpu); 1100 void (*set_nmi)(struct kvm_vcpu *vcpu); 1101 void (*queue_exception)(struct kvm_vcpu *vcpu); 1102 void (*cancel_injection)(struct kvm_vcpu *vcpu); 1103 int (*interrupt_allowed)(struct kvm_vcpu *vcpu); 1104 int (*nmi_allowed)(struct kvm_vcpu *vcpu); 1105 bool (*get_nmi_mask)(struct kvm_vcpu *vcpu); 1106 void (*set_nmi_mask)(struct kvm_vcpu *vcpu, bool masked); 1107 void (*enable_nmi_window)(struct kvm_vcpu *vcpu); 1108 void (*enable_irq_window)(struct kvm_vcpu *vcpu); 1109 void (*update_cr8_intercept)(struct kvm_vcpu *vcpu, int tpr, int irr); 1110 bool (*get_enable_apicv)(struct kvm *kvm); 1111 void (*refresh_apicv_exec_ctrl)(struct kvm_vcpu *vcpu); 1112 void (*hwapic_irr_update)(struct kvm_vcpu *vcpu, int max_irr); 1113 void (*hwapic_isr_update)(struct kvm_vcpu *vcpu, int isr); 1114 bool (*guest_apic_has_interrupt)(struct kvm_vcpu *vcpu); 1115 void (*load_eoi_exitmap)(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap); 1116 void (*set_virtual_apic_mode)(struct kvm_vcpu *vcpu); 1117 void (*set_apic_access_page_addr)(struct kvm_vcpu *vcpu, hpa_t hpa); 1118 void (*deliver_posted_interrupt)(struct kvm_vcpu *vcpu, int vector); 1119 int (*sync_pir_to_irr)(struct kvm_vcpu *vcpu); 1120 int (*set_tss_addr)(struct kvm *kvm, unsigned int addr); 1121 int (*set_identity_map_addr)(struct kvm *kvm, u64 ident_addr); 1122 int (*get_tdp_level)(struct kvm_vcpu *vcpu); 1123 u64 (*get_mt_mask)(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio); 1124 int (*get_lpage_level)(void); 1125 bool (*rdtscp_supported)(void); 1126 bool (*invpcid_supported)(void); 1127 1128 void (*set_tdp_cr3)(struct kvm_vcpu *vcpu, unsigned long cr3); 1129 1130 void (*set_supported_cpuid)(u32 func, struct kvm_cpuid_entry2 *entry); 1131 1132 bool (*has_wbinvd_exit)(void); 1133 1134 u64 (*read_l1_tsc_offset)(struct kvm_vcpu *vcpu); 1135 /* Returns actual tsc_offset set in active VMCS */ 1136 u64 (*write_l1_tsc_offset)(struct kvm_vcpu *vcpu, u64 offset); 1137 1138 void (*get_exit_info)(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2); 1139 1140 int (*check_intercept)(struct kvm_vcpu *vcpu, 1141 struct x86_instruction_info *info, 1142 enum x86_intercept_stage stage); 1143 void (*handle_exit_irqoff)(struct kvm_vcpu *vcpu); 1144 bool (*mpx_supported)(void); 1145 bool (*xsaves_supported)(void); 1146 bool (*umip_emulated)(void); 1147 bool (*pt_supported)(void); 1148 1149 int (*check_nested_events)(struct kvm_vcpu *vcpu, bool external_intr); 1150 void (*request_immediate_exit)(struct kvm_vcpu *vcpu); 1151 1152 void (*sched_in)(struct kvm_vcpu *kvm, int cpu); 1153 1154 /* 1155 * Arch-specific dirty logging hooks. These hooks are only supposed to 1156 * be valid if the specific arch has hardware-accelerated dirty logging 1157 * mechanism. Currently only for PML on VMX. 1158 * 1159 * - slot_enable_log_dirty: 1160 * called when enabling log dirty mode for the slot. 1161 * - slot_disable_log_dirty: 1162 * called when disabling log dirty mode for the slot. 1163 * also called when slot is created with log dirty disabled. 1164 * - flush_log_dirty: 1165 * called before reporting dirty_bitmap to userspace. 1166 * - enable_log_dirty_pt_masked: 1167 * called when reenabling log dirty for the GFNs in the mask after 1168 * corresponding bits are cleared in slot->dirty_bitmap. 1169 */ 1170 void (*slot_enable_log_dirty)(struct kvm *kvm, 1171 struct kvm_memory_slot *slot); 1172 void (*slot_disable_log_dirty)(struct kvm *kvm, 1173 struct kvm_memory_slot *slot); 1174 void (*flush_log_dirty)(struct kvm *kvm); 1175 void (*enable_log_dirty_pt_masked)(struct kvm *kvm, 1176 struct kvm_memory_slot *slot, 1177 gfn_t offset, unsigned long mask); 1178 int (*write_log_dirty)(struct kvm_vcpu *vcpu); 1179 1180 /* pmu operations of sub-arch */ 1181 const struct kvm_pmu_ops *pmu_ops; 1182 1183 /* 1184 * Architecture specific hooks for vCPU blocking due to 1185 * HLT instruction. 1186 * Returns for .pre_block(): 1187 * - 0 means continue to block the vCPU. 1188 * - 1 means we cannot block the vCPU since some event 1189 * happens during this period, such as, 'ON' bit in 1190 * posted-interrupts descriptor is set. 1191 */ 1192 int (*pre_block)(struct kvm_vcpu *vcpu); 1193 void (*post_block)(struct kvm_vcpu *vcpu); 1194 1195 void (*vcpu_blocking)(struct kvm_vcpu *vcpu); 1196 void (*vcpu_unblocking)(struct kvm_vcpu *vcpu); 1197 1198 int (*update_pi_irte)(struct kvm *kvm, unsigned int host_irq, 1199 uint32_t guest_irq, bool set); 1200 void (*apicv_post_state_restore)(struct kvm_vcpu *vcpu); 1201 bool (*dy_apicv_has_pending_interrupt)(struct kvm_vcpu *vcpu); 1202 1203 int (*set_hv_timer)(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc, 1204 bool *expired); 1205 void (*cancel_hv_timer)(struct kvm_vcpu *vcpu); 1206 1207 void (*setup_mce)(struct kvm_vcpu *vcpu); 1208 1209 int (*get_nested_state)(struct kvm_vcpu *vcpu, 1210 struct kvm_nested_state __user *user_kvm_nested_state, 1211 unsigned user_data_size); 1212 int (*set_nested_state)(struct kvm_vcpu *vcpu, 1213 struct kvm_nested_state __user *user_kvm_nested_state, 1214 struct kvm_nested_state *kvm_state); 1215 bool (*get_vmcs12_pages)(struct kvm_vcpu *vcpu); 1216 1217 int (*smi_allowed)(struct kvm_vcpu *vcpu); 1218 int (*pre_enter_smm)(struct kvm_vcpu *vcpu, char *smstate); 1219 int (*pre_leave_smm)(struct kvm_vcpu *vcpu, const char *smstate); 1220 int (*enable_smi_window)(struct kvm_vcpu *vcpu); 1221 1222 int (*mem_enc_op)(struct kvm *kvm, void __user *argp); 1223 int (*mem_enc_reg_region)(struct kvm *kvm, struct kvm_enc_region *argp); 1224 int (*mem_enc_unreg_region)(struct kvm *kvm, struct kvm_enc_region *argp); 1225 1226 int (*get_msr_feature)(struct kvm_msr_entry *entry); 1227 1228 int (*nested_enable_evmcs)(struct kvm_vcpu *vcpu, 1229 uint16_t *vmcs_version); 1230 uint16_t (*nested_get_evmcs_version)(struct kvm_vcpu *vcpu); 1231 1232 bool (*need_emulation_on_page_fault)(struct kvm_vcpu *vcpu); 1233 1234 bool (*apic_init_signal_blocked)(struct kvm_vcpu *vcpu); 1235 int (*enable_direct_tlbflush)(struct kvm_vcpu *vcpu); 1236 }; 1237 1238 struct kvm_arch_async_pf { 1239 u32 token; 1240 gfn_t gfn; 1241 unsigned long cr3; 1242 bool direct_map; 1243 }; 1244 1245 extern struct kvm_x86_ops *kvm_x86_ops; 1246 extern struct kmem_cache *x86_fpu_cache; 1247 1248 #define __KVM_HAVE_ARCH_VM_ALLOC 1249 static inline struct kvm *kvm_arch_alloc_vm(void) 1250 { 1251 return kvm_x86_ops->vm_alloc(); 1252 } 1253 1254 static inline void kvm_arch_free_vm(struct kvm *kvm) 1255 { 1256 return kvm_x86_ops->vm_free(kvm); 1257 } 1258 1259 #define __KVM_HAVE_ARCH_FLUSH_REMOTE_TLB 1260 static inline int kvm_arch_flush_remote_tlb(struct kvm *kvm) 1261 { 1262 if (kvm_x86_ops->tlb_remote_flush && 1263 !kvm_x86_ops->tlb_remote_flush(kvm)) 1264 return 0; 1265 else 1266 return -ENOTSUPP; 1267 } 1268 1269 int kvm_mmu_module_init(void); 1270 void kvm_mmu_module_exit(void); 1271 1272 void kvm_mmu_destroy(struct kvm_vcpu *vcpu); 1273 int kvm_mmu_create(struct kvm_vcpu *vcpu); 1274 void kvm_mmu_init_vm(struct kvm *kvm); 1275 void kvm_mmu_uninit_vm(struct kvm *kvm); 1276 void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask, 1277 u64 dirty_mask, u64 nx_mask, u64 x_mask, u64 p_mask, 1278 u64 acc_track_mask, u64 me_mask); 1279 1280 void kvm_mmu_reset_context(struct kvm_vcpu *vcpu); 1281 void kvm_mmu_slot_remove_write_access(struct kvm *kvm, 1282 struct kvm_memory_slot *memslot); 1283 void kvm_mmu_zap_collapsible_sptes(struct kvm *kvm, 1284 const struct kvm_memory_slot *memslot); 1285 void kvm_mmu_slot_leaf_clear_dirty(struct kvm *kvm, 1286 struct kvm_memory_slot *memslot); 1287 void kvm_mmu_slot_largepage_remove_write_access(struct kvm *kvm, 1288 struct kvm_memory_slot *memslot); 1289 void kvm_mmu_slot_set_dirty(struct kvm *kvm, 1290 struct kvm_memory_slot *memslot); 1291 void kvm_mmu_clear_dirty_pt_masked(struct kvm *kvm, 1292 struct kvm_memory_slot *slot, 1293 gfn_t gfn_offset, unsigned long mask); 1294 void kvm_mmu_zap_all(struct kvm *kvm); 1295 void kvm_mmu_invalidate_mmio_sptes(struct kvm *kvm, u64 gen); 1296 unsigned long kvm_mmu_calculate_default_mmu_pages(struct kvm *kvm); 1297 void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned long kvm_nr_mmu_pages); 1298 1299 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3); 1300 bool pdptrs_changed(struct kvm_vcpu *vcpu); 1301 1302 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa, 1303 const void *val, int bytes); 1304 1305 struct kvm_irq_mask_notifier { 1306 void (*func)(struct kvm_irq_mask_notifier *kimn, bool masked); 1307 int irq; 1308 struct hlist_node link; 1309 }; 1310 1311 void kvm_register_irq_mask_notifier(struct kvm *kvm, int irq, 1312 struct kvm_irq_mask_notifier *kimn); 1313 void kvm_unregister_irq_mask_notifier(struct kvm *kvm, int irq, 1314 struct kvm_irq_mask_notifier *kimn); 1315 void kvm_fire_mask_notifiers(struct kvm *kvm, unsigned irqchip, unsigned pin, 1316 bool mask); 1317 1318 extern bool tdp_enabled; 1319 1320 u64 vcpu_tsc_khz(struct kvm_vcpu *vcpu); 1321 1322 /* control of guest tsc rate supported? */ 1323 extern bool kvm_has_tsc_control; 1324 /* maximum supported tsc_khz for guests */ 1325 extern u32 kvm_max_guest_tsc_khz; 1326 /* number of bits of the fractional part of the TSC scaling ratio */ 1327 extern u8 kvm_tsc_scaling_ratio_frac_bits; 1328 /* maximum allowed value of TSC scaling ratio */ 1329 extern u64 kvm_max_tsc_scaling_ratio; 1330 /* 1ull << kvm_tsc_scaling_ratio_frac_bits */ 1331 extern u64 kvm_default_tsc_scaling_ratio; 1332 1333 extern u64 kvm_mce_cap_supported; 1334 1335 /* 1336 * EMULTYPE_NO_DECODE - Set when re-emulating an instruction (after completing 1337 * userspace I/O) to indicate that the emulation context 1338 * should be resued as is, i.e. skip initialization of 1339 * emulation context, instruction fetch and decode. 1340 * 1341 * EMULTYPE_TRAP_UD - Set when emulating an intercepted #UD from hardware. 1342 * Indicates that only select instructions (tagged with 1343 * EmulateOnUD) should be emulated (to minimize the emulator 1344 * attack surface). See also EMULTYPE_TRAP_UD_FORCED. 1345 * 1346 * EMULTYPE_SKIP - Set when emulating solely to skip an instruction, i.e. to 1347 * decode the instruction length. For use *only* by 1348 * kvm_x86_ops->skip_emulated_instruction() implementations. 1349 * 1350 * EMULTYPE_ALLOW_RETRY - Set when the emulator should resume the guest to 1351 * retry native execution under certain conditions. 1352 * 1353 * EMULTYPE_TRAP_UD_FORCED - Set when emulating an intercepted #UD that was 1354 * triggered by KVM's magic "force emulation" prefix, 1355 * which is opt in via module param (off by default). 1356 * Bypasses EmulateOnUD restriction despite emulating 1357 * due to an intercepted #UD (see EMULTYPE_TRAP_UD). 1358 * Used to test the full emulator from userspace. 1359 * 1360 * EMULTYPE_VMWARE_GP - Set when emulating an intercepted #GP for VMware 1361 * backdoor emulation, which is opt in via module param. 1362 * VMware backoor emulation handles select instructions 1363 * and reinjects the #GP for all other cases. 1364 */ 1365 #define EMULTYPE_NO_DECODE (1 << 0) 1366 #define EMULTYPE_TRAP_UD (1 << 1) 1367 #define EMULTYPE_SKIP (1 << 2) 1368 #define EMULTYPE_ALLOW_RETRY (1 << 3) 1369 #define EMULTYPE_TRAP_UD_FORCED (1 << 4) 1370 #define EMULTYPE_VMWARE_GP (1 << 5) 1371 int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type); 1372 int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu, 1373 void *insn, int insn_len); 1374 1375 void kvm_enable_efer_bits(u64); 1376 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer); 1377 int __kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data, bool host_initiated); 1378 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data); 1379 int kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data); 1380 int kvm_emulate_rdmsr(struct kvm_vcpu *vcpu); 1381 int kvm_emulate_wrmsr(struct kvm_vcpu *vcpu); 1382 1383 struct x86_emulate_ctxt; 1384 1385 int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in); 1386 int kvm_emulate_cpuid(struct kvm_vcpu *vcpu); 1387 int kvm_emulate_halt(struct kvm_vcpu *vcpu); 1388 int kvm_vcpu_halt(struct kvm_vcpu *vcpu); 1389 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu); 1390 1391 void kvm_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg); 1392 int kvm_load_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector, int seg); 1393 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector); 1394 1395 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index, 1396 int reason, bool has_error_code, u32 error_code); 1397 1398 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0); 1399 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3); 1400 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4); 1401 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8); 1402 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val); 1403 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val); 1404 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu); 1405 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw); 1406 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l); 1407 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr); 1408 1409 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr); 1410 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr); 1411 1412 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu); 1413 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags); 1414 bool kvm_rdpmc(struct kvm_vcpu *vcpu); 1415 1416 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr); 1417 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code); 1418 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr); 1419 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code); 1420 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault); 1421 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, 1422 gfn_t gfn, void *data, int offset, int len, 1423 u32 access); 1424 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl); 1425 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr); 1426 1427 static inline int __kvm_irq_line_state(unsigned long *irq_state, 1428 int irq_source_id, int level) 1429 { 1430 /* Logical OR for level trig interrupt */ 1431 if (level) 1432 __set_bit(irq_source_id, irq_state); 1433 else 1434 __clear_bit(irq_source_id, irq_state); 1435 1436 return !!(*irq_state); 1437 } 1438 1439 #define KVM_MMU_ROOT_CURRENT BIT(0) 1440 #define KVM_MMU_ROOT_PREVIOUS(i) BIT(1+i) 1441 #define KVM_MMU_ROOTS_ALL (~0UL) 1442 1443 int kvm_pic_set_irq(struct kvm_pic *pic, int irq, int irq_source_id, int level); 1444 void kvm_pic_clear_all(struct kvm_pic *pic, int irq_source_id); 1445 1446 void kvm_inject_nmi(struct kvm_vcpu *vcpu); 1447 1448 int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn); 1449 int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva); 1450 void __kvm_mmu_free_some_pages(struct kvm_vcpu *vcpu); 1451 int kvm_mmu_load(struct kvm_vcpu *vcpu); 1452 void kvm_mmu_unload(struct kvm_vcpu *vcpu); 1453 void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu); 1454 void kvm_mmu_free_roots(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, 1455 ulong roots_to_free); 1456 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access, 1457 struct x86_exception *exception); 1458 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, 1459 struct x86_exception *exception); 1460 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, 1461 struct x86_exception *exception); 1462 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, 1463 struct x86_exception *exception); 1464 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, 1465 struct x86_exception *exception); 1466 1467 void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu); 1468 1469 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu); 1470 1471 int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t gva, u64 error_code, 1472 void *insn, int insn_len); 1473 void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva); 1474 void kvm_mmu_invpcid_gva(struct kvm_vcpu *vcpu, gva_t gva, unsigned long pcid); 1475 void kvm_mmu_new_cr3(struct kvm_vcpu *vcpu, gpa_t new_cr3, bool skip_tlb_flush); 1476 1477 void kvm_enable_tdp(void); 1478 void kvm_disable_tdp(void); 1479 1480 static inline gpa_t translate_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access, 1481 struct x86_exception *exception) 1482 { 1483 return gpa; 1484 } 1485 1486 static inline struct kvm_mmu_page *page_header(hpa_t shadow_page) 1487 { 1488 struct page *page = pfn_to_page(shadow_page >> PAGE_SHIFT); 1489 1490 return (struct kvm_mmu_page *)page_private(page); 1491 } 1492 1493 static inline u16 kvm_read_ldt(void) 1494 { 1495 u16 ldt; 1496 asm("sldt %0" : "=g"(ldt)); 1497 return ldt; 1498 } 1499 1500 static inline void kvm_load_ldt(u16 sel) 1501 { 1502 asm("lldt %0" : : "rm"(sel)); 1503 } 1504 1505 #ifdef CONFIG_X86_64 1506 static inline unsigned long read_msr(unsigned long msr) 1507 { 1508 u64 value; 1509 1510 rdmsrl(msr, value); 1511 return value; 1512 } 1513 #endif 1514 1515 static inline u32 get_rdx_init_val(void) 1516 { 1517 return 0x600; /* P6 family */ 1518 } 1519 1520 static inline void kvm_inject_gp(struct kvm_vcpu *vcpu, u32 error_code) 1521 { 1522 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code); 1523 } 1524 1525 #define TSS_IOPB_BASE_OFFSET 0x66 1526 #define TSS_BASE_SIZE 0x68 1527 #define TSS_IOPB_SIZE (65536 / 8) 1528 #define TSS_REDIRECTION_SIZE (256 / 8) 1529 #define RMODE_TSS_SIZE \ 1530 (TSS_BASE_SIZE + TSS_REDIRECTION_SIZE + TSS_IOPB_SIZE + 1) 1531 1532 enum { 1533 TASK_SWITCH_CALL = 0, 1534 TASK_SWITCH_IRET = 1, 1535 TASK_SWITCH_JMP = 2, 1536 TASK_SWITCH_GATE = 3, 1537 }; 1538 1539 #define HF_GIF_MASK (1 << 0) 1540 #define HF_HIF_MASK (1 << 1) 1541 #define HF_VINTR_MASK (1 << 2) 1542 #define HF_NMI_MASK (1 << 3) 1543 #define HF_IRET_MASK (1 << 4) 1544 #define HF_GUEST_MASK (1 << 5) /* VCPU is in guest-mode */ 1545 #define HF_SMM_MASK (1 << 6) 1546 #define HF_SMM_INSIDE_NMI_MASK (1 << 7) 1547 1548 #define __KVM_VCPU_MULTIPLE_ADDRESS_SPACE 1549 #define KVM_ADDRESS_SPACE_NUM 2 1550 1551 #define kvm_arch_vcpu_memslots_id(vcpu) ((vcpu)->arch.hflags & HF_SMM_MASK ? 1 : 0) 1552 #define kvm_memslots_for_spte_role(kvm, role) __kvm_memslots(kvm, (role).smm) 1553 1554 asmlinkage void kvm_spurious_fault(void); 1555 1556 /* 1557 * Hardware virtualization extension instructions may fault if a 1558 * reboot turns off virtualization while processes are running. 1559 * Usually after catching the fault we just panic; during reboot 1560 * instead the instruction is ignored. 1561 */ 1562 #define __kvm_handle_fault_on_reboot(insn) \ 1563 "666: \n\t" \ 1564 insn "\n\t" \ 1565 "jmp 668f \n\t" \ 1566 "667: \n\t" \ 1567 "call kvm_spurious_fault \n\t" \ 1568 "668: \n\t" \ 1569 _ASM_EXTABLE(666b, 667b) 1570 1571 #define KVM_ARCH_WANT_MMU_NOTIFIER 1572 int kvm_unmap_hva_range(struct kvm *kvm, unsigned long start, unsigned long end); 1573 int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end); 1574 int kvm_test_age_hva(struct kvm *kvm, unsigned long hva); 1575 int kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte); 1576 int kvm_cpu_has_injectable_intr(struct kvm_vcpu *v); 1577 int kvm_cpu_has_interrupt(struct kvm_vcpu *vcpu); 1578 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu); 1579 int kvm_cpu_get_interrupt(struct kvm_vcpu *v); 1580 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event); 1581 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu); 1582 1583 int kvm_pv_send_ipi(struct kvm *kvm, unsigned long ipi_bitmap_low, 1584 unsigned long ipi_bitmap_high, u32 min, 1585 unsigned long icr, int op_64_bit); 1586 1587 void kvm_define_shared_msr(unsigned index, u32 msr); 1588 int kvm_set_shared_msr(unsigned index, u64 val, u64 mask); 1589 1590 u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc); 1591 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc); 1592 1593 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu); 1594 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip); 1595 1596 void kvm_make_mclock_inprogress_request(struct kvm *kvm); 1597 void kvm_make_scan_ioapic_request(struct kvm *kvm); 1598 void kvm_make_scan_ioapic_request_mask(struct kvm *kvm, 1599 unsigned long *vcpu_bitmap); 1600 1601 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu, 1602 struct kvm_async_pf *work); 1603 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu, 1604 struct kvm_async_pf *work); 1605 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, 1606 struct kvm_async_pf *work); 1607 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu); 1608 extern bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn); 1609 1610 int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu); 1611 int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err); 1612 void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu); 1613 1614 int kvm_is_in_guest(void); 1615 1616 int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size); 1617 int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size); 1618 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu); 1619 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu); 1620 1621 bool kvm_intr_is_single_vcpu(struct kvm *kvm, struct kvm_lapic_irq *irq, 1622 struct kvm_vcpu **dest_vcpu); 1623 1624 void kvm_set_msi_irq(struct kvm *kvm, struct kvm_kernel_irq_routing_entry *e, 1625 struct kvm_lapic_irq *irq); 1626 1627 static inline bool kvm_irq_is_postable(struct kvm_lapic_irq *irq) 1628 { 1629 /* We can only post Fixed and LowPrio IRQs */ 1630 return (irq->delivery_mode == dest_Fixed || 1631 irq->delivery_mode == dest_LowestPrio); 1632 } 1633 1634 static inline void kvm_arch_vcpu_blocking(struct kvm_vcpu *vcpu) 1635 { 1636 if (kvm_x86_ops->vcpu_blocking) 1637 kvm_x86_ops->vcpu_blocking(vcpu); 1638 } 1639 1640 static inline void kvm_arch_vcpu_unblocking(struct kvm_vcpu *vcpu) 1641 { 1642 if (kvm_x86_ops->vcpu_unblocking) 1643 kvm_x86_ops->vcpu_unblocking(vcpu); 1644 } 1645 1646 static inline void kvm_arch_vcpu_block_finish(struct kvm_vcpu *vcpu) {} 1647 1648 static inline int kvm_cpu_get_apicid(int mps_cpu) 1649 { 1650 #ifdef CONFIG_X86_LOCAL_APIC 1651 return default_cpu_present_to_apicid(mps_cpu); 1652 #else 1653 WARN_ON_ONCE(1); 1654 return BAD_APICID; 1655 #endif 1656 } 1657 1658 #define put_smstate(type, buf, offset, val) \ 1659 *(type *)((buf) + (offset) - 0x7e00) = val 1660 1661 #define GET_SMSTATE(type, buf, offset) \ 1662 (*(type *)((buf) + (offset) - 0x7e00)) 1663 1664 #endif /* _ASM_X86_KVM_HOST_H */ 1665