1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Kernel-based Virtual Machine driver for Linux 4 * 5 * This header defines architecture specific interfaces, x86 version 6 */ 7 8 #ifndef _ASM_X86_KVM_HOST_H 9 #define _ASM_X86_KVM_HOST_H 10 11 #include <linux/types.h> 12 #include <linux/mm.h> 13 #include <linux/mmu_notifier.h> 14 #include <linux/tracepoint.h> 15 #include <linux/cpumask.h> 16 #include <linux/irq_work.h> 17 #include <linux/irq.h> 18 19 #include <linux/kvm.h> 20 #include <linux/kvm_para.h> 21 #include <linux/kvm_types.h> 22 #include <linux/perf_event.h> 23 #include <linux/pvclock_gtod.h> 24 #include <linux/clocksource.h> 25 #include <linux/irqbypass.h> 26 #include <linux/hyperv.h> 27 28 #include <asm/apic.h> 29 #include <asm/pvclock-abi.h> 30 #include <asm/desc.h> 31 #include <asm/mtrr.h> 32 #include <asm/msr-index.h> 33 #include <asm/asm.h> 34 #include <asm/kvm_page_track.h> 35 #include <asm/kvm_vcpu_regs.h> 36 #include <asm/hyperv-tlfs.h> 37 38 #define __KVM_HAVE_ARCH_VCPU_DEBUGFS 39 40 #define KVM_MAX_VCPUS 288 41 #define KVM_SOFT_MAX_VCPUS 240 42 #define KVM_MAX_VCPU_ID 1023 43 #define KVM_USER_MEM_SLOTS 509 44 /* memory slots that are not exposed to userspace */ 45 #define KVM_PRIVATE_MEM_SLOTS 3 46 #define KVM_MEM_SLOTS_NUM (KVM_USER_MEM_SLOTS + KVM_PRIVATE_MEM_SLOTS) 47 48 #define KVM_HALT_POLL_NS_DEFAULT 200000 49 50 #define KVM_IRQCHIP_NUM_PINS KVM_IOAPIC_NUM_PINS 51 52 #define KVM_DIRTY_LOG_MANUAL_CAPS (KVM_DIRTY_LOG_MANUAL_PROTECT_ENABLE | \ 53 KVM_DIRTY_LOG_INITIALLY_SET) 54 55 /* x86-specific vcpu->requests bit members */ 56 #define KVM_REQ_MIGRATE_TIMER KVM_ARCH_REQ(0) 57 #define KVM_REQ_REPORT_TPR_ACCESS KVM_ARCH_REQ(1) 58 #define KVM_REQ_TRIPLE_FAULT KVM_ARCH_REQ(2) 59 #define KVM_REQ_MMU_SYNC KVM_ARCH_REQ(3) 60 #define KVM_REQ_CLOCK_UPDATE KVM_ARCH_REQ(4) 61 #define KVM_REQ_LOAD_MMU_PGD KVM_ARCH_REQ(5) 62 #define KVM_REQ_EVENT KVM_ARCH_REQ(6) 63 #define KVM_REQ_APF_HALT KVM_ARCH_REQ(7) 64 #define KVM_REQ_STEAL_UPDATE KVM_ARCH_REQ(8) 65 #define KVM_REQ_NMI KVM_ARCH_REQ(9) 66 #define KVM_REQ_PMU KVM_ARCH_REQ(10) 67 #define KVM_REQ_PMI KVM_ARCH_REQ(11) 68 #define KVM_REQ_SMI KVM_ARCH_REQ(12) 69 #define KVM_REQ_MASTERCLOCK_UPDATE KVM_ARCH_REQ(13) 70 #define KVM_REQ_MCLOCK_INPROGRESS \ 71 KVM_ARCH_REQ_FLAGS(14, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP) 72 #define KVM_REQ_SCAN_IOAPIC \ 73 KVM_ARCH_REQ_FLAGS(15, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP) 74 #define KVM_REQ_GLOBAL_CLOCK_UPDATE KVM_ARCH_REQ(16) 75 #define KVM_REQ_APIC_PAGE_RELOAD \ 76 KVM_ARCH_REQ_FLAGS(17, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP) 77 #define KVM_REQ_HV_CRASH KVM_ARCH_REQ(18) 78 #define KVM_REQ_IOAPIC_EOI_EXIT KVM_ARCH_REQ(19) 79 #define KVM_REQ_HV_RESET KVM_ARCH_REQ(20) 80 #define KVM_REQ_HV_EXIT KVM_ARCH_REQ(21) 81 #define KVM_REQ_HV_STIMER KVM_ARCH_REQ(22) 82 #define KVM_REQ_LOAD_EOI_EXITMAP KVM_ARCH_REQ(23) 83 #define KVM_REQ_GET_NESTED_STATE_PAGES KVM_ARCH_REQ(24) 84 #define KVM_REQ_APICV_UPDATE \ 85 KVM_ARCH_REQ_FLAGS(25, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP) 86 #define KVM_REQ_TLB_FLUSH_CURRENT KVM_ARCH_REQ(26) 87 #define KVM_REQ_HV_TLB_FLUSH \ 88 KVM_ARCH_REQ_FLAGS(27, KVM_REQUEST_NO_WAKEUP) 89 #define KVM_REQ_APF_READY KVM_ARCH_REQ(28) 90 #define KVM_REQ_MSR_FILTER_CHANGED KVM_ARCH_REQ(29) 91 92 #define CR0_RESERVED_BITS \ 93 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \ 94 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \ 95 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG)) 96 97 #define CR4_RESERVED_BITS \ 98 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\ 99 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \ 100 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR | X86_CR4_PCIDE \ 101 | X86_CR4_OSXSAVE | X86_CR4_SMEP | X86_CR4_FSGSBASE \ 102 | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_VMXE \ 103 | X86_CR4_SMAP | X86_CR4_PKE | X86_CR4_UMIP)) 104 105 #define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR) 106 107 108 109 #define INVALID_PAGE (~(hpa_t)0) 110 #define VALID_PAGE(x) ((x) != INVALID_PAGE) 111 112 #define UNMAPPED_GVA (~(gpa_t)0) 113 114 /* KVM Hugepage definitions for x86 */ 115 #define KVM_MAX_HUGEPAGE_LEVEL PG_LEVEL_1G 116 #define KVM_NR_PAGE_SIZES (KVM_MAX_HUGEPAGE_LEVEL - PG_LEVEL_4K + 1) 117 #define KVM_HPAGE_GFN_SHIFT(x) (((x) - 1) * 9) 118 #define KVM_HPAGE_SHIFT(x) (PAGE_SHIFT + KVM_HPAGE_GFN_SHIFT(x)) 119 #define KVM_HPAGE_SIZE(x) (1UL << KVM_HPAGE_SHIFT(x)) 120 #define KVM_HPAGE_MASK(x) (~(KVM_HPAGE_SIZE(x) - 1)) 121 #define KVM_PAGES_PER_HPAGE(x) (KVM_HPAGE_SIZE(x) / PAGE_SIZE) 122 123 static inline gfn_t gfn_to_index(gfn_t gfn, gfn_t base_gfn, int level) 124 { 125 /* KVM_HPAGE_GFN_SHIFT(PG_LEVEL_4K) must be 0. */ 126 return (gfn >> KVM_HPAGE_GFN_SHIFT(level)) - 127 (base_gfn >> KVM_HPAGE_GFN_SHIFT(level)); 128 } 129 130 #define KVM_PERMILLE_MMU_PAGES 20 131 #define KVM_MIN_ALLOC_MMU_PAGES 64UL 132 #define KVM_MMU_HASH_SHIFT 12 133 #define KVM_NUM_MMU_PAGES (1 << KVM_MMU_HASH_SHIFT) 134 #define KVM_MIN_FREE_MMU_PAGES 5 135 #define KVM_REFILL_PAGES 25 136 #define KVM_MAX_CPUID_ENTRIES 256 137 #define KVM_NR_FIXED_MTRR_REGION 88 138 #define KVM_NR_VAR_MTRR 8 139 140 #define ASYNC_PF_PER_VCPU 64 141 142 enum kvm_reg { 143 VCPU_REGS_RAX = __VCPU_REGS_RAX, 144 VCPU_REGS_RCX = __VCPU_REGS_RCX, 145 VCPU_REGS_RDX = __VCPU_REGS_RDX, 146 VCPU_REGS_RBX = __VCPU_REGS_RBX, 147 VCPU_REGS_RSP = __VCPU_REGS_RSP, 148 VCPU_REGS_RBP = __VCPU_REGS_RBP, 149 VCPU_REGS_RSI = __VCPU_REGS_RSI, 150 VCPU_REGS_RDI = __VCPU_REGS_RDI, 151 #ifdef CONFIG_X86_64 152 VCPU_REGS_R8 = __VCPU_REGS_R8, 153 VCPU_REGS_R9 = __VCPU_REGS_R9, 154 VCPU_REGS_R10 = __VCPU_REGS_R10, 155 VCPU_REGS_R11 = __VCPU_REGS_R11, 156 VCPU_REGS_R12 = __VCPU_REGS_R12, 157 VCPU_REGS_R13 = __VCPU_REGS_R13, 158 VCPU_REGS_R14 = __VCPU_REGS_R14, 159 VCPU_REGS_R15 = __VCPU_REGS_R15, 160 #endif 161 VCPU_REGS_RIP, 162 NR_VCPU_REGS, 163 164 VCPU_EXREG_PDPTR = NR_VCPU_REGS, 165 VCPU_EXREG_CR0, 166 VCPU_EXREG_CR3, 167 VCPU_EXREG_CR4, 168 VCPU_EXREG_RFLAGS, 169 VCPU_EXREG_SEGMENTS, 170 VCPU_EXREG_EXIT_INFO_1, 171 VCPU_EXREG_EXIT_INFO_2, 172 }; 173 174 enum { 175 VCPU_SREG_ES, 176 VCPU_SREG_CS, 177 VCPU_SREG_SS, 178 VCPU_SREG_DS, 179 VCPU_SREG_FS, 180 VCPU_SREG_GS, 181 VCPU_SREG_TR, 182 VCPU_SREG_LDTR, 183 }; 184 185 enum exit_fastpath_completion { 186 EXIT_FASTPATH_NONE, 187 EXIT_FASTPATH_REENTER_GUEST, 188 EXIT_FASTPATH_EXIT_HANDLED, 189 }; 190 typedef enum exit_fastpath_completion fastpath_t; 191 192 struct x86_emulate_ctxt; 193 struct x86_exception; 194 enum x86_intercept; 195 enum x86_intercept_stage; 196 197 #define KVM_NR_DB_REGS 4 198 199 #define DR6_BD (1 << 13) 200 #define DR6_BS (1 << 14) 201 #define DR6_BT (1 << 15) 202 #define DR6_RTM (1 << 16) 203 #define DR6_FIXED_1 0xfffe0ff0 204 #define DR6_INIT 0xffff0ff0 205 #define DR6_VOLATILE 0x0001e00f 206 207 #define DR7_BP_EN_MASK 0x000000ff 208 #define DR7_GE (1 << 9) 209 #define DR7_GD (1 << 13) 210 #define DR7_FIXED_1 0x00000400 211 #define DR7_VOLATILE 0xffff2bff 212 213 #define PFERR_PRESENT_BIT 0 214 #define PFERR_WRITE_BIT 1 215 #define PFERR_USER_BIT 2 216 #define PFERR_RSVD_BIT 3 217 #define PFERR_FETCH_BIT 4 218 #define PFERR_PK_BIT 5 219 #define PFERR_GUEST_FINAL_BIT 32 220 #define PFERR_GUEST_PAGE_BIT 33 221 222 #define PFERR_PRESENT_MASK (1U << PFERR_PRESENT_BIT) 223 #define PFERR_WRITE_MASK (1U << PFERR_WRITE_BIT) 224 #define PFERR_USER_MASK (1U << PFERR_USER_BIT) 225 #define PFERR_RSVD_MASK (1U << PFERR_RSVD_BIT) 226 #define PFERR_FETCH_MASK (1U << PFERR_FETCH_BIT) 227 #define PFERR_PK_MASK (1U << PFERR_PK_BIT) 228 #define PFERR_GUEST_FINAL_MASK (1ULL << PFERR_GUEST_FINAL_BIT) 229 #define PFERR_GUEST_PAGE_MASK (1ULL << PFERR_GUEST_PAGE_BIT) 230 231 #define PFERR_NESTED_GUEST_PAGE (PFERR_GUEST_PAGE_MASK | \ 232 PFERR_WRITE_MASK | \ 233 PFERR_PRESENT_MASK) 234 235 /* apic attention bits */ 236 #define KVM_APIC_CHECK_VAPIC 0 237 /* 238 * The following bit is set with PV-EOI, unset on EOI. 239 * We detect PV-EOI changes by guest by comparing 240 * this bit with PV-EOI in guest memory. 241 * See the implementation in apic_update_pv_eoi. 242 */ 243 #define KVM_APIC_PV_EOI_PENDING 1 244 245 struct kvm_kernel_irq_routing_entry; 246 247 /* 248 * the pages used as guest page table on soft mmu are tracked by 249 * kvm_memory_slot.arch.gfn_track which is 16 bits, so the role bits used 250 * by indirect shadow page can not be more than 15 bits. 251 * 252 * Currently, we used 14 bits that are @level, @gpte_is_8_bytes, @quadrant, @access, 253 * @nxe, @cr0_wp, @smep_andnot_wp and @smap_andnot_wp. 254 */ 255 union kvm_mmu_page_role { 256 u32 word; 257 struct { 258 unsigned level:4; 259 unsigned gpte_is_8_bytes:1; 260 unsigned quadrant:2; 261 unsigned direct:1; 262 unsigned access:3; 263 unsigned invalid:1; 264 unsigned nxe:1; 265 unsigned cr0_wp:1; 266 unsigned smep_andnot_wp:1; 267 unsigned smap_andnot_wp:1; 268 unsigned ad_disabled:1; 269 unsigned guest_mode:1; 270 unsigned :6; 271 272 /* 273 * This is left at the top of the word so that 274 * kvm_memslots_for_spte_role can extract it with a 275 * simple shift. While there is room, give it a whole 276 * byte so it is also faster to load it from memory. 277 */ 278 unsigned smm:8; 279 }; 280 }; 281 282 union kvm_mmu_extended_role { 283 /* 284 * This structure complements kvm_mmu_page_role caching everything needed for 285 * MMU configuration. If nothing in both these structures changed, MMU 286 * re-configuration can be skipped. @valid bit is set on first usage so we don't 287 * treat all-zero structure as valid data. 288 */ 289 u32 word; 290 struct { 291 unsigned int valid:1; 292 unsigned int execonly:1; 293 unsigned int cr0_pg:1; 294 unsigned int cr4_pae:1; 295 unsigned int cr4_pse:1; 296 unsigned int cr4_pke:1; 297 unsigned int cr4_smap:1; 298 unsigned int cr4_smep:1; 299 unsigned int maxphyaddr:6; 300 }; 301 }; 302 303 union kvm_mmu_role { 304 u64 as_u64; 305 struct { 306 union kvm_mmu_page_role base; 307 union kvm_mmu_extended_role ext; 308 }; 309 }; 310 311 struct kvm_rmap_head { 312 unsigned long val; 313 }; 314 315 struct kvm_pio_request { 316 unsigned long linear_rip; 317 unsigned long count; 318 int in; 319 int port; 320 int size; 321 }; 322 323 #define PT64_ROOT_MAX_LEVEL 5 324 325 struct rsvd_bits_validate { 326 u64 rsvd_bits_mask[2][PT64_ROOT_MAX_LEVEL]; 327 u64 bad_mt_xwr; 328 }; 329 330 struct kvm_mmu_root_info { 331 gpa_t pgd; 332 hpa_t hpa; 333 }; 334 335 #define KVM_MMU_ROOT_INFO_INVALID \ 336 ((struct kvm_mmu_root_info) { .pgd = INVALID_PAGE, .hpa = INVALID_PAGE }) 337 338 #define KVM_MMU_NUM_PREV_ROOTS 3 339 340 struct kvm_mmu_page; 341 342 /* 343 * x86 supports 4 paging modes (5-level 64-bit, 4-level 64-bit, 3-level 32-bit, 344 * and 2-level 32-bit). The kvm_mmu structure abstracts the details of the 345 * current mmu mode. 346 */ 347 struct kvm_mmu { 348 unsigned long (*get_guest_pgd)(struct kvm_vcpu *vcpu); 349 u64 (*get_pdptr)(struct kvm_vcpu *vcpu, int index); 350 int (*page_fault)(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, u32 err, 351 bool prefault); 352 void (*inject_page_fault)(struct kvm_vcpu *vcpu, 353 struct x86_exception *fault); 354 gpa_t (*gva_to_gpa)(struct kvm_vcpu *vcpu, gpa_t gva_or_gpa, 355 u32 access, struct x86_exception *exception); 356 gpa_t (*translate_gpa)(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access, 357 struct x86_exception *exception); 358 int (*sync_page)(struct kvm_vcpu *vcpu, 359 struct kvm_mmu_page *sp); 360 void (*invlpg)(struct kvm_vcpu *vcpu, gva_t gva, hpa_t root_hpa); 361 void (*update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, 362 u64 *spte, const void *pte); 363 hpa_t root_hpa; 364 gpa_t root_pgd; 365 union kvm_mmu_role mmu_role; 366 u8 root_level; 367 u8 shadow_root_level; 368 u8 ept_ad; 369 bool direct_map; 370 struct kvm_mmu_root_info prev_roots[KVM_MMU_NUM_PREV_ROOTS]; 371 372 /* 373 * Bitmap; bit set = permission fault 374 * Byte index: page fault error code [4:1] 375 * Bit index: pte permissions in ACC_* format 376 */ 377 u8 permissions[16]; 378 379 /* 380 * The pkru_mask indicates if protection key checks are needed. It 381 * consists of 16 domains indexed by page fault error code bits [4:1], 382 * with PFEC.RSVD replaced by ACC_USER_MASK from the page tables. 383 * Each domain has 2 bits which are ANDed with AD and WD from PKRU. 384 */ 385 u32 pkru_mask; 386 387 u64 *pae_root; 388 u64 *lm_root; 389 390 /* 391 * check zero bits on shadow page table entries, these 392 * bits include not only hardware reserved bits but also 393 * the bits spte never used. 394 */ 395 struct rsvd_bits_validate shadow_zero_check; 396 397 struct rsvd_bits_validate guest_rsvd_check; 398 399 /* Can have large pages at levels 2..last_nonleaf_level-1. */ 400 u8 last_nonleaf_level; 401 402 bool nx; 403 404 u64 pdptrs[4]; /* pae */ 405 }; 406 407 struct kvm_tlb_range { 408 u64 start_gfn; 409 u64 pages; 410 }; 411 412 enum pmc_type { 413 KVM_PMC_GP = 0, 414 KVM_PMC_FIXED, 415 }; 416 417 struct kvm_pmc { 418 enum pmc_type type; 419 u8 idx; 420 u64 counter; 421 u64 eventsel; 422 struct perf_event *perf_event; 423 struct kvm_vcpu *vcpu; 424 /* 425 * eventsel value for general purpose counters, 426 * ctrl value for fixed counters. 427 */ 428 u64 current_config; 429 }; 430 431 struct kvm_pmu { 432 unsigned nr_arch_gp_counters; 433 unsigned nr_arch_fixed_counters; 434 unsigned available_event_types; 435 u64 fixed_ctr_ctrl; 436 u64 global_ctrl; 437 u64 global_status; 438 u64 global_ovf_ctrl; 439 u64 counter_bitmask[2]; 440 u64 global_ctrl_mask; 441 u64 global_ovf_ctrl_mask; 442 u64 reserved_bits; 443 u8 version; 444 struct kvm_pmc gp_counters[INTEL_PMC_MAX_GENERIC]; 445 struct kvm_pmc fixed_counters[INTEL_PMC_MAX_FIXED]; 446 struct irq_work irq_work; 447 DECLARE_BITMAP(reprogram_pmi, X86_PMC_IDX_MAX); 448 DECLARE_BITMAP(all_valid_pmc_idx, X86_PMC_IDX_MAX); 449 DECLARE_BITMAP(pmc_in_use, X86_PMC_IDX_MAX); 450 451 /* 452 * The gate to release perf_events not marked in 453 * pmc_in_use only once in a vcpu time slice. 454 */ 455 bool need_cleanup; 456 457 /* 458 * The total number of programmed perf_events and it helps to avoid 459 * redundant check before cleanup if guest don't use vPMU at all. 460 */ 461 u8 event_count; 462 }; 463 464 struct kvm_pmu_ops; 465 466 enum { 467 KVM_DEBUGREG_BP_ENABLED = 1, 468 KVM_DEBUGREG_WONT_EXIT = 2, 469 KVM_DEBUGREG_RELOAD = 4, 470 }; 471 472 struct kvm_mtrr_range { 473 u64 base; 474 u64 mask; 475 struct list_head node; 476 }; 477 478 struct kvm_mtrr { 479 struct kvm_mtrr_range var_ranges[KVM_NR_VAR_MTRR]; 480 mtrr_type fixed_ranges[KVM_NR_FIXED_MTRR_REGION]; 481 u64 deftype; 482 483 struct list_head head; 484 }; 485 486 /* Hyper-V SynIC timer */ 487 struct kvm_vcpu_hv_stimer { 488 struct hrtimer timer; 489 int index; 490 union hv_stimer_config config; 491 u64 count; 492 u64 exp_time; 493 struct hv_message msg; 494 bool msg_pending; 495 }; 496 497 /* Hyper-V synthetic interrupt controller (SynIC)*/ 498 struct kvm_vcpu_hv_synic { 499 u64 version; 500 u64 control; 501 u64 msg_page; 502 u64 evt_page; 503 atomic64_t sint[HV_SYNIC_SINT_COUNT]; 504 atomic_t sint_to_gsi[HV_SYNIC_SINT_COUNT]; 505 DECLARE_BITMAP(auto_eoi_bitmap, 256); 506 DECLARE_BITMAP(vec_bitmap, 256); 507 bool active; 508 bool dont_zero_synic_pages; 509 }; 510 511 /* Hyper-V per vcpu emulation context */ 512 struct kvm_vcpu_hv { 513 u32 vp_index; 514 u64 hv_vapic; 515 s64 runtime_offset; 516 struct kvm_vcpu_hv_synic synic; 517 struct kvm_hyperv_exit exit; 518 struct kvm_vcpu_hv_stimer stimer[HV_SYNIC_STIMER_COUNT]; 519 DECLARE_BITMAP(stimer_pending_bitmap, HV_SYNIC_STIMER_COUNT); 520 cpumask_t tlb_flush; 521 }; 522 523 struct kvm_vcpu_arch { 524 /* 525 * rip and regs accesses must go through 526 * kvm_{register,rip}_{read,write} functions. 527 */ 528 unsigned long regs[NR_VCPU_REGS]; 529 u32 regs_avail; 530 u32 regs_dirty; 531 532 unsigned long cr0; 533 unsigned long cr0_guest_owned_bits; 534 unsigned long cr2; 535 unsigned long cr3; 536 unsigned long cr4; 537 unsigned long cr4_guest_owned_bits; 538 unsigned long cr4_guest_rsvd_bits; 539 unsigned long cr8; 540 u32 host_pkru; 541 u32 pkru; 542 u32 hflags; 543 u64 efer; 544 u64 apic_base; 545 struct kvm_lapic *apic; /* kernel irqchip context */ 546 bool apicv_active; 547 bool load_eoi_exitmap_pending; 548 DECLARE_BITMAP(ioapic_handled_vectors, 256); 549 unsigned long apic_attention; 550 int32_t apic_arb_prio; 551 int mp_state; 552 u64 ia32_misc_enable_msr; 553 u64 smbase; 554 u64 smi_count; 555 bool tpr_access_reporting; 556 bool xsaves_enabled; 557 u64 ia32_xss; 558 u64 microcode_version; 559 u64 arch_capabilities; 560 u64 perf_capabilities; 561 562 /* 563 * Paging state of the vcpu 564 * 565 * If the vcpu runs in guest mode with two level paging this still saves 566 * the paging mode of the l1 guest. This context is always used to 567 * handle faults. 568 */ 569 struct kvm_mmu *mmu; 570 571 /* Non-nested MMU for L1 */ 572 struct kvm_mmu root_mmu; 573 574 /* L1 MMU when running nested */ 575 struct kvm_mmu guest_mmu; 576 577 /* 578 * Paging state of an L2 guest (used for nested npt) 579 * 580 * This context will save all necessary information to walk page tables 581 * of an L2 guest. This context is only initialized for page table 582 * walking and not for faulting since we never handle l2 page faults on 583 * the host. 584 */ 585 struct kvm_mmu nested_mmu; 586 587 /* 588 * Pointer to the mmu context currently used for 589 * gva_to_gpa translations. 590 */ 591 struct kvm_mmu *walk_mmu; 592 593 struct kvm_mmu_memory_cache mmu_pte_list_desc_cache; 594 struct kvm_mmu_memory_cache mmu_shadow_page_cache; 595 struct kvm_mmu_memory_cache mmu_gfn_array_cache; 596 struct kvm_mmu_memory_cache mmu_page_header_cache; 597 598 /* 599 * QEMU userspace and the guest each have their own FPU state. 600 * In vcpu_run, we switch between the user and guest FPU contexts. 601 * While running a VCPU, the VCPU thread will have the guest FPU 602 * context. 603 * 604 * Note that while the PKRU state lives inside the fpu registers, 605 * it is switched out separately at VMENTER and VMEXIT time. The 606 * "guest_fpu" state here contains the guest FPU context, with the 607 * host PRKU bits. 608 */ 609 struct fpu *user_fpu; 610 struct fpu *guest_fpu; 611 612 u64 xcr0; 613 u64 guest_supported_xcr0; 614 615 struct kvm_pio_request pio; 616 void *pio_data; 617 void *guest_ins_data; 618 619 u8 event_exit_inst_len; 620 621 struct kvm_queued_exception { 622 bool pending; 623 bool injected; 624 bool has_error_code; 625 u8 nr; 626 u32 error_code; 627 unsigned long payload; 628 bool has_payload; 629 u8 nested_apf; 630 } exception; 631 632 struct kvm_queued_interrupt { 633 bool injected; 634 bool soft; 635 u8 nr; 636 } interrupt; 637 638 int halt_request; /* real mode on Intel only */ 639 640 int cpuid_nent; 641 struct kvm_cpuid_entry2 *cpuid_entries; 642 643 unsigned long cr3_lm_rsvd_bits; 644 int maxphyaddr; 645 int max_tdp_level; 646 647 /* emulate context */ 648 649 struct x86_emulate_ctxt *emulate_ctxt; 650 bool emulate_regs_need_sync_to_vcpu; 651 bool emulate_regs_need_sync_from_vcpu; 652 int (*complete_userspace_io)(struct kvm_vcpu *vcpu); 653 654 gpa_t time; 655 struct pvclock_vcpu_time_info hv_clock; 656 unsigned int hw_tsc_khz; 657 struct gfn_to_hva_cache pv_time; 658 bool pv_time_enabled; 659 /* set guest stopped flag in pvclock flags field */ 660 bool pvclock_set_guest_stopped_request; 661 662 struct { 663 u8 preempted; 664 u64 msr_val; 665 u64 last_steal; 666 struct gfn_to_pfn_cache cache; 667 } st; 668 669 u64 l1_tsc_offset; 670 u64 tsc_offset; 671 u64 last_guest_tsc; 672 u64 last_host_tsc; 673 u64 tsc_offset_adjustment; 674 u64 this_tsc_nsec; 675 u64 this_tsc_write; 676 u64 this_tsc_generation; 677 bool tsc_catchup; 678 bool tsc_always_catchup; 679 s8 virtual_tsc_shift; 680 u32 virtual_tsc_mult; 681 u32 virtual_tsc_khz; 682 s64 ia32_tsc_adjust_msr; 683 u64 msr_ia32_power_ctl; 684 u64 tsc_scaling_ratio; 685 686 atomic_t nmi_queued; /* unprocessed asynchronous NMIs */ 687 unsigned nmi_pending; /* NMI queued after currently running handler */ 688 bool nmi_injected; /* Trying to inject an NMI this entry */ 689 bool smi_pending; /* SMI queued after currently running handler */ 690 691 struct kvm_mtrr mtrr_state; 692 u64 pat; 693 694 unsigned switch_db_regs; 695 unsigned long db[KVM_NR_DB_REGS]; 696 unsigned long dr6; 697 unsigned long dr7; 698 unsigned long eff_db[KVM_NR_DB_REGS]; 699 unsigned long guest_debug_dr7; 700 u64 msr_platform_info; 701 u64 msr_misc_features_enables; 702 703 u64 mcg_cap; 704 u64 mcg_status; 705 u64 mcg_ctl; 706 u64 mcg_ext_ctl; 707 u64 *mce_banks; 708 709 /* Cache MMIO info */ 710 u64 mmio_gva; 711 unsigned mmio_access; 712 gfn_t mmio_gfn; 713 u64 mmio_gen; 714 715 struct kvm_pmu pmu; 716 717 /* used for guest single stepping over the given code position */ 718 unsigned long singlestep_rip; 719 720 struct kvm_vcpu_hv hyperv; 721 722 cpumask_var_t wbinvd_dirty_mask; 723 724 unsigned long last_retry_eip; 725 unsigned long last_retry_addr; 726 727 struct { 728 bool halted; 729 gfn_t gfns[ASYNC_PF_PER_VCPU]; 730 struct gfn_to_hva_cache data; 731 u64 msr_en_val; /* MSR_KVM_ASYNC_PF_EN */ 732 u64 msr_int_val; /* MSR_KVM_ASYNC_PF_INT */ 733 u16 vec; 734 u32 id; 735 bool send_user_only; 736 u32 host_apf_flags; 737 unsigned long nested_apf_token; 738 bool delivery_as_pf_vmexit; 739 bool pageready_pending; 740 } apf; 741 742 /* OSVW MSRs (AMD only) */ 743 struct { 744 u64 length; 745 u64 status; 746 } osvw; 747 748 struct { 749 u64 msr_val; 750 struct gfn_to_hva_cache data; 751 } pv_eoi; 752 753 u64 msr_kvm_poll_control; 754 755 /* 756 * Indicates the guest is trying to write a gfn that contains one or 757 * more of the PTEs used to translate the write itself, i.e. the access 758 * is changing its own translation in the guest page tables. KVM exits 759 * to userspace if emulation of the faulting instruction fails and this 760 * flag is set, as KVM cannot make forward progress. 761 * 762 * If emulation fails for a write to guest page tables, KVM unprotects 763 * (zaps) the shadow page for the target gfn and resumes the guest to 764 * retry the non-emulatable instruction (on hardware). Unprotecting the 765 * gfn doesn't allow forward progress for a self-changing access because 766 * doing so also zaps the translation for the gfn, i.e. retrying the 767 * instruction will hit a !PRESENT fault, which results in a new shadow 768 * page and sends KVM back to square one. 769 */ 770 bool write_fault_to_shadow_pgtable; 771 772 /* set at EPT violation at this point */ 773 unsigned long exit_qualification; 774 775 /* pv related host specific info */ 776 struct { 777 bool pv_unhalted; 778 } pv; 779 780 int pending_ioapic_eoi; 781 int pending_external_vector; 782 783 /* be preempted when it's in kernel-mode(cpl=0) */ 784 bool preempted_in_kernel; 785 786 /* Flush the L1 Data cache for L1TF mitigation on VMENTER */ 787 bool l1tf_flush_l1d; 788 789 /* Host CPU on which VM-entry was most recently attempted */ 790 unsigned int last_vmentry_cpu; 791 792 /* AMD MSRC001_0015 Hardware Configuration */ 793 u64 msr_hwcr; 794 795 /* pv related cpuid info */ 796 struct { 797 /* 798 * value of the eax register in the KVM_CPUID_FEATURES CPUID 799 * leaf. 800 */ 801 u32 features; 802 803 /* 804 * indicates whether pv emulation should be disabled if features 805 * are not present in the guest's cpuid 806 */ 807 bool enforce; 808 } pv_cpuid; 809 810 /* Protected Guests */ 811 bool guest_state_protected; 812 }; 813 814 struct kvm_lpage_info { 815 int disallow_lpage; 816 }; 817 818 struct kvm_arch_memory_slot { 819 struct kvm_rmap_head *rmap[KVM_NR_PAGE_SIZES]; 820 struct kvm_lpage_info *lpage_info[KVM_NR_PAGE_SIZES - 1]; 821 unsigned short *gfn_track[KVM_PAGE_TRACK_MAX]; 822 }; 823 824 /* 825 * We use as the mode the number of bits allocated in the LDR for the 826 * logical processor ID. It happens that these are all powers of two. 827 * This makes it is very easy to detect cases where the APICs are 828 * configured for multiple modes; in that case, we cannot use the map and 829 * hence cannot use kvm_irq_delivery_to_apic_fast either. 830 */ 831 #define KVM_APIC_MODE_XAPIC_CLUSTER 4 832 #define KVM_APIC_MODE_XAPIC_FLAT 8 833 #define KVM_APIC_MODE_X2APIC 16 834 835 struct kvm_apic_map { 836 struct rcu_head rcu; 837 u8 mode; 838 u32 max_apic_id; 839 union { 840 struct kvm_lapic *xapic_flat_map[8]; 841 struct kvm_lapic *xapic_cluster_map[16][4]; 842 }; 843 struct kvm_lapic *phys_map[]; 844 }; 845 846 /* Hyper-V synthetic debugger (SynDbg)*/ 847 struct kvm_hv_syndbg { 848 struct { 849 u64 control; 850 u64 status; 851 u64 send_page; 852 u64 recv_page; 853 u64 pending_page; 854 } control; 855 u64 options; 856 }; 857 858 /* Hyper-V emulation context */ 859 struct kvm_hv { 860 struct mutex hv_lock; 861 u64 hv_guest_os_id; 862 u64 hv_hypercall; 863 u64 hv_tsc_page; 864 865 /* Hyper-v based guest crash (NT kernel bugcheck) parameters */ 866 u64 hv_crash_param[HV_X64_MSR_CRASH_PARAMS]; 867 u64 hv_crash_ctl; 868 869 struct ms_hyperv_tsc_page tsc_ref; 870 871 struct idr conn_to_evt; 872 873 u64 hv_reenlightenment_control; 874 u64 hv_tsc_emulation_control; 875 u64 hv_tsc_emulation_status; 876 877 /* How many vCPUs have VP index != vCPU index */ 878 atomic_t num_mismatched_vp_indexes; 879 880 struct hv_partition_assist_pg *hv_pa_pg; 881 struct kvm_hv_syndbg hv_syndbg; 882 }; 883 884 struct msr_bitmap_range { 885 u32 flags; 886 u32 nmsrs; 887 u32 base; 888 unsigned long *bitmap; 889 }; 890 891 enum kvm_irqchip_mode { 892 KVM_IRQCHIP_NONE, 893 KVM_IRQCHIP_KERNEL, /* created with KVM_CREATE_IRQCHIP */ 894 KVM_IRQCHIP_SPLIT, /* created with KVM_CAP_SPLIT_IRQCHIP */ 895 }; 896 897 #define APICV_INHIBIT_REASON_DISABLE 0 898 #define APICV_INHIBIT_REASON_HYPERV 1 899 #define APICV_INHIBIT_REASON_NESTED 2 900 #define APICV_INHIBIT_REASON_IRQWIN 3 901 #define APICV_INHIBIT_REASON_PIT_REINJ 4 902 #define APICV_INHIBIT_REASON_X2APIC 5 903 904 struct kvm_arch { 905 unsigned long n_used_mmu_pages; 906 unsigned long n_requested_mmu_pages; 907 unsigned long n_max_mmu_pages; 908 unsigned int indirect_shadow_pages; 909 u8 mmu_valid_gen; 910 struct hlist_head mmu_page_hash[KVM_NUM_MMU_PAGES]; 911 /* 912 * Hash table of struct kvm_mmu_page. 913 */ 914 struct list_head active_mmu_pages; 915 struct list_head zapped_obsolete_pages; 916 struct list_head lpage_disallowed_mmu_pages; 917 struct kvm_page_track_notifier_node mmu_sp_tracker; 918 struct kvm_page_track_notifier_head track_notifier_head; 919 920 struct list_head assigned_dev_head; 921 struct iommu_domain *iommu_domain; 922 bool iommu_noncoherent; 923 #define __KVM_HAVE_ARCH_NONCOHERENT_DMA 924 atomic_t noncoherent_dma_count; 925 #define __KVM_HAVE_ARCH_ASSIGNED_DEVICE 926 atomic_t assigned_device_count; 927 struct kvm_pic *vpic; 928 struct kvm_ioapic *vioapic; 929 struct kvm_pit *vpit; 930 atomic_t vapics_in_nmi_mode; 931 struct mutex apic_map_lock; 932 struct kvm_apic_map *apic_map; 933 atomic_t apic_map_dirty; 934 935 bool apic_access_page_done; 936 unsigned long apicv_inhibit_reasons; 937 938 gpa_t wall_clock; 939 940 bool mwait_in_guest; 941 bool hlt_in_guest; 942 bool pause_in_guest; 943 bool cstate_in_guest; 944 945 unsigned long irq_sources_bitmap; 946 s64 kvmclock_offset; 947 raw_spinlock_t tsc_write_lock; 948 u64 last_tsc_nsec; 949 u64 last_tsc_write; 950 u32 last_tsc_khz; 951 u64 cur_tsc_nsec; 952 u64 cur_tsc_write; 953 u64 cur_tsc_offset; 954 u64 cur_tsc_generation; 955 int nr_vcpus_matched_tsc; 956 957 spinlock_t pvclock_gtod_sync_lock; 958 bool use_master_clock; 959 u64 master_kernel_ns; 960 u64 master_cycle_now; 961 struct delayed_work kvmclock_update_work; 962 struct delayed_work kvmclock_sync_work; 963 964 struct kvm_xen_hvm_config xen_hvm_config; 965 966 /* reads protected by irq_srcu, writes by irq_lock */ 967 struct hlist_head mask_notifier_list; 968 969 struct kvm_hv hyperv; 970 971 #ifdef CONFIG_KVM_MMU_AUDIT 972 int audit_point; 973 #endif 974 975 bool backwards_tsc_observed; 976 bool boot_vcpu_runs_old_kvmclock; 977 u32 bsp_vcpu_id; 978 979 u64 disabled_quirks; 980 981 enum kvm_irqchip_mode irqchip_mode; 982 u8 nr_reserved_ioapic_pins; 983 984 bool disabled_lapic_found; 985 986 bool x2apic_format; 987 bool x2apic_broadcast_quirk_disabled; 988 989 bool guest_can_read_msr_platform_info; 990 bool exception_payload_enabled; 991 992 /* Deflect RDMSR and WRMSR to user space when they trigger a #GP */ 993 u32 user_space_msr_mask; 994 995 struct { 996 u8 count; 997 bool default_allow:1; 998 struct msr_bitmap_range ranges[16]; 999 } msr_filter; 1000 1001 struct kvm_pmu_event_filter *pmu_event_filter; 1002 struct task_struct *nx_lpage_recovery_thread; 1003 1004 /* 1005 * Whether the TDP MMU is enabled for this VM. This contains a 1006 * snapshot of the TDP MMU module parameter from when the VM was 1007 * created and remains unchanged for the life of the VM. If this is 1008 * true, TDP MMU handler functions will run for various MMU 1009 * operations. 1010 */ 1011 bool tdp_mmu_enabled; 1012 1013 /* 1014 * List of struct kvmp_mmu_pages being used as roots. 1015 * All struct kvm_mmu_pages in the list should have 1016 * tdp_mmu_page set. 1017 * All struct kvm_mmu_pages in the list should have a positive 1018 * root_count except when a thread holds the MMU lock and is removing 1019 * an entry from the list. 1020 */ 1021 struct list_head tdp_mmu_roots; 1022 1023 /* 1024 * List of struct kvmp_mmu_pages not being used as roots. 1025 * All struct kvm_mmu_pages in the list should have 1026 * tdp_mmu_page set and a root_count of 0. 1027 */ 1028 struct list_head tdp_mmu_pages; 1029 }; 1030 1031 struct kvm_vm_stat { 1032 ulong mmu_shadow_zapped; 1033 ulong mmu_pte_write; 1034 ulong mmu_pte_updated; 1035 ulong mmu_pde_zapped; 1036 ulong mmu_flooded; 1037 ulong mmu_recycled; 1038 ulong mmu_cache_miss; 1039 ulong mmu_unsync; 1040 ulong remote_tlb_flush; 1041 ulong lpages; 1042 ulong nx_lpage_splits; 1043 ulong max_mmu_page_hash_collisions; 1044 }; 1045 1046 struct kvm_vcpu_stat { 1047 u64 pf_fixed; 1048 u64 pf_guest; 1049 u64 tlb_flush; 1050 u64 invlpg; 1051 1052 u64 exits; 1053 u64 io_exits; 1054 u64 mmio_exits; 1055 u64 signal_exits; 1056 u64 irq_window_exits; 1057 u64 nmi_window_exits; 1058 u64 l1d_flush; 1059 u64 halt_exits; 1060 u64 halt_successful_poll; 1061 u64 halt_attempted_poll; 1062 u64 halt_poll_invalid; 1063 u64 halt_wakeup; 1064 u64 request_irq_exits; 1065 u64 irq_exits; 1066 u64 host_state_reload; 1067 u64 fpu_reload; 1068 u64 insn_emulation; 1069 u64 insn_emulation_fail; 1070 u64 hypercalls; 1071 u64 irq_injections; 1072 u64 nmi_injections; 1073 u64 req_event; 1074 u64 halt_poll_success_ns; 1075 u64 halt_poll_fail_ns; 1076 }; 1077 1078 struct x86_instruction_info; 1079 1080 struct msr_data { 1081 bool host_initiated; 1082 u32 index; 1083 u64 data; 1084 }; 1085 1086 struct kvm_lapic_irq { 1087 u32 vector; 1088 u16 delivery_mode; 1089 u16 dest_mode; 1090 bool level; 1091 u16 trig_mode; 1092 u32 shorthand; 1093 u32 dest_id; 1094 bool msi_redir_hint; 1095 }; 1096 1097 static inline u16 kvm_lapic_irq_dest_mode(bool dest_mode_logical) 1098 { 1099 return dest_mode_logical ? APIC_DEST_LOGICAL : APIC_DEST_PHYSICAL; 1100 } 1101 1102 struct kvm_x86_ops { 1103 int (*hardware_enable)(void); 1104 void (*hardware_disable)(void); 1105 void (*hardware_unsetup)(void); 1106 bool (*cpu_has_accelerated_tpr)(void); 1107 bool (*has_emulated_msr)(struct kvm *kvm, u32 index); 1108 void (*vcpu_after_set_cpuid)(struct kvm_vcpu *vcpu); 1109 1110 unsigned int vm_size; 1111 int (*vm_init)(struct kvm *kvm); 1112 void (*vm_destroy)(struct kvm *kvm); 1113 1114 /* Create, but do not attach this VCPU */ 1115 int (*vcpu_create)(struct kvm_vcpu *vcpu); 1116 void (*vcpu_free)(struct kvm_vcpu *vcpu); 1117 void (*vcpu_reset)(struct kvm_vcpu *vcpu, bool init_event); 1118 1119 void (*prepare_guest_switch)(struct kvm_vcpu *vcpu); 1120 void (*vcpu_load)(struct kvm_vcpu *vcpu, int cpu); 1121 void (*vcpu_put)(struct kvm_vcpu *vcpu); 1122 1123 void (*update_exception_bitmap)(struct kvm_vcpu *vcpu); 1124 int (*get_msr)(struct kvm_vcpu *vcpu, struct msr_data *msr); 1125 int (*set_msr)(struct kvm_vcpu *vcpu, struct msr_data *msr); 1126 u64 (*get_segment_base)(struct kvm_vcpu *vcpu, int seg); 1127 void (*get_segment)(struct kvm_vcpu *vcpu, 1128 struct kvm_segment *var, int seg); 1129 int (*get_cpl)(struct kvm_vcpu *vcpu); 1130 void (*set_segment)(struct kvm_vcpu *vcpu, 1131 struct kvm_segment *var, int seg); 1132 void (*get_cs_db_l_bits)(struct kvm_vcpu *vcpu, int *db, int *l); 1133 void (*set_cr0)(struct kvm_vcpu *vcpu, unsigned long cr0); 1134 bool (*is_valid_cr4)(struct kvm_vcpu *vcpu, unsigned long cr0); 1135 void (*set_cr4)(struct kvm_vcpu *vcpu, unsigned long cr4); 1136 int (*set_efer)(struct kvm_vcpu *vcpu, u64 efer); 1137 void (*get_idt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt); 1138 void (*set_idt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt); 1139 void (*get_gdt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt); 1140 void (*set_gdt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt); 1141 void (*sync_dirty_debug_regs)(struct kvm_vcpu *vcpu); 1142 void (*set_dr7)(struct kvm_vcpu *vcpu, unsigned long value); 1143 void (*cache_reg)(struct kvm_vcpu *vcpu, enum kvm_reg reg); 1144 unsigned long (*get_rflags)(struct kvm_vcpu *vcpu); 1145 void (*set_rflags)(struct kvm_vcpu *vcpu, unsigned long rflags); 1146 1147 void (*tlb_flush_all)(struct kvm_vcpu *vcpu); 1148 void (*tlb_flush_current)(struct kvm_vcpu *vcpu); 1149 int (*tlb_remote_flush)(struct kvm *kvm); 1150 int (*tlb_remote_flush_with_range)(struct kvm *kvm, 1151 struct kvm_tlb_range *range); 1152 1153 /* 1154 * Flush any TLB entries associated with the given GVA. 1155 * Does not need to flush GPA->HPA mappings. 1156 * Can potentially get non-canonical addresses through INVLPGs, which 1157 * the implementation may choose to ignore if appropriate. 1158 */ 1159 void (*tlb_flush_gva)(struct kvm_vcpu *vcpu, gva_t addr); 1160 1161 /* 1162 * Flush any TLB entries created by the guest. Like tlb_flush_gva(), 1163 * does not need to flush GPA->HPA mappings. 1164 */ 1165 void (*tlb_flush_guest)(struct kvm_vcpu *vcpu); 1166 1167 enum exit_fastpath_completion (*run)(struct kvm_vcpu *vcpu); 1168 int (*handle_exit)(struct kvm_vcpu *vcpu, 1169 enum exit_fastpath_completion exit_fastpath); 1170 int (*skip_emulated_instruction)(struct kvm_vcpu *vcpu); 1171 void (*update_emulated_instruction)(struct kvm_vcpu *vcpu); 1172 void (*set_interrupt_shadow)(struct kvm_vcpu *vcpu, int mask); 1173 u32 (*get_interrupt_shadow)(struct kvm_vcpu *vcpu); 1174 void (*patch_hypercall)(struct kvm_vcpu *vcpu, 1175 unsigned char *hypercall_addr); 1176 void (*set_irq)(struct kvm_vcpu *vcpu); 1177 void (*set_nmi)(struct kvm_vcpu *vcpu); 1178 void (*queue_exception)(struct kvm_vcpu *vcpu); 1179 void (*cancel_injection)(struct kvm_vcpu *vcpu); 1180 int (*interrupt_allowed)(struct kvm_vcpu *vcpu, bool for_injection); 1181 int (*nmi_allowed)(struct kvm_vcpu *vcpu, bool for_injection); 1182 bool (*get_nmi_mask)(struct kvm_vcpu *vcpu); 1183 void (*set_nmi_mask)(struct kvm_vcpu *vcpu, bool masked); 1184 void (*enable_nmi_window)(struct kvm_vcpu *vcpu); 1185 void (*enable_irq_window)(struct kvm_vcpu *vcpu); 1186 void (*update_cr8_intercept)(struct kvm_vcpu *vcpu, int tpr, int irr); 1187 bool (*check_apicv_inhibit_reasons)(ulong bit); 1188 void (*pre_update_apicv_exec_ctrl)(struct kvm *kvm, bool activate); 1189 void (*refresh_apicv_exec_ctrl)(struct kvm_vcpu *vcpu); 1190 void (*hwapic_irr_update)(struct kvm_vcpu *vcpu, int max_irr); 1191 void (*hwapic_isr_update)(struct kvm_vcpu *vcpu, int isr); 1192 bool (*guest_apic_has_interrupt)(struct kvm_vcpu *vcpu); 1193 void (*load_eoi_exitmap)(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap); 1194 void (*set_virtual_apic_mode)(struct kvm_vcpu *vcpu); 1195 void (*set_apic_access_page_addr)(struct kvm_vcpu *vcpu); 1196 int (*deliver_posted_interrupt)(struct kvm_vcpu *vcpu, int vector); 1197 int (*sync_pir_to_irr)(struct kvm_vcpu *vcpu); 1198 int (*set_tss_addr)(struct kvm *kvm, unsigned int addr); 1199 int (*set_identity_map_addr)(struct kvm *kvm, u64 ident_addr); 1200 u64 (*get_mt_mask)(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio); 1201 1202 void (*load_mmu_pgd)(struct kvm_vcpu *vcpu, unsigned long pgd, 1203 int pgd_level); 1204 1205 bool (*has_wbinvd_exit)(void); 1206 1207 /* Returns actual tsc_offset set in active VMCS */ 1208 u64 (*write_l1_tsc_offset)(struct kvm_vcpu *vcpu, u64 offset); 1209 1210 /* 1211 * Retrieve somewhat arbitrary exit information. Intended to be used 1212 * only from within tracepoints to avoid VMREADs when tracing is off. 1213 */ 1214 void (*get_exit_info)(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2, 1215 u32 *exit_int_info, u32 *exit_int_info_err_code); 1216 1217 int (*check_intercept)(struct kvm_vcpu *vcpu, 1218 struct x86_instruction_info *info, 1219 enum x86_intercept_stage stage, 1220 struct x86_exception *exception); 1221 void (*handle_exit_irqoff)(struct kvm_vcpu *vcpu); 1222 1223 void (*request_immediate_exit)(struct kvm_vcpu *vcpu); 1224 1225 void (*sched_in)(struct kvm_vcpu *kvm, int cpu); 1226 1227 /* 1228 * Arch-specific dirty logging hooks. These hooks are only supposed to 1229 * be valid if the specific arch has hardware-accelerated dirty logging 1230 * mechanism. Currently only for PML on VMX. 1231 * 1232 * - slot_enable_log_dirty: 1233 * called when enabling log dirty mode for the slot. 1234 * - slot_disable_log_dirty: 1235 * called when disabling log dirty mode for the slot. 1236 * also called when slot is created with log dirty disabled. 1237 * - flush_log_dirty: 1238 * called before reporting dirty_bitmap to userspace. 1239 * - enable_log_dirty_pt_masked: 1240 * called when reenabling log dirty for the GFNs in the mask after 1241 * corresponding bits are cleared in slot->dirty_bitmap. 1242 */ 1243 void (*slot_enable_log_dirty)(struct kvm *kvm, 1244 struct kvm_memory_slot *slot); 1245 void (*slot_disable_log_dirty)(struct kvm *kvm, 1246 struct kvm_memory_slot *slot); 1247 void (*flush_log_dirty)(struct kvm *kvm); 1248 void (*enable_log_dirty_pt_masked)(struct kvm *kvm, 1249 struct kvm_memory_slot *slot, 1250 gfn_t offset, unsigned long mask); 1251 int (*cpu_dirty_log_size)(void); 1252 1253 /* pmu operations of sub-arch */ 1254 const struct kvm_pmu_ops *pmu_ops; 1255 const struct kvm_x86_nested_ops *nested_ops; 1256 1257 /* 1258 * Architecture specific hooks for vCPU blocking due to 1259 * HLT instruction. 1260 * Returns for .pre_block(): 1261 * - 0 means continue to block the vCPU. 1262 * - 1 means we cannot block the vCPU since some event 1263 * happens during this period, such as, 'ON' bit in 1264 * posted-interrupts descriptor is set. 1265 */ 1266 int (*pre_block)(struct kvm_vcpu *vcpu); 1267 void (*post_block)(struct kvm_vcpu *vcpu); 1268 1269 void (*vcpu_blocking)(struct kvm_vcpu *vcpu); 1270 void (*vcpu_unblocking)(struct kvm_vcpu *vcpu); 1271 1272 int (*update_pi_irte)(struct kvm *kvm, unsigned int host_irq, 1273 uint32_t guest_irq, bool set); 1274 void (*apicv_post_state_restore)(struct kvm_vcpu *vcpu); 1275 bool (*dy_apicv_has_pending_interrupt)(struct kvm_vcpu *vcpu); 1276 1277 int (*set_hv_timer)(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc, 1278 bool *expired); 1279 void (*cancel_hv_timer)(struct kvm_vcpu *vcpu); 1280 1281 void (*setup_mce)(struct kvm_vcpu *vcpu); 1282 1283 int (*smi_allowed)(struct kvm_vcpu *vcpu, bool for_injection); 1284 int (*pre_enter_smm)(struct kvm_vcpu *vcpu, char *smstate); 1285 int (*pre_leave_smm)(struct kvm_vcpu *vcpu, const char *smstate); 1286 void (*enable_smi_window)(struct kvm_vcpu *vcpu); 1287 1288 int (*mem_enc_op)(struct kvm *kvm, void __user *argp); 1289 int (*mem_enc_reg_region)(struct kvm *kvm, struct kvm_enc_region *argp); 1290 int (*mem_enc_unreg_region)(struct kvm *kvm, struct kvm_enc_region *argp); 1291 1292 int (*get_msr_feature)(struct kvm_msr_entry *entry); 1293 1294 bool (*can_emulate_instruction)(struct kvm_vcpu *vcpu, void *insn, int insn_len); 1295 1296 bool (*apic_init_signal_blocked)(struct kvm_vcpu *vcpu); 1297 int (*enable_direct_tlbflush)(struct kvm_vcpu *vcpu); 1298 1299 void (*migrate_timers)(struct kvm_vcpu *vcpu); 1300 void (*msr_filter_changed)(struct kvm_vcpu *vcpu); 1301 int (*complete_emulated_msr)(struct kvm_vcpu *vcpu, int err); 1302 1303 void (*vcpu_deliver_sipi_vector)(struct kvm_vcpu *vcpu, u8 vector); 1304 }; 1305 1306 struct kvm_x86_nested_ops { 1307 int (*check_events)(struct kvm_vcpu *vcpu); 1308 bool (*hv_timer_pending)(struct kvm_vcpu *vcpu); 1309 int (*get_state)(struct kvm_vcpu *vcpu, 1310 struct kvm_nested_state __user *user_kvm_nested_state, 1311 unsigned user_data_size); 1312 int (*set_state)(struct kvm_vcpu *vcpu, 1313 struct kvm_nested_state __user *user_kvm_nested_state, 1314 struct kvm_nested_state *kvm_state); 1315 bool (*get_nested_state_pages)(struct kvm_vcpu *vcpu); 1316 int (*write_log_dirty)(struct kvm_vcpu *vcpu, gpa_t l2_gpa); 1317 1318 int (*enable_evmcs)(struct kvm_vcpu *vcpu, 1319 uint16_t *vmcs_version); 1320 uint16_t (*get_evmcs_version)(struct kvm_vcpu *vcpu); 1321 }; 1322 1323 struct kvm_x86_init_ops { 1324 int (*cpu_has_kvm_support)(void); 1325 int (*disabled_by_bios)(void); 1326 int (*check_processor_compatibility)(void); 1327 int (*hardware_setup)(void); 1328 1329 struct kvm_x86_ops *runtime_ops; 1330 }; 1331 1332 struct kvm_arch_async_pf { 1333 u32 token; 1334 gfn_t gfn; 1335 unsigned long cr3; 1336 bool direct_map; 1337 }; 1338 1339 extern u64 __read_mostly host_efer; 1340 extern bool __read_mostly allow_smaller_maxphyaddr; 1341 extern struct kvm_x86_ops kvm_x86_ops; 1342 1343 #define __KVM_HAVE_ARCH_VM_ALLOC 1344 static inline struct kvm *kvm_arch_alloc_vm(void) 1345 { 1346 return __vmalloc(kvm_x86_ops.vm_size, GFP_KERNEL_ACCOUNT | __GFP_ZERO); 1347 } 1348 void kvm_arch_free_vm(struct kvm *kvm); 1349 1350 #define __KVM_HAVE_ARCH_FLUSH_REMOTE_TLB 1351 static inline int kvm_arch_flush_remote_tlb(struct kvm *kvm) 1352 { 1353 if (kvm_x86_ops.tlb_remote_flush && 1354 !kvm_x86_ops.tlb_remote_flush(kvm)) 1355 return 0; 1356 else 1357 return -ENOTSUPP; 1358 } 1359 1360 int kvm_mmu_module_init(void); 1361 void kvm_mmu_module_exit(void); 1362 1363 void kvm_mmu_destroy(struct kvm_vcpu *vcpu); 1364 int kvm_mmu_create(struct kvm_vcpu *vcpu); 1365 void kvm_mmu_init_vm(struct kvm *kvm); 1366 void kvm_mmu_uninit_vm(struct kvm *kvm); 1367 void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask, 1368 u64 dirty_mask, u64 nx_mask, u64 x_mask, u64 p_mask, 1369 u64 acc_track_mask, u64 me_mask); 1370 1371 void kvm_mmu_reset_context(struct kvm_vcpu *vcpu); 1372 void kvm_mmu_slot_remove_write_access(struct kvm *kvm, 1373 struct kvm_memory_slot *memslot, 1374 int start_level); 1375 void kvm_mmu_zap_collapsible_sptes(struct kvm *kvm, 1376 const struct kvm_memory_slot *memslot); 1377 void kvm_mmu_slot_leaf_clear_dirty(struct kvm *kvm, 1378 struct kvm_memory_slot *memslot); 1379 void kvm_mmu_slot_largepage_remove_write_access(struct kvm *kvm, 1380 struct kvm_memory_slot *memslot); 1381 void kvm_mmu_slot_set_dirty(struct kvm *kvm, 1382 struct kvm_memory_slot *memslot); 1383 void kvm_mmu_clear_dirty_pt_masked(struct kvm *kvm, 1384 struct kvm_memory_slot *slot, 1385 gfn_t gfn_offset, unsigned long mask); 1386 void kvm_mmu_zap_all(struct kvm *kvm); 1387 void kvm_mmu_invalidate_mmio_sptes(struct kvm *kvm, u64 gen); 1388 unsigned long kvm_mmu_calculate_default_mmu_pages(struct kvm *kvm); 1389 void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned long kvm_nr_mmu_pages); 1390 1391 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3); 1392 bool pdptrs_changed(struct kvm_vcpu *vcpu); 1393 1394 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa, 1395 const void *val, int bytes); 1396 1397 struct kvm_irq_mask_notifier { 1398 void (*func)(struct kvm_irq_mask_notifier *kimn, bool masked); 1399 int irq; 1400 struct hlist_node link; 1401 }; 1402 1403 void kvm_register_irq_mask_notifier(struct kvm *kvm, int irq, 1404 struct kvm_irq_mask_notifier *kimn); 1405 void kvm_unregister_irq_mask_notifier(struct kvm *kvm, int irq, 1406 struct kvm_irq_mask_notifier *kimn); 1407 void kvm_fire_mask_notifiers(struct kvm *kvm, unsigned irqchip, unsigned pin, 1408 bool mask); 1409 1410 extern bool tdp_enabled; 1411 1412 u64 vcpu_tsc_khz(struct kvm_vcpu *vcpu); 1413 1414 /* control of guest tsc rate supported? */ 1415 extern bool kvm_has_tsc_control; 1416 /* maximum supported tsc_khz for guests */ 1417 extern u32 kvm_max_guest_tsc_khz; 1418 /* number of bits of the fractional part of the TSC scaling ratio */ 1419 extern u8 kvm_tsc_scaling_ratio_frac_bits; 1420 /* maximum allowed value of TSC scaling ratio */ 1421 extern u64 kvm_max_tsc_scaling_ratio; 1422 /* 1ull << kvm_tsc_scaling_ratio_frac_bits */ 1423 extern u64 kvm_default_tsc_scaling_ratio; 1424 1425 extern u64 kvm_mce_cap_supported; 1426 1427 /* 1428 * EMULTYPE_NO_DECODE - Set when re-emulating an instruction (after completing 1429 * userspace I/O) to indicate that the emulation context 1430 * should be resued as is, i.e. skip initialization of 1431 * emulation context, instruction fetch and decode. 1432 * 1433 * EMULTYPE_TRAP_UD - Set when emulating an intercepted #UD from hardware. 1434 * Indicates that only select instructions (tagged with 1435 * EmulateOnUD) should be emulated (to minimize the emulator 1436 * attack surface). See also EMULTYPE_TRAP_UD_FORCED. 1437 * 1438 * EMULTYPE_SKIP - Set when emulating solely to skip an instruction, i.e. to 1439 * decode the instruction length. For use *only* by 1440 * kvm_x86_ops.skip_emulated_instruction() implementations. 1441 * 1442 * EMULTYPE_ALLOW_RETRY_PF - Set when the emulator should resume the guest to 1443 * retry native execution under certain conditions, 1444 * Can only be set in conjunction with EMULTYPE_PF. 1445 * 1446 * EMULTYPE_TRAP_UD_FORCED - Set when emulating an intercepted #UD that was 1447 * triggered by KVM's magic "force emulation" prefix, 1448 * which is opt in via module param (off by default). 1449 * Bypasses EmulateOnUD restriction despite emulating 1450 * due to an intercepted #UD (see EMULTYPE_TRAP_UD). 1451 * Used to test the full emulator from userspace. 1452 * 1453 * EMULTYPE_VMWARE_GP - Set when emulating an intercepted #GP for VMware 1454 * backdoor emulation, which is opt in via module param. 1455 * VMware backoor emulation handles select instructions 1456 * and reinjects the #GP for all other cases. 1457 * 1458 * EMULTYPE_PF - Set when emulating MMIO by way of an intercepted #PF, in which 1459 * case the CR2/GPA value pass on the stack is valid. 1460 */ 1461 #define EMULTYPE_NO_DECODE (1 << 0) 1462 #define EMULTYPE_TRAP_UD (1 << 1) 1463 #define EMULTYPE_SKIP (1 << 2) 1464 #define EMULTYPE_ALLOW_RETRY_PF (1 << 3) 1465 #define EMULTYPE_TRAP_UD_FORCED (1 << 4) 1466 #define EMULTYPE_VMWARE_GP (1 << 5) 1467 #define EMULTYPE_PF (1 << 6) 1468 1469 int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type); 1470 int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu, 1471 void *insn, int insn_len); 1472 1473 void kvm_enable_efer_bits(u64); 1474 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer); 1475 int __kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data, bool host_initiated); 1476 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data); 1477 int kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data); 1478 int kvm_emulate_rdmsr(struct kvm_vcpu *vcpu); 1479 int kvm_emulate_wrmsr(struct kvm_vcpu *vcpu); 1480 1481 int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in); 1482 int kvm_emulate_cpuid(struct kvm_vcpu *vcpu); 1483 int kvm_emulate_halt(struct kvm_vcpu *vcpu); 1484 int kvm_vcpu_halt(struct kvm_vcpu *vcpu); 1485 int kvm_emulate_ap_reset_hold(struct kvm_vcpu *vcpu); 1486 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu); 1487 1488 void kvm_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg); 1489 int kvm_load_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector, int seg); 1490 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector); 1491 1492 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index, 1493 int reason, bool has_error_code, u32 error_code); 1494 1495 void kvm_free_guest_fpu(struct kvm_vcpu *vcpu); 1496 1497 void kvm_post_set_cr0(struct kvm_vcpu *vcpu, unsigned long old_cr0, unsigned long cr0); 1498 void kvm_post_set_cr4(struct kvm_vcpu *vcpu, unsigned long old_cr4, unsigned long cr4); 1499 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0); 1500 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3); 1501 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4); 1502 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8); 1503 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val); 1504 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val); 1505 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu); 1506 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw); 1507 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l); 1508 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr); 1509 1510 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr); 1511 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr); 1512 1513 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu); 1514 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags); 1515 bool kvm_rdpmc(struct kvm_vcpu *vcpu); 1516 1517 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr); 1518 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code); 1519 void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr, unsigned long payload); 1520 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr); 1521 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code); 1522 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault); 1523 bool kvm_inject_emulated_page_fault(struct kvm_vcpu *vcpu, 1524 struct x86_exception *fault); 1525 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, 1526 gfn_t gfn, void *data, int offset, int len, 1527 u32 access); 1528 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl); 1529 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr); 1530 1531 static inline int __kvm_irq_line_state(unsigned long *irq_state, 1532 int irq_source_id, int level) 1533 { 1534 /* Logical OR for level trig interrupt */ 1535 if (level) 1536 __set_bit(irq_source_id, irq_state); 1537 else 1538 __clear_bit(irq_source_id, irq_state); 1539 1540 return !!(*irq_state); 1541 } 1542 1543 #define KVM_MMU_ROOT_CURRENT BIT(0) 1544 #define KVM_MMU_ROOT_PREVIOUS(i) BIT(1+i) 1545 #define KVM_MMU_ROOTS_ALL (~0UL) 1546 1547 int kvm_pic_set_irq(struct kvm_pic *pic, int irq, int irq_source_id, int level); 1548 void kvm_pic_clear_all(struct kvm_pic *pic, int irq_source_id); 1549 1550 void kvm_inject_nmi(struct kvm_vcpu *vcpu); 1551 1552 void kvm_update_dr7(struct kvm_vcpu *vcpu); 1553 1554 int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn); 1555 int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva); 1556 void __kvm_mmu_free_some_pages(struct kvm_vcpu *vcpu); 1557 int kvm_mmu_load(struct kvm_vcpu *vcpu); 1558 void kvm_mmu_unload(struct kvm_vcpu *vcpu); 1559 void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu); 1560 void kvm_mmu_free_roots(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, 1561 ulong roots_to_free); 1562 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access, 1563 struct x86_exception *exception); 1564 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, 1565 struct x86_exception *exception); 1566 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, 1567 struct x86_exception *exception); 1568 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, 1569 struct x86_exception *exception); 1570 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, 1571 struct x86_exception *exception); 1572 1573 bool kvm_apicv_activated(struct kvm *kvm); 1574 void kvm_apicv_init(struct kvm *kvm, bool enable); 1575 void kvm_vcpu_update_apicv(struct kvm_vcpu *vcpu); 1576 void kvm_request_apicv_update(struct kvm *kvm, bool activate, 1577 unsigned long bit); 1578 1579 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu); 1580 1581 int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, u64 error_code, 1582 void *insn, int insn_len); 1583 void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva); 1584 void kvm_mmu_invalidate_gva(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, 1585 gva_t gva, hpa_t root_hpa); 1586 void kvm_mmu_invpcid_gva(struct kvm_vcpu *vcpu, gva_t gva, unsigned long pcid); 1587 void kvm_mmu_new_pgd(struct kvm_vcpu *vcpu, gpa_t new_pgd, bool skip_tlb_flush, 1588 bool skip_mmu_sync); 1589 1590 void kvm_configure_mmu(bool enable_tdp, int tdp_max_root_level, 1591 int tdp_huge_page_level); 1592 1593 static inline u16 kvm_read_ldt(void) 1594 { 1595 u16 ldt; 1596 asm("sldt %0" : "=g"(ldt)); 1597 return ldt; 1598 } 1599 1600 static inline void kvm_load_ldt(u16 sel) 1601 { 1602 asm("lldt %0" : : "rm"(sel)); 1603 } 1604 1605 #ifdef CONFIG_X86_64 1606 static inline unsigned long read_msr(unsigned long msr) 1607 { 1608 u64 value; 1609 1610 rdmsrl(msr, value); 1611 return value; 1612 } 1613 #endif 1614 1615 static inline u32 get_rdx_init_val(void) 1616 { 1617 return 0x600; /* P6 family */ 1618 } 1619 1620 static inline void kvm_inject_gp(struct kvm_vcpu *vcpu, u32 error_code) 1621 { 1622 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code); 1623 } 1624 1625 #define TSS_IOPB_BASE_OFFSET 0x66 1626 #define TSS_BASE_SIZE 0x68 1627 #define TSS_IOPB_SIZE (65536 / 8) 1628 #define TSS_REDIRECTION_SIZE (256 / 8) 1629 #define RMODE_TSS_SIZE \ 1630 (TSS_BASE_SIZE + TSS_REDIRECTION_SIZE + TSS_IOPB_SIZE + 1) 1631 1632 enum { 1633 TASK_SWITCH_CALL = 0, 1634 TASK_SWITCH_IRET = 1, 1635 TASK_SWITCH_JMP = 2, 1636 TASK_SWITCH_GATE = 3, 1637 }; 1638 1639 #define HF_GIF_MASK (1 << 0) 1640 #define HF_NMI_MASK (1 << 3) 1641 #define HF_IRET_MASK (1 << 4) 1642 #define HF_GUEST_MASK (1 << 5) /* VCPU is in guest-mode */ 1643 #define HF_SMM_MASK (1 << 6) 1644 #define HF_SMM_INSIDE_NMI_MASK (1 << 7) 1645 1646 #define __KVM_VCPU_MULTIPLE_ADDRESS_SPACE 1647 #define KVM_ADDRESS_SPACE_NUM 2 1648 1649 #define kvm_arch_vcpu_memslots_id(vcpu) ((vcpu)->arch.hflags & HF_SMM_MASK ? 1 : 0) 1650 #define kvm_memslots_for_spte_role(kvm, role) __kvm_memslots(kvm, (role).smm) 1651 1652 asmlinkage void kvm_spurious_fault(void); 1653 1654 /* 1655 * Hardware virtualization extension instructions may fault if a 1656 * reboot turns off virtualization while processes are running. 1657 * Usually after catching the fault we just panic; during reboot 1658 * instead the instruction is ignored. 1659 */ 1660 #define __kvm_handle_fault_on_reboot(insn) \ 1661 "666: \n\t" \ 1662 insn "\n\t" \ 1663 "jmp 668f \n\t" \ 1664 "667: \n\t" \ 1665 "1: \n\t" \ 1666 ".pushsection .discard.instr_begin \n\t" \ 1667 ".long 1b - . \n\t" \ 1668 ".popsection \n\t" \ 1669 "call kvm_spurious_fault \n\t" \ 1670 "1: \n\t" \ 1671 ".pushsection .discard.instr_end \n\t" \ 1672 ".long 1b - . \n\t" \ 1673 ".popsection \n\t" \ 1674 "668: \n\t" \ 1675 _ASM_EXTABLE(666b, 667b) 1676 1677 #define KVM_ARCH_WANT_MMU_NOTIFIER 1678 int kvm_unmap_hva_range(struct kvm *kvm, unsigned long start, unsigned long end, 1679 unsigned flags); 1680 int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end); 1681 int kvm_test_age_hva(struct kvm *kvm, unsigned long hva); 1682 int kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte); 1683 int kvm_cpu_has_injectable_intr(struct kvm_vcpu *v); 1684 int kvm_cpu_has_interrupt(struct kvm_vcpu *vcpu); 1685 int kvm_cpu_has_extint(struct kvm_vcpu *v); 1686 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu); 1687 int kvm_cpu_get_interrupt(struct kvm_vcpu *v); 1688 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event); 1689 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu); 1690 1691 int kvm_pv_send_ipi(struct kvm *kvm, unsigned long ipi_bitmap_low, 1692 unsigned long ipi_bitmap_high, u32 min, 1693 unsigned long icr, int op_64_bit); 1694 1695 void kvm_define_user_return_msr(unsigned index, u32 msr); 1696 int kvm_set_user_return_msr(unsigned index, u64 val, u64 mask); 1697 1698 u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc); 1699 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc); 1700 1701 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu); 1702 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip); 1703 1704 void kvm_make_mclock_inprogress_request(struct kvm *kvm); 1705 void kvm_make_scan_ioapic_request(struct kvm *kvm); 1706 void kvm_make_scan_ioapic_request_mask(struct kvm *kvm, 1707 unsigned long *vcpu_bitmap); 1708 1709 bool kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu, 1710 struct kvm_async_pf *work); 1711 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu, 1712 struct kvm_async_pf *work); 1713 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, 1714 struct kvm_async_pf *work); 1715 void kvm_arch_async_page_present_queued(struct kvm_vcpu *vcpu); 1716 bool kvm_arch_can_dequeue_async_page_present(struct kvm_vcpu *vcpu); 1717 extern bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn); 1718 1719 int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu); 1720 int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err); 1721 void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu); 1722 1723 int kvm_is_in_guest(void); 1724 1725 void __user *__x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, 1726 u32 size); 1727 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu); 1728 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu); 1729 1730 bool kvm_intr_is_single_vcpu(struct kvm *kvm, struct kvm_lapic_irq *irq, 1731 struct kvm_vcpu **dest_vcpu); 1732 1733 void kvm_set_msi_irq(struct kvm *kvm, struct kvm_kernel_irq_routing_entry *e, 1734 struct kvm_lapic_irq *irq); 1735 1736 static inline bool kvm_irq_is_postable(struct kvm_lapic_irq *irq) 1737 { 1738 /* We can only post Fixed and LowPrio IRQs */ 1739 return (irq->delivery_mode == APIC_DM_FIXED || 1740 irq->delivery_mode == APIC_DM_LOWEST); 1741 } 1742 1743 static inline void kvm_arch_vcpu_blocking(struct kvm_vcpu *vcpu) 1744 { 1745 if (kvm_x86_ops.vcpu_blocking) 1746 kvm_x86_ops.vcpu_blocking(vcpu); 1747 } 1748 1749 static inline void kvm_arch_vcpu_unblocking(struct kvm_vcpu *vcpu) 1750 { 1751 if (kvm_x86_ops.vcpu_unblocking) 1752 kvm_x86_ops.vcpu_unblocking(vcpu); 1753 } 1754 1755 static inline void kvm_arch_vcpu_block_finish(struct kvm_vcpu *vcpu) {} 1756 1757 static inline int kvm_cpu_get_apicid(int mps_cpu) 1758 { 1759 #ifdef CONFIG_X86_LOCAL_APIC 1760 return default_cpu_present_to_apicid(mps_cpu); 1761 #else 1762 WARN_ON_ONCE(1); 1763 return BAD_APICID; 1764 #endif 1765 } 1766 1767 #define put_smstate(type, buf, offset, val) \ 1768 *(type *)((buf) + (offset) - 0x7e00) = val 1769 1770 #define GET_SMSTATE(type, buf, offset) \ 1771 (*(type *)((buf) + (offset) - 0x7e00)) 1772 1773 int kvm_cpu_dirty_log_size(void); 1774 1775 #endif /* _ASM_X86_KVM_HOST_H */ 1776