1 #ifndef _ASM_X86_IRQ_VECTORS_H 2 #define _ASM_X86_IRQ_VECTORS_H 3 4 #include <linux/threads.h> 5 /* 6 * Linux IRQ vector layout. 7 * 8 * There are 256 IDT entries (per CPU - each entry is 8 bytes) which can 9 * be defined by Linux. They are used as a jump table by the CPU when a 10 * given vector is triggered - by a CPU-external, CPU-internal or 11 * software-triggered event. 12 * 13 * Linux sets the kernel code address each entry jumps to early during 14 * bootup, and never changes them. This is the general layout of the 15 * IDT entries: 16 * 17 * Vectors 0 ... 31 : system traps and exceptions - hardcoded events 18 * Vectors 32 ... 127 : device interrupts 19 * Vector 128 : legacy int80 syscall interface 20 * Vectors 129 ... INVALIDATE_TLB_VECTOR_START-1 except 204 : device interrupts 21 * Vectors INVALIDATE_TLB_VECTOR_START ... 255 : special interrupts 22 * 23 * 64-bit x86 has per CPU IDT tables, 32-bit has one shared IDT table. 24 * 25 * This file enumerates the exact layout of them: 26 */ 27 28 #define NMI_VECTOR 0x02 29 #define MCE_VECTOR 0x12 30 31 /* 32 * IDT vectors usable for external interrupt sources start at 0x20. 33 * (0x80 is the syscall vector, 0x30-0x3f are for ISA) 34 */ 35 #define FIRST_EXTERNAL_VECTOR 0x20 36 /* 37 * We start allocating at 0x21 to spread out vectors evenly between 38 * priority levels. (0x80 is the syscall vector) 39 */ 40 #define VECTOR_OFFSET_START 1 41 42 /* 43 * Reserve the lowest usable vector (and hence lowest priority) 0x20 for 44 * triggering cleanup after irq migration. 0x21-0x2f will still be used 45 * for device interrupts. 46 */ 47 #define IRQ_MOVE_CLEANUP_VECTOR FIRST_EXTERNAL_VECTOR 48 49 #define IA32_SYSCALL_VECTOR 0x80 50 51 /* 52 * Vectors 0x30-0x3f are used for ISA interrupts. 53 * round up to the next 16-vector boundary 54 */ 55 #define IRQ0_VECTOR ((FIRST_EXTERNAL_VECTOR + 16) & ~15) 56 57 #define IRQ1_VECTOR (IRQ0_VECTOR + 1) 58 #define IRQ2_VECTOR (IRQ0_VECTOR + 2) 59 #define IRQ3_VECTOR (IRQ0_VECTOR + 3) 60 #define IRQ4_VECTOR (IRQ0_VECTOR + 4) 61 #define IRQ5_VECTOR (IRQ0_VECTOR + 5) 62 #define IRQ6_VECTOR (IRQ0_VECTOR + 6) 63 #define IRQ7_VECTOR (IRQ0_VECTOR + 7) 64 #define IRQ8_VECTOR (IRQ0_VECTOR + 8) 65 #define IRQ9_VECTOR (IRQ0_VECTOR + 9) 66 #define IRQ10_VECTOR (IRQ0_VECTOR + 10) 67 #define IRQ11_VECTOR (IRQ0_VECTOR + 11) 68 #define IRQ12_VECTOR (IRQ0_VECTOR + 12) 69 #define IRQ13_VECTOR (IRQ0_VECTOR + 13) 70 #define IRQ14_VECTOR (IRQ0_VECTOR + 14) 71 #define IRQ15_VECTOR (IRQ0_VECTOR + 15) 72 73 /* 74 * Special IRQ vectors used by the SMP architecture, 0xf0-0xff 75 * 76 * some of the following vectors are 'rare', they are merged 77 * into a single vector (CALL_FUNCTION_VECTOR) to save vector space. 78 * TLB, reschedule and local APIC vectors are performance-critical. 79 */ 80 81 #define SPURIOUS_APIC_VECTOR 0xff 82 /* 83 * Sanity check 84 */ 85 #if ((SPURIOUS_APIC_VECTOR & 0x0F) != 0x0F) 86 # error SPURIOUS_APIC_VECTOR definition error 87 #endif 88 89 #define ERROR_APIC_VECTOR 0xfe 90 #define RESCHEDULE_VECTOR 0xfd 91 #define CALL_FUNCTION_VECTOR 0xfc 92 #define CALL_FUNCTION_SINGLE_VECTOR 0xfb 93 #define THERMAL_APIC_VECTOR 0xfa 94 #define THRESHOLD_APIC_VECTOR 0xf9 95 #define REBOOT_VECTOR 0xf8 96 97 /* 98 * Generic system vector for platform specific use 99 */ 100 #define X86_PLATFORM_IPI_VECTOR 0xf7 101 102 /* Vector for KVM to deliver posted interrupt IPI */ 103 #ifdef CONFIG_HAVE_KVM 104 #define POSTED_INTR_VECTOR 0xf2 105 #endif 106 107 /* 108 * IRQ work vector: 109 */ 110 #define IRQ_WORK_VECTOR 0xf6 111 112 #define UV_BAU_MESSAGE 0xf5 113 114 /* Vector on which hypervisor callbacks will be delivered */ 115 #define HYPERVISOR_CALLBACK_VECTOR 0xf3 116 117 /* 118 * Local APIC timer IRQ vector is on a different priority level, 119 * to work around the 'lost local interrupt if more than 2 IRQ 120 * sources per level' errata. 121 */ 122 #define LOCAL_TIMER_VECTOR 0xef 123 124 #define NR_VECTORS 256 125 126 #ifdef CONFIG_X86_LOCAL_APIC 127 #define FIRST_SYSTEM_VECTOR LOCAL_TIMER_VECTOR 128 #else 129 #define FIRST_SYSTEM_VECTOR NR_VECTORS 130 #endif 131 132 #define FPU_IRQ 13 133 134 #define FIRST_VM86_IRQ 3 135 #define LAST_VM86_IRQ 15 136 137 #ifndef __ASSEMBLY__ 138 static inline int invalid_vm86_irq(int irq) 139 { 140 return irq < FIRST_VM86_IRQ || irq > LAST_VM86_IRQ; 141 } 142 #endif 143 144 /* 145 * Size the maximum number of interrupts. 146 * 147 * If the irq_desc[] array has a sparse layout, we can size things 148 * generously - it scales up linearly with the maximum number of CPUs, 149 * and the maximum number of IO-APICs, whichever is higher. 150 * 151 * In other cases we size more conservatively, to not create too large 152 * static arrays. 153 */ 154 155 #define NR_IRQS_LEGACY 16 156 157 #define IO_APIC_VECTOR_LIMIT ( 32 * MAX_IO_APICS ) 158 159 #ifdef CONFIG_X86_IO_APIC 160 # define CPU_VECTOR_LIMIT (64 * NR_CPUS) 161 # define NR_IRQS \ 162 (CPU_VECTOR_LIMIT > IO_APIC_VECTOR_LIMIT ? \ 163 (NR_VECTORS + CPU_VECTOR_LIMIT) : \ 164 (NR_VECTORS + IO_APIC_VECTOR_LIMIT)) 165 #else /* !CONFIG_X86_IO_APIC: */ 166 # define NR_IRQS NR_IRQS_LEGACY 167 #endif 168 169 #endif /* _ASM_X86_IRQ_VECTORS_H */ 170