11965aae3SH. Peter Anvin #ifndef _ASM_X86_IRQ_VECTORS_H 21965aae3SH. Peter Anvin #define _ASM_X86_IRQ_VECTORS_H 3bb898558SAl Viro 49fc2e79dSIngo Molnar /* 59fc2e79dSIngo Molnar * Linux IRQ vector layout. 69fc2e79dSIngo Molnar * 79fc2e79dSIngo Molnar * There are 256 IDT entries (per CPU - each entry is 8 bytes) which can 89fc2e79dSIngo Molnar * be defined by Linux. They are used as a jump table by the CPU when a 99fc2e79dSIngo Molnar * given vector is triggered - by a CPU-external, CPU-internal or 109fc2e79dSIngo Molnar * software-triggered event. 119fc2e79dSIngo Molnar * 129fc2e79dSIngo Molnar * Linux sets the kernel code address each entry jumps to early during 139fc2e79dSIngo Molnar * bootup, and never changes them. This is the general layout of the 149fc2e79dSIngo Molnar * IDT entries: 159fc2e79dSIngo Molnar * 169fc2e79dSIngo Molnar * Vectors 0 ... 31 : system traps and exceptions - hardcoded events 179fc2e79dSIngo Molnar * Vectors 32 ... 127 : device interrupts 189fc2e79dSIngo Molnar * Vector 128 : legacy int80 syscall interface 199fc2e79dSIngo Molnar * Vectors 129 ... 237 : device interrupts 209fc2e79dSIngo Molnar * Vectors 238 ... 255 : special interrupts 219fc2e79dSIngo Molnar * 229fc2e79dSIngo Molnar * 64-bit x86 has per CPU IDT tables, 32-bit has one shared IDT table. 239fc2e79dSIngo Molnar * 249fc2e79dSIngo Molnar * This file enumerates the exact layout of them: 259fc2e79dSIngo Molnar */ 269fc2e79dSIngo Molnar 27bb898558SAl Viro #define NMI_VECTOR 0x02 288fa8dd9eSAndi Kleen #define MCE_VECTOR 0x12 29bb898558SAl Viro 30bb898558SAl Viro /* 31bb898558SAl Viro * IDT vectors usable for external interrupt sources start 32bb898558SAl Viro * at 0x20: 3399d113b1SH. Peter Anvin * hpa said we can start from 0x1f. 3499d113b1SH. Peter Anvin * 0x1f is documented as reserved. However, the ability for the APIC 3599d113b1SH. Peter Anvin * to generate vectors starting at 0x10 is documented, as is the 3699d113b1SH. Peter Anvin * ability for the CPU to receive any vector number as an interrupt. 3799d113b1SH. Peter Anvin * 0x1f is used for IRQ_MOVE_CLEANUP_VECTOR since that vector needs 3899d113b1SH. Peter Anvin * an entire privilege level (16 vectors) all by itself at a higher 3999d113b1SH. Peter Anvin * priority than any actual device vector. Thus, by placing it in the 4099d113b1SH. Peter Anvin * otherwise-unusable 0x10 privilege level, we avoid wasting a full 4199d113b1SH. Peter Anvin * 16-vector block. 42bb898558SAl Viro */ 4399d113b1SH. Peter Anvin #define FIRST_EXTERNAL_VECTOR 0x1f 44bb898558SAl Viro 4599d113b1SH. Peter Anvin #define IA32_SYSCALL_VECTOR 0x80 46bb898558SAl Viro #ifdef CONFIG_X86_32 47bb898558SAl Viro # define SYSCALL_VECTOR 0x80 48bb898558SAl Viro #endif 49bb898558SAl Viro 50bb898558SAl Viro /* 5199d113b1SH. Peter Anvin * Reserve the lowest usable priority level 0x10 - 0x1f for triggering 52bb898558SAl Viro * cleanup after irq migration. 5399d113b1SH. Peter Anvin * this overlaps with the reserved range for cpu exceptions so this 5499d113b1SH. Peter Anvin * will need to be changed to 0x20 - 0x2f if the last cpu exception is 5599d113b1SH. Peter Anvin * ever allocated. 56bb898558SAl Viro */ 5799d113b1SH. Peter Anvin 58bb898558SAl Viro #define IRQ_MOVE_CLEANUP_VECTOR FIRST_EXTERNAL_VECTOR 59bb898558SAl Viro 60bb898558SAl Viro /* 6199d113b1SH. Peter Anvin * Vectors 0x20-0x2f are used for ISA interrupts. 6299d113b1SH. Peter Anvin * round up to the next 16-vector boundary 63bb898558SAl Viro */ 6499d113b1SH. Peter Anvin #define IRQ0_VECTOR ((FIRST_EXTERNAL_VECTOR + 16) & ~15) 659fc2e79dSIngo Molnar 66bb898558SAl Viro #define IRQ1_VECTOR (IRQ0_VECTOR + 1) 67bb898558SAl Viro #define IRQ2_VECTOR (IRQ0_VECTOR + 2) 68bb898558SAl Viro #define IRQ3_VECTOR (IRQ0_VECTOR + 3) 69bb898558SAl Viro #define IRQ4_VECTOR (IRQ0_VECTOR + 4) 70bb898558SAl Viro #define IRQ5_VECTOR (IRQ0_VECTOR + 5) 71bb898558SAl Viro #define IRQ6_VECTOR (IRQ0_VECTOR + 6) 72bb898558SAl Viro #define IRQ7_VECTOR (IRQ0_VECTOR + 7) 73bb898558SAl Viro #define IRQ8_VECTOR (IRQ0_VECTOR + 8) 74bb898558SAl Viro #define IRQ9_VECTOR (IRQ0_VECTOR + 9) 75bb898558SAl Viro #define IRQ10_VECTOR (IRQ0_VECTOR + 10) 76bb898558SAl Viro #define IRQ11_VECTOR (IRQ0_VECTOR + 11) 77bb898558SAl Viro #define IRQ12_VECTOR (IRQ0_VECTOR + 12) 78bb898558SAl Viro #define IRQ13_VECTOR (IRQ0_VECTOR + 13) 79bb898558SAl Viro #define IRQ14_VECTOR (IRQ0_VECTOR + 14) 80bb898558SAl Viro #define IRQ15_VECTOR (IRQ0_VECTOR + 15) 81bb898558SAl Viro 82bb898558SAl Viro /* 83bb898558SAl Viro * Special IRQ vectors used by the SMP architecture, 0xf0-0xff 84bb898558SAl Viro * 85bb898558SAl Viro * some of the following vectors are 'rare', they are merged 86bb898558SAl Viro * into a single vector (CALL_FUNCTION_VECTOR) to save vector space. 87bb898558SAl Viro * TLB, reschedule and local APIC vectors are performance-critical. 88bb898558SAl Viro */ 895da690d2SIngo Molnar 905da690d2SIngo Molnar #define SPURIOUS_APIC_VECTOR 0xff 91647ad94fSIngo Molnar /* 92647ad94fSIngo Molnar * Sanity check 93647ad94fSIngo Molnar */ 94647ad94fSIngo Molnar #if ((SPURIOUS_APIC_VECTOR & 0x0F) != 0x0F) 95647ad94fSIngo Molnar # error SPURIOUS_APIC_VECTOR definition error 96647ad94fSIngo Molnar #endif 97647ad94fSIngo Molnar 985da690d2SIngo Molnar #define ERROR_APIC_VECTOR 0xfe 995da690d2SIngo Molnar #define RESCHEDULE_VECTOR 0xfd 1005da690d2SIngo Molnar #define CALL_FUNCTION_VECTOR 0xfc 1015da690d2SIngo Molnar #define CALL_FUNCTION_SINGLE_VECTOR 0xfb 1025da690d2SIngo Molnar #define THERMAL_APIC_VECTOR 0xfa 103bb898558SAl Viro #define THRESHOLD_APIC_VECTOR 0xf9 1044ef702c1SAndi Kleen #define REBOOT_VECTOR 0xf8 105bb898558SAl Viro 1065da690d2SIngo Molnar /* f0-f7 used for spreading out TLB flushes: */ 1075da690d2SIngo Molnar #define INVALIDATE_TLB_VECTOR_END 0xf7 1085da690d2SIngo Molnar #define INVALIDATE_TLB_VECTOR_START 0xf0 1095da690d2SIngo Molnar #define NUM_INVALIDATE_TLB_VECTORS 8 1105da690d2SIngo Molnar 111bb898558SAl Viro /* 112bb898558SAl Viro * Local APIC timer IRQ vector is on a different priority level, 113bb898558SAl Viro * to work around the 'lost local interrupt if more than 2 IRQ 114bb898558SAl Viro * sources per level' errata. 115bb898558SAl Viro */ 116bb898558SAl Viro #define LOCAL_TIMER_VECTOR 0xef 117bb898558SAl Viro 118bb898558SAl Viro /* 119acaabe79SDimitri Sivanich * Generic system vector for platform specific use 120acaabe79SDimitri Sivanich */ 1214a4de9c7SDimitri Sivanich #define X86_PLATFORM_IPI_VECTOR 0xed 122acaabe79SDimitri Sivanich 123acaabe79SDimitri Sivanich /* 124b6276f35SPeter Zijlstra * Performance monitoring pending work vector: 125b6276f35SPeter Zijlstra */ 126b6276f35SPeter Zijlstra #define LOCAL_PENDING_VECTOR 0xec 127b6276f35SPeter Zijlstra 1281d865fb7SCliff Wickman #define UV_BAU_MESSAGE 0xea 1294ef702c1SAndi Kleen 130bb898558SAl Viro /* 131ccc3c319SAndi Kleen * Self IPI vector for machine checks 132ccc3c319SAndi Kleen */ 133ccc3c319SAndi Kleen #define MCE_SELF_VECTOR 0xeb 134ccc3c319SAndi Kleen 135ccc3c319SAndi Kleen /* 136bb898558SAl Viro * First APIC vector available to drivers: (vectors 0x30-0xee) we 13799d113b1SH. Peter Anvin * start at 0x31 to spread out vectors evenly between priority 138bb898558SAl Viro * levels. (0x80 is the syscall vector) 139bb898558SAl Viro */ 140bb898558SAl Viro #define FIRST_DEVICE_VECTOR (IRQ15_VECTOR + 2) 141bb898558SAl Viro 142bb898558SAl Viro #define NR_VECTORS 256 143bb898558SAl Viro 144bb898558SAl Viro #define FPU_IRQ 13 145bb898558SAl Viro 146bb898558SAl Viro #define FIRST_VM86_IRQ 3 147bb898558SAl Viro #define LAST_VM86_IRQ 15 148d8106d2eSIngo Molnar 149d8106d2eSIngo Molnar #ifndef __ASSEMBLY__ 150d8106d2eSIngo Molnar static inline int invalid_vm86_irq(int irq) 151d8106d2eSIngo Molnar { 15257e37293SCyrill Gorcunov return irq < FIRST_VM86_IRQ || irq > LAST_VM86_IRQ; 153d8106d2eSIngo Molnar } 154d8106d2eSIngo Molnar #endif 155bb898558SAl Viro 156009eb3feSIngo Molnar /* 157009eb3feSIngo Molnar * Size the maximum number of interrupts. 158009eb3feSIngo Molnar * 159009eb3feSIngo Molnar * If the irq_desc[] array has a sparse layout, we can size things 160009eb3feSIngo Molnar * generously - it scales up linearly with the maximum number of CPUs, 161009eb3feSIngo Molnar * and the maximum number of IO-APICs, whichever is higher. 162009eb3feSIngo Molnar * 163009eb3feSIngo Molnar * In other cases we size more conservatively, to not create too large 164009eb3feSIngo Molnar * static arrays. 165009eb3feSIngo Molnar */ 166009eb3feSIngo Molnar 16799d093d1SYinghai Lu #define NR_IRQS_LEGACY 16 16899d093d1SYinghai Lu 169009eb3feSIngo Molnar #define IO_APIC_VECTOR_LIMIT ( 32 * MAX_IO_APICS ) 170009eb3feSIngo Molnar 1713e92ab3dSIngo Molnar #ifdef CONFIG_X86_IO_APIC 172009eb3feSIngo Molnar # ifdef CONFIG_SPARSE_IRQ 1739959c888SYinghai Lu # define CPU_VECTOR_LIMIT (64 * NR_CPUS) 1744a046d17SYinghai Lu # define NR_IRQS \ 175009eb3feSIngo Molnar (CPU_VECTOR_LIMIT > IO_APIC_VECTOR_LIMIT ? \ 176009eb3feSIngo Molnar (NR_VECTORS + CPU_VECTOR_LIMIT) : \ 177009eb3feSIngo Molnar (NR_VECTORS + IO_APIC_VECTOR_LIMIT)) 178009eb3feSIngo Molnar # else 1799959c888SYinghai Lu # define CPU_VECTOR_LIMIT (32 * NR_CPUS) 1809959c888SYinghai Lu # define NR_IRQS \ 1819959c888SYinghai Lu (CPU_VECTOR_LIMIT < IO_APIC_VECTOR_LIMIT ? \ 1829959c888SYinghai Lu (NR_VECTORS + CPU_VECTOR_LIMIT) : \ 1839959c888SYinghai Lu (NR_VECTORS + IO_APIC_VECTOR_LIMIT)) 1840b8f1efaSYinghai Lu # endif 1853e92ab3dSIngo Molnar #else /* !CONFIG_X86_IO_APIC: */ 186009eb3feSIngo Molnar # define NR_IRQS NR_IRQS_LEGACY 187bb898558SAl Viro #endif 188bb898558SAl Viro 1891965aae3SH. Peter Anvin #endif /* _ASM_X86_IRQ_VECTORS_H */ 190