11965aae3SH. Peter Anvin #ifndef _ASM_X86_IRQ_VECTORS_H 21965aae3SH. Peter Anvin #define _ASM_X86_IRQ_VECTORS_H 3bb898558SAl Viro 460f6e65dSShaohua Li #include <linux/threads.h> 59fc2e79dSIngo Molnar /* 69fc2e79dSIngo Molnar * Linux IRQ vector layout. 79fc2e79dSIngo Molnar * 89fc2e79dSIngo Molnar * There are 256 IDT entries (per CPU - each entry is 8 bytes) which can 99fc2e79dSIngo Molnar * be defined by Linux. They are used as a jump table by the CPU when a 109fc2e79dSIngo Molnar * given vector is triggered - by a CPU-external, CPU-internal or 119fc2e79dSIngo Molnar * software-triggered event. 129fc2e79dSIngo Molnar * 139fc2e79dSIngo Molnar * Linux sets the kernel code address each entry jumps to early during 149fc2e79dSIngo Molnar * bootup, and never changes them. This is the general layout of the 159fc2e79dSIngo Molnar * IDT entries: 169fc2e79dSIngo Molnar * 179fc2e79dSIngo Molnar * Vectors 0 ... 31 : system traps and exceptions - hardcoded events 189fc2e79dSIngo Molnar * Vectors 32 ... 127 : device interrupts 199fc2e79dSIngo Molnar * Vector 128 : legacy int80 syscall interface 205cec93c2SAndy Lutomirski * Vectors 129 ... INVALIDATE_TLB_VECTOR_START-1 except 204 : device interrupts 2170e4a369SShaohua Li * Vectors INVALIDATE_TLB_VECTOR_START ... 255 : special interrupts 229fc2e79dSIngo Molnar * 239fc2e79dSIngo Molnar * 64-bit x86 has per CPU IDT tables, 32-bit has one shared IDT table. 249fc2e79dSIngo Molnar * 259fc2e79dSIngo Molnar * This file enumerates the exact layout of them: 269fc2e79dSIngo Molnar */ 279fc2e79dSIngo Molnar 28bb898558SAl Viro #define NMI_VECTOR 0x02 298fa8dd9eSAndi Kleen #define MCE_VECTOR 0x12 30bb898558SAl Viro 31bb898558SAl Viro /* 326579b474SSuresh Siddha * IDT vectors usable for external interrupt sources start at 0x20. 336579b474SSuresh Siddha * (0x80 is the syscall vector, 0x30-0x3f are for ISA) 34bb898558SAl Viro */ 356579b474SSuresh Siddha #define FIRST_EXTERNAL_VECTOR 0x20 366579b474SSuresh Siddha /* 376579b474SSuresh Siddha * We start allocating at 0x21 to spread out vectors evenly between 386579b474SSuresh Siddha * priority levels. (0x80 is the syscall vector) 396579b474SSuresh Siddha */ 406579b474SSuresh Siddha #define VECTOR_OFFSET_START 1 416579b474SSuresh Siddha 426579b474SSuresh Siddha /* 436579b474SSuresh Siddha * Reserve the lowest usable vector (and hence lowest priority) 0x20 for 446579b474SSuresh Siddha * triggering cleanup after irq migration. 0x21-0x2f will still be used 456579b474SSuresh Siddha * for device interrupts. 466579b474SSuresh Siddha */ 476579b474SSuresh Siddha #define IRQ_MOVE_CLEANUP_VECTOR FIRST_EXTERNAL_VECTOR 48bb898558SAl Viro 4999d113b1SH. Peter Anvin #define IA32_SYSCALL_VECTOR 0x80 50bb898558SAl Viro 51bb898558SAl Viro /* 526579b474SSuresh Siddha * Vectors 0x30-0x3f are used for ISA interrupts. 5399d113b1SH. Peter Anvin * round up to the next 16-vector boundary 54bb898558SAl Viro */ 558b455e65SBrian Gerst #define ISA_IRQ_VECTOR(irq) (((FIRST_EXTERNAL_VECTOR + 16) & ~15) + irq) 56bb898558SAl Viro 57bb898558SAl Viro /* 58bb898558SAl Viro * Special IRQ vectors used by the SMP architecture, 0xf0-0xff 59bb898558SAl Viro * 60bb898558SAl Viro * some of the following vectors are 'rare', they are merged 61bb898558SAl Viro * into a single vector (CALL_FUNCTION_VECTOR) to save vector space. 62bb898558SAl Viro * TLB, reschedule and local APIC vectors are performance-critical. 63bb898558SAl Viro */ 645da690d2SIngo Molnar 655da690d2SIngo Molnar #define SPURIOUS_APIC_VECTOR 0xff 66647ad94fSIngo Molnar /* 67647ad94fSIngo Molnar * Sanity check 68647ad94fSIngo Molnar */ 69647ad94fSIngo Molnar #if ((SPURIOUS_APIC_VECTOR & 0x0F) != 0x0F) 70647ad94fSIngo Molnar # error SPURIOUS_APIC_VECTOR definition error 71647ad94fSIngo Molnar #endif 72647ad94fSIngo Molnar 735da690d2SIngo Molnar #define ERROR_APIC_VECTOR 0xfe 745da690d2SIngo Molnar #define RESCHEDULE_VECTOR 0xfd 755da690d2SIngo Molnar #define CALL_FUNCTION_VECTOR 0xfc 765da690d2SIngo Molnar #define CALL_FUNCTION_SINGLE_VECTOR 0xfb 775da690d2SIngo Molnar #define THERMAL_APIC_VECTOR 0xfa 78bb898558SAl Viro #define THRESHOLD_APIC_VECTOR 0xf9 794ef702c1SAndi Kleen #define REBOOT_VECTOR 0xf8 80bb898558SAl Viro 8160f6e65dSShaohua Li /* 8260f6e65dSShaohua Li * Generic system vector for platform specific use 8360f6e65dSShaohua Li */ 8460f6e65dSShaohua Li #define X86_PLATFORM_IPI_VECTOR 0xf7 8560f6e65dSShaohua Li 86d78f2664SYang Zhang /* Vector for KVM to deliver posted interrupt IPI */ 87d78f2664SYang Zhang #ifdef CONFIG_HAVE_KVM 88d78f2664SYang Zhang #define POSTED_INTR_VECTOR 0xf2 89d78f2664SYang Zhang #endif 90d78f2664SYang Zhang 9160f6e65dSShaohua Li /* 9260f6e65dSShaohua Li * IRQ work vector: 9360f6e65dSShaohua Li */ 9460f6e65dSShaohua Li #define IRQ_WORK_VECTOR 0xf6 9560f6e65dSShaohua Li 9660f6e65dSShaohua Li #define UV_BAU_MESSAGE 0xf5 9760f6e65dSShaohua Li 98bc2b0331SK. Y. Srinivasan /* Vector on which hypervisor callbacks will be delivered */ 99bc2b0331SK. Y. Srinivasan #define HYPERVISOR_CALLBACK_VECTOR 0xf3 1005da690d2SIngo Molnar 101bb898558SAl Viro /* 102bb898558SAl Viro * Local APIC timer IRQ vector is on a different priority level, 103bb898558SAl Viro * to work around the 'lost local interrupt if more than 2 IRQ 104bb898558SAl Viro * sources per level' errata. 105bb898558SAl Viro */ 106bb898558SAl Viro #define LOCAL_TIMER_VECTOR 0xef 107bb898558SAl Viro 108bb898558SAl Viro #define NR_VECTORS 256 109bb898558SAl Viro 1102414e021SJan Beulich #ifdef CONFIG_X86_LOCAL_APIC 1112414e021SJan Beulich #define FIRST_SYSTEM_VECTOR LOCAL_TIMER_VECTOR 1122414e021SJan Beulich #else 1132414e021SJan Beulich #define FIRST_SYSTEM_VECTOR NR_VECTORS 1142414e021SJan Beulich #endif 1152414e021SJan Beulich 116bb898558SAl Viro #define FPU_IRQ 13 117bb898558SAl Viro 118bb898558SAl Viro #define FIRST_VM86_IRQ 3 119bb898558SAl Viro #define LAST_VM86_IRQ 15 120d8106d2eSIngo Molnar 121d8106d2eSIngo Molnar #ifndef __ASSEMBLY__ 122d8106d2eSIngo Molnar static inline int invalid_vm86_irq(int irq) 123d8106d2eSIngo Molnar { 12457e37293SCyrill Gorcunov return irq < FIRST_VM86_IRQ || irq > LAST_VM86_IRQ; 125d8106d2eSIngo Molnar } 126d8106d2eSIngo Molnar #endif 127bb898558SAl Viro 128009eb3feSIngo Molnar /* 129009eb3feSIngo Molnar * Size the maximum number of interrupts. 130009eb3feSIngo Molnar * 131009eb3feSIngo Molnar * If the irq_desc[] array has a sparse layout, we can size things 132009eb3feSIngo Molnar * generously - it scales up linearly with the maximum number of CPUs, 133009eb3feSIngo Molnar * and the maximum number of IO-APICs, whichever is higher. 134009eb3feSIngo Molnar * 135009eb3feSIngo Molnar * In other cases we size more conservatively, to not create too large 136009eb3feSIngo Molnar * static arrays. 137009eb3feSIngo Molnar */ 138009eb3feSIngo Molnar 13999d093d1SYinghai Lu #define NR_IRQS_LEGACY 16 14099d093d1SYinghai Lu 141009eb3feSIngo Molnar #define IO_APIC_VECTOR_LIMIT ( 32 * MAX_IO_APICS ) 142009eb3feSIngo Molnar 1433e92ab3dSIngo Molnar #ifdef CONFIG_X86_IO_APIC 1449959c888SYinghai Lu # define CPU_VECTOR_LIMIT (64 * NR_CPUS) 1454a046d17SYinghai Lu # define NR_IRQS \ 146009eb3feSIngo Molnar (CPU_VECTOR_LIMIT > IO_APIC_VECTOR_LIMIT ? \ 147009eb3feSIngo Molnar (NR_VECTORS + CPU_VECTOR_LIMIT) : \ 148009eb3feSIngo Molnar (NR_VECTORS + IO_APIC_VECTOR_LIMIT)) 1493e92ab3dSIngo Molnar #else /* !CONFIG_X86_IO_APIC: */ 150009eb3feSIngo Molnar # define NR_IRQS NR_IRQS_LEGACY 151bb898558SAl Viro #endif 152bb898558SAl Viro 1531965aae3SH. Peter Anvin #endif /* _ASM_X86_IRQ_VECTORS_H */ 154