1b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */ 21965aae3SH. Peter Anvin #ifndef _ASM_X86_IRQ_VECTORS_H 31965aae3SH. Peter Anvin #define _ASM_X86_IRQ_VECTORS_H 4bb898558SAl Viro 560f6e65dSShaohua Li #include <linux/threads.h> 69fc2e79dSIngo Molnar /* 79fc2e79dSIngo Molnar * Linux IRQ vector layout. 89fc2e79dSIngo Molnar * 99fc2e79dSIngo Molnar * There are 256 IDT entries (per CPU - each entry is 8 bytes) which can 109fc2e79dSIngo Molnar * be defined by Linux. They are used as a jump table by the CPU when a 119fc2e79dSIngo Molnar * given vector is triggered - by a CPU-external, CPU-internal or 129fc2e79dSIngo Molnar * software-triggered event. 139fc2e79dSIngo Molnar * 149fc2e79dSIngo Molnar * Linux sets the kernel code address each entry jumps to early during 159fc2e79dSIngo Molnar * bootup, and never changes them. This is the general layout of the 169fc2e79dSIngo Molnar * IDT entries: 179fc2e79dSIngo Molnar * 189fc2e79dSIngo Molnar * Vectors 0 ... 31 : system traps and exceptions - hardcoded events 199fc2e79dSIngo Molnar * Vectors 32 ... 127 : device interrupts 209fc2e79dSIngo Molnar * Vector 128 : legacy int80 syscall interface 212c464543SJiang Biao * Vectors 129 ... LOCAL_TIMER_VECTOR-1 222c464543SJiang Biao * Vectors LOCAL_TIMER_VECTOR ... 255 : special interrupts 239fc2e79dSIngo Molnar * 249fc2e79dSIngo Molnar * 64-bit x86 has per CPU IDT tables, 32-bit has one shared IDT table. 259fc2e79dSIngo Molnar * 269fc2e79dSIngo Molnar * This file enumerates the exact layout of them: 279fc2e79dSIngo Molnar */ 289fc2e79dSIngo Molnar 29f1b7d45dSH. Peter Anvin (Intel) /* This is used as an interrupt vector when programming the APIC. */ 30bb898558SAl Viro #define NMI_VECTOR 0x02 31bb898558SAl Viro 32bb898558SAl Viro /* 336579b474SSuresh Siddha * IDT vectors usable for external interrupt sources start at 0x20. 346579b474SSuresh Siddha * (0x80 is the syscall vector, 0x30-0x3f are for ISA) 35bb898558SAl Viro */ 366579b474SSuresh Siddha #define FIRST_EXTERNAL_VECTOR 0x20 376579b474SSuresh Siddha 3899d113b1SH. Peter Anvin #define IA32_SYSCALL_VECTOR 0x80 39bb898558SAl Viro 40bb898558SAl Viro /* 416579b474SSuresh Siddha * Vectors 0x30-0x3f are used for ISA interrupts. 4299d113b1SH. Peter Anvin * round up to the next 16-vector boundary 43bb898558SAl Viro */ 448b455e65SBrian Gerst #define ISA_IRQ_VECTOR(irq) (((FIRST_EXTERNAL_VECTOR + 16) & ~15) + irq) 45bb898558SAl Viro 46bb898558SAl Viro /* 47bb898558SAl Viro * Special IRQ vectors used by the SMP architecture, 0xf0-0xff 48bb898558SAl Viro * 49bb898558SAl Viro * some of the following vectors are 'rare', they are merged 50bb898558SAl Viro * into a single vector (CALL_FUNCTION_VECTOR) to save vector space. 51bb898558SAl Viro * TLB, reschedule and local APIC vectors are performance-critical. 52bb898558SAl Viro */ 535da690d2SIngo Molnar 545da690d2SIngo Molnar #define SPURIOUS_APIC_VECTOR 0xff 55647ad94fSIngo Molnar /* 56647ad94fSIngo Molnar * Sanity check 57647ad94fSIngo Molnar */ 58647ad94fSIngo Molnar #if ((SPURIOUS_APIC_VECTOR & 0x0F) != 0x0F) 59647ad94fSIngo Molnar # error SPURIOUS_APIC_VECTOR definition error 60647ad94fSIngo Molnar #endif 61647ad94fSIngo Molnar 625da690d2SIngo Molnar #define ERROR_APIC_VECTOR 0xfe 635da690d2SIngo Molnar #define RESCHEDULE_VECTOR 0xfd 645da690d2SIngo Molnar #define CALL_FUNCTION_VECTOR 0xfc 655da690d2SIngo Molnar #define CALL_FUNCTION_SINGLE_VECTOR 0xfb 665da690d2SIngo Molnar #define THERMAL_APIC_VECTOR 0xfa 67bb898558SAl Viro #define THRESHOLD_APIC_VECTOR 0xf9 684ef702c1SAndi Kleen #define REBOOT_VECTOR 0xf8 69bb898558SAl Viro 7060f6e65dSShaohua Li /* 7160f6e65dSShaohua Li * Generic system vector for platform specific use 7260f6e65dSShaohua Li */ 7360f6e65dSShaohua Li #define X86_PLATFORM_IPI_VECTOR 0xf7 7460f6e65dSShaohua Li 7560f6e65dSShaohua Li /* 7660f6e65dSShaohua Li * IRQ work vector: 7760f6e65dSShaohua Li */ 7860f6e65dSShaohua Li #define IRQ_WORK_VECTOR 0xf6 7960f6e65dSShaohua Li 80f1b7d45dSH. Peter Anvin (Intel) /* 0xf5 - unused, was UV_BAU_MESSAGE */ 8124fd78a8SAravind Gopalakrishnan #define DEFERRED_ERROR_VECTOR 0xf4 8260f6e65dSShaohua Li 83bc2b0331SK. Y. Srinivasan /* Vector on which hypervisor callbacks will be delivered */ 84bc2b0331SK. Y. Srinivasan #define HYPERVISOR_CALLBACK_VECTOR 0xf3 855da690d2SIngo Molnar 865c0d728eSAravind Gopalakrishnan /* Vector for KVM to deliver posted interrupt IPI */ 875c0d728eSAravind Gopalakrishnan #ifdef CONFIG_HAVE_KVM 885c0d728eSAravind Gopalakrishnan #define POSTED_INTR_VECTOR 0xf2 89210f84b0SWincy Van #define POSTED_INTR_WAKEUP_VECTOR 0xf1 90210f84b0SWincy Van #define POSTED_INTR_NESTED_VECTOR 0xf0 915c0d728eSAravind Gopalakrishnan #endif 925c0d728eSAravind Gopalakrishnan 932db1f959SThomas Gleixner #define MANAGED_IRQ_SHUTDOWN_VECTOR 0xef 9493286261SVitaly Kuznetsov 9593286261SVitaly Kuznetsov #if IS_ENABLED(CONFIG_HYPERV) 9693286261SVitaly Kuznetsov #define HYPERV_REENLIGHTENMENT_VECTOR 0xee 97248e742aSMichael Kelley #define HYPERV_STIMER0_VECTOR 0xed 9893286261SVitaly Kuznetsov #endif 9993286261SVitaly Kuznetsov 100248e742aSMichael Kelley #define LOCAL_TIMER_VECTOR 0xec 101bb898558SAl Viro 102bb898558SAl Viro #define NR_VECTORS 256 103bb898558SAl Viro 1042414e021SJan Beulich #ifdef CONFIG_X86_LOCAL_APIC 1052414e021SJan Beulich #define FIRST_SYSTEM_VECTOR LOCAL_TIMER_VECTOR 1062414e021SJan Beulich #else 1072414e021SJan Beulich #define FIRST_SYSTEM_VECTOR NR_VECTORS 1082414e021SJan Beulich #endif 1092414e021SJan Beulich 110*ff851003SH. Peter Anvin (Intel) #define NR_EXTERNAL_VECTORS (FIRST_SYSTEM_VECTOR - FIRST_EXTERNAL_VECTOR) 111*ff851003SH. Peter Anvin (Intel) #define NR_SYSTEM_VECTORS (NR_VECTORS - FIRST_SYSTEM_VECTOR) 112*ff851003SH. Peter Anvin (Intel) 113009eb3feSIngo Molnar /* 114009eb3feSIngo Molnar * Size the maximum number of interrupts. 115009eb3feSIngo Molnar * 116009eb3feSIngo Molnar * If the irq_desc[] array has a sparse layout, we can size things 117009eb3feSIngo Molnar * generously - it scales up linearly with the maximum number of CPUs, 118009eb3feSIngo Molnar * and the maximum number of IO-APICs, whichever is higher. 119009eb3feSIngo Molnar * 120009eb3feSIngo Molnar * In other cases we size more conservatively, to not create too large 121009eb3feSIngo Molnar * static arrays. 122009eb3feSIngo Molnar */ 123009eb3feSIngo Molnar 12499d093d1SYinghai Lu #define NR_IRQS_LEGACY 16 12599d093d1SYinghai Lu 1264399b14fSJiang Liu #define CPU_VECTOR_LIMIT (64 * NR_CPUS) 127009eb3feSIngo Molnar #define IO_APIC_VECTOR_LIMIT (32 * MAX_IO_APICS) 128009eb3feSIngo Molnar 1294399b14fSJiang Liu #if defined(CONFIG_X86_IO_APIC) && defined(CONFIG_PCI_MSI) 1304a046d17SYinghai Lu #define NR_IRQS \ 131009eb3feSIngo Molnar (CPU_VECTOR_LIMIT > IO_APIC_VECTOR_LIMIT ? \ 132009eb3feSIngo Molnar (NR_VECTORS + CPU_VECTOR_LIMIT) : \ 133009eb3feSIngo Molnar (NR_VECTORS + IO_APIC_VECTOR_LIMIT)) 1344399b14fSJiang Liu #elif defined(CONFIG_X86_IO_APIC) 1354399b14fSJiang Liu #define NR_IRQS (NR_VECTORS + IO_APIC_VECTOR_LIMIT) 1364399b14fSJiang Liu #elif defined(CONFIG_PCI_MSI) 1374399b14fSJiang Liu #define NR_IRQS (NR_VECTORS + CPU_VECTOR_LIMIT) 1384399b14fSJiang Liu #else 139009eb3feSIngo Molnar #define NR_IRQS NR_IRQS_LEGACY 140bb898558SAl Viro #endif 141bb898558SAl Viro 1421965aae3SH. Peter Anvin #endif /* _ASM_X86_IRQ_VECTORS_H */ 143