1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _ASM_X86_IO_APIC_H 3 #define _ASM_X86_IO_APIC_H 4 5 #include <linux/types.h> 6 #include <asm/mpspec.h> 7 #include <asm/apicdef.h> 8 #include <asm/irq_vectors.h> 9 #include <asm/x86_init.h> 10 /* 11 * Intel IO-APIC support for SMP and UP systems. 12 * 13 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar 14 */ 15 16 /* 17 * The structure of the IO-APIC: 18 */ 19 union IO_APIC_reg_00 { 20 u32 raw; 21 struct { 22 u32 __reserved_2 : 14, 23 LTS : 1, 24 delivery_type : 1, 25 __reserved_1 : 8, 26 ID : 8; 27 } __attribute__ ((packed)) bits; 28 }; 29 30 union IO_APIC_reg_01 { 31 u32 raw; 32 struct { 33 u32 version : 8, 34 __reserved_2 : 7, 35 PRQ : 1, 36 entries : 8, 37 __reserved_1 : 8; 38 } __attribute__ ((packed)) bits; 39 }; 40 41 union IO_APIC_reg_02 { 42 u32 raw; 43 struct { 44 u32 __reserved_2 : 24, 45 arbitration : 4, 46 __reserved_1 : 4; 47 } __attribute__ ((packed)) bits; 48 }; 49 50 union IO_APIC_reg_03 { 51 u32 raw; 52 struct { 53 u32 boot_DT : 1, 54 __reserved_1 : 31; 55 } __attribute__ ((packed)) bits; 56 }; 57 58 struct IO_APIC_route_entry { 59 union { 60 struct { 61 u64 vector : 8, 62 delivery_mode : 3, 63 dest_mode_logical : 1, 64 delivery_status : 1, 65 active_low : 1, 66 irr : 1, 67 is_level : 1, 68 masked : 1, 69 reserved_0 : 15, 70 reserved_1 : 17, 71 virt_destid_8_14 : 7, 72 destid_0_7 : 8; 73 }; 74 struct { 75 u64 ir_shared_0 : 8, 76 ir_zero : 3, 77 ir_index_15 : 1, 78 ir_shared_1 : 5, 79 ir_reserved_0 : 31, 80 ir_format : 1, 81 ir_index_0_14 : 15; 82 }; 83 struct { 84 u64 w1 : 32, 85 w2 : 32; 86 }; 87 }; 88 } __attribute__ ((packed)); 89 90 struct irq_alloc_info; 91 struct ioapic_domain_cfg; 92 93 #define IOAPIC_MAP_ALLOC 0x1 94 #define IOAPIC_MAP_CHECK 0x2 95 96 #ifdef CONFIG_X86_IO_APIC 97 98 /* 99 * # of IO-APICs and # of IRQ routing registers 100 */ 101 extern int nr_ioapics; 102 103 extern int mpc_ioapic_id(int ioapic); 104 extern unsigned int mpc_ioapic_addr(int ioapic); 105 106 /* # of MP IRQ source entries */ 107 extern int mp_irq_entries; 108 109 /* MP IRQ source entries */ 110 extern struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES]; 111 112 /* True if "noapic" boot option passed */ 113 extern bool ioapic_is_disabled; 114 115 /* 1 if "noapic" boot option passed */ 116 extern int noioapicquirk; 117 118 /* -1 if "noapic" boot option passed */ 119 extern int noioapicreroute; 120 121 extern u32 gsi_top; 122 123 extern unsigned long io_apic_irqs; 124 125 #define IO_APIC_IRQ(x) (((x) >= NR_IRQS_LEGACY) || ((1 << (x)) & io_apic_irqs)) 126 127 /* 128 * If we use the IO-APIC for IRQ routing, disable automatic 129 * assignment of PCI IRQ's. 130 */ 131 #define io_apic_assign_pci_irqs \ 132 (mp_irq_entries && !ioapic_is_disabled && io_apic_irqs) 133 134 struct irq_cfg; 135 extern void ioapic_insert_resources(void); 136 extern int arch_early_ioapic_init(void); 137 138 extern int save_ioapic_entries(void); 139 extern void mask_ioapic_entries(void); 140 extern int restore_ioapic_entries(void); 141 142 extern void setup_ioapic_ids_from_mpc(void); 143 extern void setup_ioapic_ids_from_mpc_nocheck(void); 144 145 extern int mp_find_ioapic(u32 gsi); 146 extern int mp_find_ioapic_pin(int ioapic, u32 gsi); 147 extern int mp_map_gsi_to_irq(u32 gsi, unsigned int flags, 148 struct irq_alloc_info *info); 149 extern void mp_unmap_irq(int irq); 150 extern int mp_register_ioapic(int id, u32 address, u32 gsi_base, 151 struct ioapic_domain_cfg *cfg); 152 extern int mp_unregister_ioapic(u32 gsi_base); 153 extern int mp_ioapic_registered(u32 gsi_base); 154 155 extern void ioapic_set_alloc_attr(struct irq_alloc_info *info, 156 int node, int trigger, int polarity); 157 158 extern void mp_save_irq(struct mpc_intsrc *m); 159 160 extern void disable_ioapic_support(void); 161 162 extern void __init io_apic_init_mappings(void); 163 extern unsigned int native_io_apic_read(unsigned int apic, unsigned int reg); 164 extern void native_restore_boot_irq_mode(void); 165 166 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg) 167 { 168 return x86_apic_ops.io_apic_read(apic, reg); 169 } 170 171 extern void setup_IO_APIC(void); 172 extern void enable_IO_APIC(void); 173 extern void clear_IO_APIC(void); 174 extern void restore_boot_irq_mode(void); 175 extern int IO_APIC_get_PCI_irq_vector(int bus, int devfn, int pin); 176 extern void print_IO_APICs(void); 177 #else /* !CONFIG_X86_IO_APIC */ 178 179 #define IO_APIC_IRQ(x) 0 180 #define io_apic_assign_pci_irqs 0 181 #define setup_ioapic_ids_from_mpc x86_init_noop 182 #define nr_ioapics (0) 183 static inline void ioapic_insert_resources(void) { } 184 static inline int arch_early_ioapic_init(void) { return 0; } 185 static inline void print_IO_APICs(void) {} 186 #define gsi_top (NR_IRQS_LEGACY) 187 static inline int mp_find_ioapic(u32 gsi) { return 0; } 188 static inline int mp_map_gsi_to_irq(u32 gsi, unsigned int flags, 189 struct irq_alloc_info *info) 190 { 191 return gsi; 192 } 193 194 static inline void mp_unmap_irq(int irq) { } 195 196 static inline int save_ioapic_entries(void) 197 { 198 return -ENOMEM; 199 } 200 201 static inline void mask_ioapic_entries(void) { } 202 static inline int restore_ioapic_entries(void) 203 { 204 return -ENOMEM; 205 } 206 207 static inline void mp_save_irq(struct mpc_intsrc *m) { } 208 static inline void disable_ioapic_support(void) { } 209 static inline void io_apic_init_mappings(void) { } 210 #define native_io_apic_read NULL 211 #define native_restore_boot_irq_mode NULL 212 213 static inline void setup_IO_APIC(void) { } 214 static inline void enable_IO_APIC(void) { } 215 static inline void restore_boot_irq_mode(void) { } 216 217 #endif 218 219 #endif /* _ASM_X86_IO_APIC_H */ 220