1 #ifndef _ASM_X86_IO_APIC_H 2 #define _ASM_X86_IO_APIC_H 3 4 #include <linux/types.h> 5 #include <asm/mpspec.h> 6 #include <asm/apicdef.h> 7 #include <asm/irq_vectors.h> 8 9 /* 10 * Intel IO-APIC support for SMP and UP systems. 11 * 12 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar 13 */ 14 15 /* I/O Unit Redirection Table */ 16 #define IO_APIC_REDIR_VECTOR_MASK 0x000FF 17 #define IO_APIC_REDIR_DEST_LOGICAL 0x00800 18 #define IO_APIC_REDIR_DEST_PHYSICAL 0x00000 19 #define IO_APIC_REDIR_SEND_PENDING (1 << 12) 20 #define IO_APIC_REDIR_REMOTE_IRR (1 << 14) 21 #define IO_APIC_REDIR_LEVEL_TRIGGER (1 << 15) 22 #define IO_APIC_REDIR_MASKED (1 << 16) 23 24 struct io_apic_ops { 25 void (*init) (void); 26 unsigned int (*read) (unsigned int apic, unsigned int reg); 27 void (*write) (unsigned int apic, unsigned int reg, unsigned int value); 28 void (*modify)(unsigned int apic, unsigned int reg, unsigned int value); 29 }; 30 31 void __init set_io_apic_ops(const struct io_apic_ops *); 32 33 /* 34 * The structure of the IO-APIC: 35 */ 36 union IO_APIC_reg_00 { 37 u32 raw; 38 struct { 39 u32 __reserved_2 : 14, 40 LTS : 1, 41 delivery_type : 1, 42 __reserved_1 : 8, 43 ID : 8; 44 } __attribute__ ((packed)) bits; 45 }; 46 47 union IO_APIC_reg_01 { 48 u32 raw; 49 struct { 50 u32 version : 8, 51 __reserved_2 : 7, 52 PRQ : 1, 53 entries : 8, 54 __reserved_1 : 8; 55 } __attribute__ ((packed)) bits; 56 }; 57 58 union IO_APIC_reg_02 { 59 u32 raw; 60 struct { 61 u32 __reserved_2 : 24, 62 arbitration : 4, 63 __reserved_1 : 4; 64 } __attribute__ ((packed)) bits; 65 }; 66 67 union IO_APIC_reg_03 { 68 u32 raw; 69 struct { 70 u32 boot_DT : 1, 71 __reserved_1 : 31; 72 } __attribute__ ((packed)) bits; 73 }; 74 75 struct IO_APIC_route_entry { 76 __u32 vector : 8, 77 delivery_mode : 3, /* 000: FIXED 78 * 001: lowest prio 79 * 111: ExtINT 80 */ 81 dest_mode : 1, /* 0: physical, 1: logical */ 82 delivery_status : 1, 83 polarity : 1, 84 irr : 1, 85 trigger : 1, /* 0: edge, 1: level */ 86 mask : 1, /* 0: enabled, 1: disabled */ 87 __reserved_2 : 15; 88 89 __u32 __reserved_3 : 24, 90 dest : 8; 91 } __attribute__ ((packed)); 92 93 struct IR_IO_APIC_route_entry { 94 __u64 vector : 8, 95 zero : 3, 96 index2 : 1, 97 delivery_status : 1, 98 polarity : 1, 99 irr : 1, 100 trigger : 1, 101 mask : 1, 102 reserved : 31, 103 format : 1, 104 index : 15; 105 } __attribute__ ((packed)); 106 107 #define IOAPIC_AUTO -1 108 #define IOAPIC_EDGE 0 109 #define IOAPIC_LEVEL 1 110 111 #ifdef CONFIG_X86_IO_APIC 112 113 /* 114 * # of IO-APICs and # of IRQ routing registers 115 */ 116 extern int nr_ioapics; 117 118 extern int mpc_ioapic_id(int ioapic); 119 extern unsigned int mpc_ioapic_addr(int ioapic); 120 extern struct mp_ioapic_gsi *mp_ioapic_gsi_routing(int ioapic); 121 122 #define MP_MAX_IOAPIC_PIN 127 123 124 /* # of MP IRQ source entries */ 125 extern int mp_irq_entries; 126 127 /* MP IRQ source entries */ 128 extern struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES]; 129 130 /* non-0 if default (table-less) MP configuration */ 131 extern int mpc_default_type; 132 133 /* Older SiS APIC requires we rewrite the index register */ 134 extern int sis_apic_bug; 135 136 /* 1 if "noapic" boot option passed */ 137 extern int skip_ioapic_setup; 138 139 /* 1 if "noapic" boot option passed */ 140 extern int noioapicquirk; 141 142 /* -1 if "noapic" boot option passed */ 143 extern int noioapicreroute; 144 145 /* 1 if the timer IRQ uses the '8259A Virtual Wire' mode */ 146 extern int timer_through_8259; 147 148 /* 149 * If we use the IO-APIC for IRQ routing, disable automatic 150 * assignment of PCI IRQ's. 151 */ 152 #define io_apic_assign_pci_irqs \ 153 (mp_irq_entries && !skip_ioapic_setup && io_apic_irqs) 154 155 struct io_apic_irq_attr; 156 extern int io_apic_set_pci_routing(struct device *dev, int irq, 157 struct io_apic_irq_attr *irq_attr); 158 void setup_IO_APIC_irq_extra(u32 gsi); 159 extern void ioapic_and_gsi_init(void); 160 extern void ioapic_insert_resources(void); 161 162 int io_apic_setup_irq_pin_once(unsigned int irq, int node, struct io_apic_irq_attr *attr); 163 164 extern int save_ioapic_entries(void); 165 extern void mask_ioapic_entries(void); 166 extern int restore_ioapic_entries(void); 167 168 extern int get_nr_irqs_gsi(void); 169 170 extern void setup_ioapic_ids_from_mpc(void); 171 extern void setup_ioapic_ids_from_mpc_nocheck(void); 172 173 struct mp_ioapic_gsi{ 174 u32 gsi_base; 175 u32 gsi_end; 176 }; 177 extern struct mp_ioapic_gsi mp_gsi_routing[]; 178 extern u32 gsi_top; 179 int mp_find_ioapic(u32 gsi); 180 int mp_find_ioapic_pin(int ioapic, u32 gsi); 181 void __init mp_register_ioapic(int id, u32 address, u32 gsi_base); 182 extern void __init pre_init_apic_IRQ0(void); 183 184 extern void mp_save_irq(struct mpc_intsrc *m); 185 186 extern void disable_ioapic_support(void); 187 188 #else /* !CONFIG_X86_IO_APIC */ 189 190 #define io_apic_assign_pci_irqs 0 191 #define setup_ioapic_ids_from_mpc x86_init_noop 192 static const int timer_through_8259 = 0; 193 static inline void ioapic_and_gsi_init(void) { } 194 static inline void ioapic_insert_resources(void) { } 195 #define gsi_top (NR_IRQS_LEGACY) 196 static inline int mp_find_ioapic(u32 gsi) { return 0; } 197 198 struct io_apic_irq_attr; 199 static inline int io_apic_set_pci_routing(struct device *dev, int irq, 200 struct io_apic_irq_attr *irq_attr) { return 0; } 201 202 static inline int save_ioapic_entries(void) 203 { 204 return -ENOMEM; 205 } 206 207 static inline void mask_ioapic_entries(void) { } 208 static inline int restore_ioapic_entries(void) 209 { 210 return -ENOMEM; 211 } 212 213 static inline void mp_save_irq(struct mpc_intsrc *m) { }; 214 static inline void disable_ioapic_support(void) { } 215 #endif 216 217 #endif /* _ASM_X86_IO_APIC_H */ 218