1 #ifndef _ASM_X86_IO_H 2 #define _ASM_X86_IO_H 3 4 /* 5 * This file contains the definitions for the x86 IO instructions 6 * inb/inw/inl/outb/outw/outl and the "string versions" of the same 7 * (insb/insw/insl/outsb/outsw/outsl). You can also use "pausing" 8 * versions of the single-IO instructions (inb_p/inw_p/..). 9 * 10 * This file is not meant to be obfuscating: it's just complicated 11 * to (a) handle it all in a way that makes gcc able to optimize it 12 * as well as possible and (b) trying to avoid writing the same thing 13 * over and over again with slight variations and possibly making a 14 * mistake somewhere. 15 */ 16 17 /* 18 * Thanks to James van Artsdalen for a better timing-fix than 19 * the two short jumps: using outb's to a nonexistent port seems 20 * to guarantee better timings even on fast machines. 21 * 22 * On the other hand, I'd like to be sure of a non-existent port: 23 * I feel a bit unsafe about using 0x80 (should be safe, though) 24 * 25 * Linus 26 */ 27 28 /* 29 * Bit simplified and optimized by Jan Hubicka 30 * Support of BIGMEM added by Gerhard Wichert, Siemens AG, July 1999. 31 * 32 * isa_memset_io, isa_memcpy_fromio, isa_memcpy_toio added, 33 * isa_read[wl] and isa_write[wl] fixed 34 * - Arnaldo Carvalho de Melo <acme@conectiva.com.br> 35 */ 36 37 #define ARCH_HAS_IOREMAP_WC 38 39 #include <linux/string.h> 40 #include <linux/compiler.h> 41 #include <asm-generic/int-ll64.h> 42 #include <asm/page.h> 43 44 #include <xen/xen.h> 45 46 #define build_mmio_read(name, size, type, reg, barrier) \ 47 static inline type name(const volatile void __iomem *addr) \ 48 { type ret; asm volatile("mov" size " %1,%0":reg (ret) \ 49 :"m" (*(volatile type __force *)addr) barrier); return ret; } 50 51 #define build_mmio_write(name, size, type, reg, barrier) \ 52 static inline void name(type val, volatile void __iomem *addr) \ 53 { asm volatile("mov" size " %0,%1": :reg (val), \ 54 "m" (*(volatile type __force *)addr) barrier); } 55 56 build_mmio_read(readb, "b", unsigned char, "=q", :"memory") 57 build_mmio_read(readw, "w", unsigned short, "=r", :"memory") 58 build_mmio_read(readl, "l", unsigned int, "=r", :"memory") 59 60 build_mmio_read(__readb, "b", unsigned char, "=q", ) 61 build_mmio_read(__readw, "w", unsigned short, "=r", ) 62 build_mmio_read(__readl, "l", unsigned int, "=r", ) 63 64 build_mmio_write(writeb, "b", unsigned char, "q", :"memory") 65 build_mmio_write(writew, "w", unsigned short, "r", :"memory") 66 build_mmio_write(writel, "l", unsigned int, "r", :"memory") 67 68 build_mmio_write(__writeb, "b", unsigned char, "q", ) 69 build_mmio_write(__writew, "w", unsigned short, "r", ) 70 build_mmio_write(__writel, "l", unsigned int, "r", ) 71 72 #define readb_relaxed(a) __readb(a) 73 #define readw_relaxed(a) __readw(a) 74 #define readl_relaxed(a) __readl(a) 75 #define __raw_readb __readb 76 #define __raw_readw __readw 77 #define __raw_readl __readl 78 79 #define __raw_writeb __writeb 80 #define __raw_writew __writew 81 #define __raw_writel __writel 82 83 #define mmiowb() barrier() 84 85 #ifdef CONFIG_X86_64 86 87 build_mmio_read(readq, "q", unsigned long, "=r", :"memory") 88 build_mmio_write(writeq, "q", unsigned long, "r", :"memory") 89 90 #else 91 92 static inline __u64 readq(const volatile void __iomem *addr) 93 { 94 const volatile u32 __iomem *p = addr; 95 u32 low, high; 96 97 low = readl(p); 98 high = readl(p + 1); 99 100 return low + ((u64)high << 32); 101 } 102 103 static inline void writeq(__u64 val, volatile void __iomem *addr) 104 { 105 writel(val, addr); 106 writel(val >> 32, addr+4); 107 } 108 109 #endif 110 111 #define readq_relaxed(a) readq(a) 112 113 #define __raw_readq(a) readq(a) 114 #define __raw_writeq(val, addr) writeq(val, addr) 115 116 /* Let people know that we have them */ 117 #define readq readq 118 #define writeq writeq 119 120 /** 121 * virt_to_phys - map virtual addresses to physical 122 * @address: address to remap 123 * 124 * The returned physical address is the physical (CPU) mapping for 125 * the memory address given. It is only valid to use this function on 126 * addresses directly mapped or allocated via kmalloc. 127 * 128 * This function does not give bus mappings for DMA transfers. In 129 * almost all conceivable cases a device driver should not be using 130 * this function 131 */ 132 133 static inline phys_addr_t virt_to_phys(volatile void *address) 134 { 135 return __pa(address); 136 } 137 138 /** 139 * phys_to_virt - map physical address to virtual 140 * @address: address to remap 141 * 142 * The returned virtual address is a current CPU mapping for 143 * the memory address given. It is only valid to use this function on 144 * addresses that have a kernel mapping 145 * 146 * This function does not handle bus mappings for DMA transfers. In 147 * almost all conceivable cases a device driver should not be using 148 * this function 149 */ 150 151 static inline void *phys_to_virt(phys_addr_t address) 152 { 153 return __va(address); 154 } 155 156 /* 157 * Change "struct page" to physical address. 158 */ 159 #define page_to_phys(page) ((dma_addr_t)page_to_pfn(page) << PAGE_SHIFT) 160 161 /* 162 * ISA I/O bus memory addresses are 1:1 with the physical address. 163 * However, we truncate the address to unsigned int to avoid undesirable 164 * promitions in legacy drivers. 165 */ 166 static inline unsigned int isa_virt_to_bus(volatile void *address) 167 { 168 return (unsigned int)virt_to_phys(address); 169 } 170 #define isa_page_to_bus(page) ((unsigned int)page_to_phys(page)) 171 #define isa_bus_to_virt phys_to_virt 172 173 /* 174 * However PCI ones are not necessarily 1:1 and therefore these interfaces 175 * are forbidden in portable PCI drivers. 176 * 177 * Allow them on x86 for legacy drivers, though. 178 */ 179 #define virt_to_bus virt_to_phys 180 #define bus_to_virt phys_to_virt 181 182 /** 183 * ioremap - map bus memory into CPU space 184 * @offset: bus address of the memory 185 * @size: size of the resource to map 186 * 187 * ioremap performs a platform specific sequence of operations to 188 * make bus memory CPU accessible via the readb/readw/readl/writeb/ 189 * writew/writel functions and the other mmio helpers. The returned 190 * address is not guaranteed to be usable directly as a virtual 191 * address. 192 * 193 * If the area you are trying to map is a PCI BAR you should have a 194 * look at pci_iomap(). 195 */ 196 extern void __iomem *ioremap_nocache(resource_size_t offset, unsigned long size); 197 extern void __iomem *ioremap_cache(resource_size_t offset, unsigned long size); 198 extern void __iomem *ioremap_prot(resource_size_t offset, unsigned long size, 199 unsigned long prot_val); 200 201 /* 202 * The default ioremap() behavior is non-cached: 203 */ 204 static inline void __iomem *ioremap(resource_size_t offset, unsigned long size) 205 { 206 return ioremap_nocache(offset, size); 207 } 208 209 extern void iounmap(volatile void __iomem *addr); 210 211 extern void set_iounmap_nonlazy(void); 212 213 #ifdef __KERNEL__ 214 215 #include <asm-generic/iomap.h> 216 217 #include <linux/vmalloc.h> 218 219 /* 220 * Convert a virtual cached pointer to an uncached pointer 221 */ 222 #define xlate_dev_kmem_ptr(p) p 223 224 static inline void 225 memset_io(volatile void __iomem *addr, unsigned char val, size_t count) 226 { 227 memset((void __force *)addr, val, count); 228 } 229 230 static inline void 231 memcpy_fromio(void *dst, const volatile void __iomem *src, size_t count) 232 { 233 memcpy(dst, (const void __force *)src, count); 234 } 235 236 static inline void 237 memcpy_toio(volatile void __iomem *dst, const void *src, size_t count) 238 { 239 memcpy((void __force *)dst, src, count); 240 } 241 242 /* 243 * ISA space is 'always mapped' on a typical x86 system, no need to 244 * explicitly ioremap() it. The fact that the ISA IO space is mapped 245 * to PAGE_OFFSET is pure coincidence - it does not mean ISA values 246 * are physical addresses. The following constant pointer can be 247 * used as the IO-area pointer (it can be iounmapped as well, so the 248 * analogy with PCI is quite large): 249 */ 250 #define __ISA_IO_base ((char __iomem *)(PAGE_OFFSET)) 251 252 /* 253 * Cache management 254 * 255 * This needed for two cases 256 * 1. Out of order aware processors 257 * 2. Accidentally out of order processors (PPro errata #51) 258 */ 259 260 static inline void flush_write_buffers(void) 261 { 262 #if defined(CONFIG_X86_OOSTORE) || defined(CONFIG_X86_PPRO_FENCE) 263 asm volatile("lock; addl $0,0(%%esp)": : :"memory"); 264 #endif 265 } 266 267 #endif /* __KERNEL__ */ 268 269 extern void native_io_delay(void); 270 271 extern int io_delay_type; 272 extern void io_delay_init(void); 273 274 #if defined(CONFIG_PARAVIRT) 275 #include <asm/paravirt.h> 276 #else 277 278 static inline void slow_down_io(void) 279 { 280 native_io_delay(); 281 #ifdef REALLY_SLOW_IO 282 native_io_delay(); 283 native_io_delay(); 284 native_io_delay(); 285 #endif 286 } 287 288 #endif 289 290 #define BUILDIO(bwl, bw, type) \ 291 static inline void out##bwl(unsigned type value, int port) \ 292 { \ 293 asm volatile("out" #bwl " %" #bw "0, %w1" \ 294 : : "a"(value), "Nd"(port)); \ 295 } \ 296 \ 297 static inline unsigned type in##bwl(int port) \ 298 { \ 299 unsigned type value; \ 300 asm volatile("in" #bwl " %w1, %" #bw "0" \ 301 : "=a"(value) : "Nd"(port)); \ 302 return value; \ 303 } \ 304 \ 305 static inline void out##bwl##_p(unsigned type value, int port) \ 306 { \ 307 out##bwl(value, port); \ 308 slow_down_io(); \ 309 } \ 310 \ 311 static inline unsigned type in##bwl##_p(int port) \ 312 { \ 313 unsigned type value = in##bwl(port); \ 314 slow_down_io(); \ 315 return value; \ 316 } \ 317 \ 318 static inline void outs##bwl(int port, const void *addr, unsigned long count) \ 319 { \ 320 asm volatile("rep; outs" #bwl \ 321 : "+S"(addr), "+c"(count) : "d"(port)); \ 322 } \ 323 \ 324 static inline void ins##bwl(int port, void *addr, unsigned long count) \ 325 { \ 326 asm volatile("rep; ins" #bwl \ 327 : "+D"(addr), "+c"(count) : "d"(port)); \ 328 } 329 330 BUILDIO(b, b, char) 331 BUILDIO(w, w, short) 332 BUILDIO(l, , int) 333 334 extern void *xlate_dev_mem_ptr(unsigned long phys); 335 extern void unxlate_dev_mem_ptr(unsigned long phys, void *addr); 336 337 extern int ioremap_change_attr(unsigned long vaddr, unsigned long size, 338 unsigned long prot_val); 339 extern void __iomem *ioremap_wc(resource_size_t offset, unsigned long size); 340 341 /* 342 * early_ioremap() and early_iounmap() are for temporary early boot-time 343 * mappings, before the real ioremap() is functional. 344 * A boot-time mapping is currently limited to at most 16 pages. 345 */ 346 extern void early_ioremap_init(void); 347 extern void early_ioremap_reset(void); 348 extern void __iomem *early_ioremap(resource_size_t phys_addr, 349 unsigned long size); 350 extern void __iomem *early_memremap(resource_size_t phys_addr, 351 unsigned long size); 352 extern void early_iounmap(void __iomem *addr, unsigned long size); 353 extern void fixup_early_ioremap(void); 354 extern bool is_early_ioremap_ptep(pte_t *ptep); 355 356 #ifdef CONFIG_XEN 357 struct bio_vec; 358 359 extern bool xen_biovec_phys_mergeable(const struct bio_vec *vec1, 360 const struct bio_vec *vec2); 361 362 #define BIOVEC_PHYS_MERGEABLE(vec1, vec2) \ 363 (__BIOVEC_PHYS_MERGEABLE(vec1, vec2) && \ 364 (!xen_domain() || xen_biovec_phys_mergeable(vec1, vec2))) 365 #endif /* CONFIG_XEN */ 366 367 #define IO_SPACE_LIMIT 0xffff 368 369 #endif /* _ASM_X86_IO_H */ 370