1 #ifndef _ASM_X86_IO_H 2 #define _ASM_X86_IO_H 3 4 /* 5 * This file contains the definitions for the x86 IO instructions 6 * inb/inw/inl/outb/outw/outl and the "string versions" of the same 7 * (insb/insw/insl/outsb/outsw/outsl). You can also use "pausing" 8 * versions of the single-IO instructions (inb_p/inw_p/..). 9 * 10 * This file is not meant to be obfuscating: it's just complicated 11 * to (a) handle it all in a way that makes gcc able to optimize it 12 * as well as possible and (b) trying to avoid writing the same thing 13 * over and over again with slight variations and possibly making a 14 * mistake somewhere. 15 */ 16 17 /* 18 * Thanks to James van Artsdalen for a better timing-fix than 19 * the two short jumps: using outb's to a nonexistent port seems 20 * to guarantee better timings even on fast machines. 21 * 22 * On the other hand, I'd like to be sure of a non-existent port: 23 * I feel a bit unsafe about using 0x80 (should be safe, though) 24 * 25 * Linus 26 */ 27 28 /* 29 * Bit simplified and optimized by Jan Hubicka 30 * Support of BIGMEM added by Gerhard Wichert, Siemens AG, July 1999. 31 * 32 * isa_memset_io, isa_memcpy_fromio, isa_memcpy_toio added, 33 * isa_read[wl] and isa_write[wl] fixed 34 * - Arnaldo Carvalho de Melo <acme@conectiva.com.br> 35 */ 36 37 #define ARCH_HAS_IOREMAP_WC 38 #define ARCH_HAS_IOREMAP_WT 39 40 #include <linux/string.h> 41 #include <linux/compiler.h> 42 #include <asm/page.h> 43 #include <asm/early_ioremap.h> 44 #include <asm/pgtable_types.h> 45 46 #define build_mmio_read(name, size, type, reg, barrier) \ 47 static inline type name(const volatile void __iomem *addr) \ 48 { type ret; asm volatile("mov" size " %1,%0":reg (ret) \ 49 :"m" (*(volatile type __force *)addr) barrier); return ret; } 50 51 #define build_mmio_write(name, size, type, reg, barrier) \ 52 static inline void name(type val, volatile void __iomem *addr) \ 53 { asm volatile("mov" size " %0,%1": :reg (val), \ 54 "m" (*(volatile type __force *)addr) barrier); } 55 56 build_mmio_read(readb, "b", unsigned char, "=q", :"memory") 57 build_mmio_read(readw, "w", unsigned short, "=r", :"memory") 58 build_mmio_read(readl, "l", unsigned int, "=r", :"memory") 59 60 build_mmio_read(__readb, "b", unsigned char, "=q", ) 61 build_mmio_read(__readw, "w", unsigned short, "=r", ) 62 build_mmio_read(__readl, "l", unsigned int, "=r", ) 63 64 build_mmio_write(writeb, "b", unsigned char, "q", :"memory") 65 build_mmio_write(writew, "w", unsigned short, "r", :"memory") 66 build_mmio_write(writel, "l", unsigned int, "r", :"memory") 67 68 build_mmio_write(__writeb, "b", unsigned char, "q", ) 69 build_mmio_write(__writew, "w", unsigned short, "r", ) 70 build_mmio_write(__writel, "l", unsigned int, "r", ) 71 72 #define readb readb 73 #define readw readw 74 #define readl readl 75 #define readb_relaxed(a) __readb(a) 76 #define readw_relaxed(a) __readw(a) 77 #define readl_relaxed(a) __readl(a) 78 #define __raw_readb __readb 79 #define __raw_readw __readw 80 #define __raw_readl __readl 81 82 #define writeb writeb 83 #define writew writew 84 #define writel writel 85 #define writeb_relaxed(v, a) __writeb(v, a) 86 #define writew_relaxed(v, a) __writew(v, a) 87 #define writel_relaxed(v, a) __writel(v, a) 88 #define __raw_writeb __writeb 89 #define __raw_writew __writew 90 #define __raw_writel __writel 91 92 #define mmiowb() barrier() 93 94 #ifdef CONFIG_X86_64 95 96 build_mmio_read(readq, "q", unsigned long, "=r", :"memory") 97 build_mmio_read(__readq, "q", unsigned long, "=r", ) 98 build_mmio_write(writeq, "q", unsigned long, "r", :"memory") 99 build_mmio_write(__writeq, "q", unsigned long, "r", ) 100 101 #define readq_relaxed(a) __readq(a) 102 #define writeq_relaxed(v, a) __writeq(v, a) 103 104 #define __raw_readq __readq 105 #define __raw_writeq __writeq 106 107 /* Let people know that we have them */ 108 #define readq readq 109 #define writeq writeq 110 111 #endif 112 113 /** 114 * virt_to_phys - map virtual addresses to physical 115 * @address: address to remap 116 * 117 * The returned physical address is the physical (CPU) mapping for 118 * the memory address given. It is only valid to use this function on 119 * addresses directly mapped or allocated via kmalloc. 120 * 121 * This function does not give bus mappings for DMA transfers. In 122 * almost all conceivable cases a device driver should not be using 123 * this function 124 */ 125 126 static inline phys_addr_t virt_to_phys(volatile void *address) 127 { 128 return __pa(address); 129 } 130 #define virt_to_phys virt_to_phys 131 132 /** 133 * phys_to_virt - map physical address to virtual 134 * @address: address to remap 135 * 136 * The returned virtual address is a current CPU mapping for 137 * the memory address given. It is only valid to use this function on 138 * addresses that have a kernel mapping 139 * 140 * This function does not handle bus mappings for DMA transfers. In 141 * almost all conceivable cases a device driver should not be using 142 * this function 143 */ 144 145 static inline void *phys_to_virt(phys_addr_t address) 146 { 147 return __va(address); 148 } 149 #define phys_to_virt phys_to_virt 150 151 /* 152 * Change "struct page" to physical address. 153 */ 154 #define page_to_phys(page) ((dma_addr_t)page_to_pfn(page) << PAGE_SHIFT) 155 156 /* 157 * ISA I/O bus memory addresses are 1:1 with the physical address. 158 * However, we truncate the address to unsigned int to avoid undesirable 159 * promitions in legacy drivers. 160 */ 161 static inline unsigned int isa_virt_to_bus(volatile void *address) 162 { 163 return (unsigned int)virt_to_phys(address); 164 } 165 #define isa_page_to_bus(page) ((unsigned int)page_to_phys(page)) 166 #define isa_bus_to_virt phys_to_virt 167 168 /* 169 * However PCI ones are not necessarily 1:1 and therefore these interfaces 170 * are forbidden in portable PCI drivers. 171 * 172 * Allow them on x86 for legacy drivers, though. 173 */ 174 #define virt_to_bus virt_to_phys 175 #define bus_to_virt phys_to_virt 176 177 /* 178 * The default ioremap() behavior is non-cached; if you need something 179 * else, you probably want one of the following. 180 */ 181 extern void __iomem *ioremap_nocache(resource_size_t offset, unsigned long size); 182 #define ioremap_nocache ioremap_nocache 183 extern void __iomem *ioremap_uc(resource_size_t offset, unsigned long size); 184 #define ioremap_uc ioremap_uc 185 186 extern void __iomem *ioremap_cache(resource_size_t offset, unsigned long size); 187 #define ioremap_cache ioremap_cache 188 extern void __iomem *ioremap_prot(resource_size_t offset, unsigned long size, unsigned long prot_val); 189 #define ioremap_prot ioremap_prot 190 191 /** 192 * ioremap - map bus memory into CPU space 193 * @offset: bus address of the memory 194 * @size: size of the resource to map 195 * 196 * ioremap performs a platform specific sequence of operations to 197 * make bus memory CPU accessible via the readb/readw/readl/writeb/ 198 * writew/writel functions and the other mmio helpers. The returned 199 * address is not guaranteed to be usable directly as a virtual 200 * address. 201 * 202 * If the area you are trying to map is a PCI BAR you should have a 203 * look at pci_iomap(). 204 */ 205 static inline void __iomem *ioremap(resource_size_t offset, unsigned long size) 206 { 207 return ioremap_nocache(offset, size); 208 } 209 #define ioremap ioremap 210 211 extern void iounmap(volatile void __iomem *addr); 212 #define iounmap iounmap 213 214 extern void set_iounmap_nonlazy(void); 215 216 #ifdef __KERNEL__ 217 218 #include <asm-generic/iomap.h> 219 220 /* 221 * ISA space is 'always mapped' on a typical x86 system, no need to 222 * explicitly ioremap() it. The fact that the ISA IO space is mapped 223 * to PAGE_OFFSET is pure coincidence - it does not mean ISA values 224 * are physical addresses. The following constant pointer can be 225 * used as the IO-area pointer (it can be iounmapped as well, so the 226 * analogy with PCI is quite large): 227 */ 228 #define __ISA_IO_base ((char __iomem *)(PAGE_OFFSET)) 229 230 /* 231 * Cache management 232 * 233 * This needed for two cases 234 * 1. Out of order aware processors 235 * 2. Accidentally out of order processors (PPro errata #51) 236 */ 237 238 static inline void flush_write_buffers(void) 239 { 240 #if defined(CONFIG_X86_PPRO_FENCE) 241 asm volatile("lock; addl $0,0(%%esp)": : :"memory"); 242 #endif 243 } 244 245 #endif /* __KERNEL__ */ 246 247 extern void native_io_delay(void); 248 249 extern int io_delay_type; 250 extern void io_delay_init(void); 251 252 #if defined(CONFIG_PARAVIRT) 253 #include <asm/paravirt.h> 254 #else 255 256 static inline void slow_down_io(void) 257 { 258 native_io_delay(); 259 #ifdef REALLY_SLOW_IO 260 native_io_delay(); 261 native_io_delay(); 262 native_io_delay(); 263 #endif 264 } 265 266 #endif 267 268 #define BUILDIO(bwl, bw, type) \ 269 static inline void out##bwl(unsigned type value, int port) \ 270 { \ 271 asm volatile("out" #bwl " %" #bw "0, %w1" \ 272 : : "a"(value), "Nd"(port)); \ 273 } \ 274 \ 275 static inline unsigned type in##bwl(int port) \ 276 { \ 277 unsigned type value; \ 278 asm volatile("in" #bwl " %w1, %" #bw "0" \ 279 : "=a"(value) : "Nd"(port)); \ 280 return value; \ 281 } \ 282 \ 283 static inline void out##bwl##_p(unsigned type value, int port) \ 284 { \ 285 out##bwl(value, port); \ 286 slow_down_io(); \ 287 } \ 288 \ 289 static inline unsigned type in##bwl##_p(int port) \ 290 { \ 291 unsigned type value = in##bwl(port); \ 292 slow_down_io(); \ 293 return value; \ 294 } \ 295 \ 296 static inline void outs##bwl(int port, const void *addr, unsigned long count) \ 297 { \ 298 asm volatile("rep; outs" #bwl \ 299 : "+S"(addr), "+c"(count) : "d"(port) : "memory"); \ 300 } \ 301 \ 302 static inline void ins##bwl(int port, void *addr, unsigned long count) \ 303 { \ 304 asm volatile("rep; ins" #bwl \ 305 : "+D"(addr), "+c"(count) : "d"(port) : "memory"); \ 306 } 307 308 BUILDIO(b, b, char) 309 BUILDIO(w, w, short) 310 BUILDIO(l, , int) 311 312 #define inb inb 313 #define inw inw 314 #define inl inl 315 #define inb_p inb_p 316 #define inw_p inw_p 317 #define inl_p inl_p 318 #define insb insb 319 #define insw insw 320 #define insl insl 321 322 #define outb outb 323 #define outw outw 324 #define outl outl 325 #define outb_p outb_p 326 #define outw_p outw_p 327 #define outl_p outl_p 328 #define outsb outsb 329 #define outsw outsw 330 #define outsl outsl 331 332 extern void *xlate_dev_mem_ptr(phys_addr_t phys); 333 extern void unxlate_dev_mem_ptr(phys_addr_t phys, void *addr); 334 335 #define xlate_dev_mem_ptr xlate_dev_mem_ptr 336 #define unxlate_dev_mem_ptr unxlate_dev_mem_ptr 337 338 extern int ioremap_change_attr(unsigned long vaddr, unsigned long size, 339 enum page_cache_mode pcm); 340 extern void __iomem *ioremap_wc(resource_size_t offset, unsigned long size); 341 #define ioremap_wc ioremap_wc 342 extern void __iomem *ioremap_wt(resource_size_t offset, unsigned long size); 343 #define ioremap_wt ioremap_wt 344 345 extern bool is_early_ioremap_ptep(pte_t *ptep); 346 347 #ifdef CONFIG_XEN 348 #include <xen/xen.h> 349 struct bio_vec; 350 351 extern bool xen_biovec_phys_mergeable(const struct bio_vec *vec1, 352 const struct bio_vec *vec2); 353 354 #define BIOVEC_PHYS_MERGEABLE(vec1, vec2) \ 355 (__BIOVEC_PHYS_MERGEABLE(vec1, vec2) && \ 356 (!xen_domain() || xen_biovec_phys_mergeable(vec1, vec2))) 357 #endif /* CONFIG_XEN */ 358 359 #define IO_SPACE_LIMIT 0xffff 360 361 #include <asm-generic/io.h> 362 #undef PCI_IOBASE 363 364 #ifdef CONFIG_MTRR 365 extern int __must_check arch_phys_wc_index(int handle); 366 #define arch_phys_wc_index arch_phys_wc_index 367 368 extern int __must_check arch_phys_wc_add(unsigned long base, 369 unsigned long size); 370 extern void arch_phys_wc_del(int handle); 371 #define arch_phys_wc_add arch_phys_wc_add 372 #endif 373 374 #ifdef CONFIG_X86_PAT 375 extern int arch_io_reserve_memtype_wc(resource_size_t start, resource_size_t size); 376 extern void arch_io_free_memtype_wc(resource_size_t start, resource_size_t size); 377 #define arch_io_reserve_memtype_wc arch_io_reserve_memtype_wc 378 #endif 379 380 extern bool arch_memremap_can_ram_remap(resource_size_t offset, 381 unsigned long size, 382 unsigned long flags); 383 #define arch_memremap_can_ram_remap arch_memremap_can_ram_remap 384 385 extern bool phys_mem_access_encrypted(unsigned long phys_addr, 386 unsigned long size); 387 388 #endif /* _ASM_X86_IO_H */ 389