1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _ASM_X86_IO_H 3 #define _ASM_X86_IO_H 4 5 /* 6 * This file contains the definitions for the x86 IO instructions 7 * inb/inw/inl/outb/outw/outl and the "string versions" of the same 8 * (insb/insw/insl/outsb/outsw/outsl). You can also use "pausing" 9 * versions of the single-IO instructions (inb_p/inw_p/..). 10 * 11 * This file is not meant to be obfuscating: it's just complicated 12 * to (a) handle it all in a way that makes gcc able to optimize it 13 * as well as possible and (b) trying to avoid writing the same thing 14 * over and over again with slight variations and possibly making a 15 * mistake somewhere. 16 */ 17 18 /* 19 * Thanks to James van Artsdalen for a better timing-fix than 20 * the two short jumps: using outb's to a nonexistent port seems 21 * to guarantee better timings even on fast machines. 22 * 23 * On the other hand, I'd like to be sure of a non-existent port: 24 * I feel a bit unsafe about using 0x80 (should be safe, though) 25 * 26 * Linus 27 */ 28 29 /* 30 * Bit simplified and optimized by Jan Hubicka 31 * Support of BIGMEM added by Gerhard Wichert, Siemens AG, July 1999. 32 * 33 * isa_memset_io, isa_memcpy_fromio, isa_memcpy_toio added, 34 * isa_read[wl] and isa_write[wl] fixed 35 * - Arnaldo Carvalho de Melo <acme@conectiva.com.br> 36 */ 37 38 #define ARCH_HAS_IOREMAP_WC 39 #define ARCH_HAS_IOREMAP_WT 40 41 #include <linux/string.h> 42 #include <linux/compiler.h> 43 #include <linux/cc_platform.h> 44 #include <asm/page.h> 45 #include <asm/early_ioremap.h> 46 #include <asm/pgtable_types.h> 47 48 #define build_mmio_read(name, size, type, reg, barrier) \ 49 static inline type name(const volatile void __iomem *addr) \ 50 { type ret; asm volatile("mov" size " %1,%0":reg (ret) \ 51 :"m" (*(volatile type __force *)addr) barrier); return ret; } 52 53 #define build_mmio_write(name, size, type, reg, barrier) \ 54 static inline void name(type val, volatile void __iomem *addr) \ 55 { asm volatile("mov" size " %0,%1": :reg (val), \ 56 "m" (*(volatile type __force *)addr) barrier); } 57 58 build_mmio_read(readb, "b", unsigned char, "=q", :"memory") 59 build_mmio_read(readw, "w", unsigned short, "=r", :"memory") 60 build_mmio_read(readl, "l", unsigned int, "=r", :"memory") 61 62 build_mmio_read(__readb, "b", unsigned char, "=q", ) 63 build_mmio_read(__readw, "w", unsigned short, "=r", ) 64 build_mmio_read(__readl, "l", unsigned int, "=r", ) 65 66 build_mmio_write(writeb, "b", unsigned char, "q", :"memory") 67 build_mmio_write(writew, "w", unsigned short, "r", :"memory") 68 build_mmio_write(writel, "l", unsigned int, "r", :"memory") 69 70 build_mmio_write(__writeb, "b", unsigned char, "q", ) 71 build_mmio_write(__writew, "w", unsigned short, "r", ) 72 build_mmio_write(__writel, "l", unsigned int, "r", ) 73 74 #define readb readb 75 #define readw readw 76 #define readl readl 77 #define readb_relaxed(a) __readb(a) 78 #define readw_relaxed(a) __readw(a) 79 #define readl_relaxed(a) __readl(a) 80 #define __raw_readb __readb 81 #define __raw_readw __readw 82 #define __raw_readl __readl 83 84 #define writeb writeb 85 #define writew writew 86 #define writel writel 87 #define writeb_relaxed(v, a) __writeb(v, a) 88 #define writew_relaxed(v, a) __writew(v, a) 89 #define writel_relaxed(v, a) __writel(v, a) 90 #define __raw_writeb __writeb 91 #define __raw_writew __writew 92 #define __raw_writel __writel 93 94 #ifdef CONFIG_X86_64 95 96 build_mmio_read(readq, "q", u64, "=r", :"memory") 97 build_mmio_read(__readq, "q", u64, "=r", ) 98 build_mmio_write(writeq, "q", u64, "r", :"memory") 99 build_mmio_write(__writeq, "q", u64, "r", ) 100 101 #define readq_relaxed(a) __readq(a) 102 #define writeq_relaxed(v, a) __writeq(v, a) 103 104 #define __raw_readq __readq 105 #define __raw_writeq __writeq 106 107 /* Let people know that we have them */ 108 #define readq readq 109 #define writeq writeq 110 111 #endif 112 113 #define ARCH_HAS_VALID_PHYS_ADDR_RANGE 114 extern int valid_phys_addr_range(phys_addr_t addr, size_t size); 115 extern int valid_mmap_phys_addr_range(unsigned long pfn, size_t size); 116 117 /** 118 * virt_to_phys - map virtual addresses to physical 119 * @address: address to remap 120 * 121 * The returned physical address is the physical (CPU) mapping for 122 * the memory address given. It is only valid to use this function on 123 * addresses directly mapped or allocated via kmalloc. 124 * 125 * This function does not give bus mappings for DMA transfers. In 126 * almost all conceivable cases a device driver should not be using 127 * this function 128 */ 129 130 static inline phys_addr_t virt_to_phys(volatile void *address) 131 { 132 return __pa(address); 133 } 134 #define virt_to_phys virt_to_phys 135 136 /** 137 * phys_to_virt - map physical address to virtual 138 * @address: address to remap 139 * 140 * The returned virtual address is a current CPU mapping for 141 * the memory address given. It is only valid to use this function on 142 * addresses that have a kernel mapping 143 * 144 * This function does not handle bus mappings for DMA transfers. In 145 * almost all conceivable cases a device driver should not be using 146 * this function 147 */ 148 149 static inline void *phys_to_virt(phys_addr_t address) 150 { 151 return __va(address); 152 } 153 #define phys_to_virt phys_to_virt 154 155 /* 156 * Change "struct page" to physical address. 157 */ 158 #define page_to_phys(page) ((dma_addr_t)page_to_pfn(page) << PAGE_SHIFT) 159 160 /* 161 * ISA I/O bus memory addresses are 1:1 with the physical address. 162 * However, we truncate the address to unsigned int to avoid undesirable 163 * promotions in legacy drivers. 164 */ 165 static inline unsigned int isa_virt_to_bus(volatile void *address) 166 { 167 return (unsigned int)virt_to_phys(address); 168 } 169 #define isa_bus_to_virt phys_to_virt 170 171 /* 172 * However PCI ones are not necessarily 1:1 and therefore these interfaces 173 * are forbidden in portable PCI drivers. 174 * 175 * Allow them on x86 for legacy drivers, though. 176 */ 177 #define virt_to_bus virt_to_phys 178 #define bus_to_virt phys_to_virt 179 180 /* 181 * The default ioremap() behavior is non-cached; if you need something 182 * else, you probably want one of the following. 183 */ 184 extern void __iomem *ioremap_uc(resource_size_t offset, unsigned long size); 185 #define ioremap_uc ioremap_uc 186 extern void __iomem *ioremap_cache(resource_size_t offset, unsigned long size); 187 #define ioremap_cache ioremap_cache 188 extern void __iomem *ioremap_prot(resource_size_t offset, unsigned long size, unsigned long prot_val); 189 #define ioremap_prot ioremap_prot 190 extern void __iomem *ioremap_encrypted(resource_size_t phys_addr, unsigned long size); 191 #define ioremap_encrypted ioremap_encrypted 192 193 /** 194 * ioremap - map bus memory into CPU space 195 * @offset: bus address of the memory 196 * @size: size of the resource to map 197 * 198 * ioremap performs a platform specific sequence of operations to 199 * make bus memory CPU accessible via the readb/readw/readl/writeb/ 200 * writew/writel functions and the other mmio helpers. The returned 201 * address is not guaranteed to be usable directly as a virtual 202 * address. 203 * 204 * If the area you are trying to map is a PCI BAR you should have a 205 * look at pci_iomap(). 206 */ 207 void __iomem *ioremap(resource_size_t offset, unsigned long size); 208 #define ioremap ioremap 209 210 extern void iounmap(volatile void __iomem *addr); 211 #define iounmap iounmap 212 213 #ifdef __KERNEL__ 214 215 void memcpy_fromio(void *, const volatile void __iomem *, size_t); 216 void memcpy_toio(volatile void __iomem *, const void *, size_t); 217 void memset_io(volatile void __iomem *, int, size_t); 218 219 #define memcpy_fromio memcpy_fromio 220 #define memcpy_toio memcpy_toio 221 #define memset_io memset_io 222 223 #include <asm-generic/iomap.h> 224 225 /* 226 * ISA space is 'always mapped' on a typical x86 system, no need to 227 * explicitly ioremap() it. The fact that the ISA IO space is mapped 228 * to PAGE_OFFSET is pure coincidence - it does not mean ISA values 229 * are physical addresses. The following constant pointer can be 230 * used as the IO-area pointer (it can be iounmapped as well, so the 231 * analogy with PCI is quite large): 232 */ 233 #define __ISA_IO_base ((char __iomem *)(PAGE_OFFSET)) 234 235 #endif /* __KERNEL__ */ 236 237 extern void native_io_delay(void); 238 239 extern int io_delay_type; 240 extern void io_delay_init(void); 241 242 #if defined(CONFIG_PARAVIRT) 243 #include <asm/paravirt.h> 244 #else 245 246 static inline void slow_down_io(void) 247 { 248 native_io_delay(); 249 #ifdef REALLY_SLOW_IO 250 native_io_delay(); 251 native_io_delay(); 252 native_io_delay(); 253 #endif 254 } 255 256 #endif 257 258 #define BUILDIO(bwl, bw, type) \ 259 static inline void out##bwl(unsigned type value, int port) \ 260 { \ 261 asm volatile("out" #bwl " %" #bw "0, %w1" \ 262 : : "a"(value), "Nd"(port)); \ 263 } \ 264 \ 265 static inline unsigned type in##bwl(int port) \ 266 { \ 267 unsigned type value; \ 268 asm volatile("in" #bwl " %w1, %" #bw "0" \ 269 : "=a"(value) : "Nd"(port)); \ 270 return value; \ 271 } \ 272 \ 273 static inline void out##bwl##_p(unsigned type value, int port) \ 274 { \ 275 out##bwl(value, port); \ 276 slow_down_io(); \ 277 } \ 278 \ 279 static inline unsigned type in##bwl##_p(int port) \ 280 { \ 281 unsigned type value = in##bwl(port); \ 282 slow_down_io(); \ 283 return value; \ 284 } \ 285 \ 286 static inline void outs##bwl(int port, const void *addr, unsigned long count) \ 287 { \ 288 if (cc_platform_has(CC_ATTR_GUEST_UNROLL_STRING_IO)) { \ 289 unsigned type *value = (unsigned type *)addr; \ 290 while (count) { \ 291 out##bwl(*value, port); \ 292 value++; \ 293 count--; \ 294 } \ 295 } else { \ 296 asm volatile("rep; outs" #bwl \ 297 : "+S"(addr), "+c"(count) \ 298 : "d"(port) : "memory"); \ 299 } \ 300 } \ 301 \ 302 static inline void ins##bwl(int port, void *addr, unsigned long count) \ 303 { \ 304 if (cc_platform_has(CC_ATTR_GUEST_UNROLL_STRING_IO)) { \ 305 unsigned type *value = (unsigned type *)addr; \ 306 while (count) { \ 307 *value = in##bwl(port); \ 308 value++; \ 309 count--; \ 310 } \ 311 } else { \ 312 asm volatile("rep; ins" #bwl \ 313 : "+D"(addr), "+c"(count) \ 314 : "d"(port) : "memory"); \ 315 } \ 316 } 317 318 BUILDIO(b, b, char) 319 BUILDIO(w, w, short) 320 BUILDIO(l, , int) 321 322 #define inb inb 323 #define inw inw 324 #define inl inl 325 #define inb_p inb_p 326 #define inw_p inw_p 327 #define inl_p inl_p 328 #define insb insb 329 #define insw insw 330 #define insl insl 331 332 #define outb outb 333 #define outw outw 334 #define outl outl 335 #define outb_p outb_p 336 #define outw_p outw_p 337 #define outl_p outl_p 338 #define outsb outsb 339 #define outsw outsw 340 #define outsl outsl 341 342 extern void *xlate_dev_mem_ptr(phys_addr_t phys); 343 extern void unxlate_dev_mem_ptr(phys_addr_t phys, void *addr); 344 345 #define xlate_dev_mem_ptr xlate_dev_mem_ptr 346 #define unxlate_dev_mem_ptr unxlate_dev_mem_ptr 347 348 extern int ioremap_change_attr(unsigned long vaddr, unsigned long size, 349 enum page_cache_mode pcm); 350 extern void __iomem *ioremap_wc(resource_size_t offset, unsigned long size); 351 #define ioremap_wc ioremap_wc 352 extern void __iomem *ioremap_wt(resource_size_t offset, unsigned long size); 353 #define ioremap_wt ioremap_wt 354 355 extern bool is_early_ioremap_ptep(pte_t *ptep); 356 357 #define IO_SPACE_LIMIT 0xffff 358 359 #include <asm-generic/io.h> 360 #undef PCI_IOBASE 361 362 #ifdef CONFIG_MTRR 363 extern int __must_check arch_phys_wc_index(int handle); 364 #define arch_phys_wc_index arch_phys_wc_index 365 366 extern int __must_check arch_phys_wc_add(unsigned long base, 367 unsigned long size); 368 extern void arch_phys_wc_del(int handle); 369 #define arch_phys_wc_add arch_phys_wc_add 370 #endif 371 372 #ifdef CONFIG_X86_PAT 373 extern int arch_io_reserve_memtype_wc(resource_size_t start, resource_size_t size); 374 extern void arch_io_free_memtype_wc(resource_size_t start, resource_size_t size); 375 #define arch_io_reserve_memtype_wc arch_io_reserve_memtype_wc 376 #endif 377 378 #ifdef CONFIG_AMD_MEM_ENCRYPT 379 extern bool arch_memremap_can_ram_remap(resource_size_t offset, 380 unsigned long size, 381 unsigned long flags); 382 #define arch_memremap_can_ram_remap arch_memremap_can_ram_remap 383 384 extern bool phys_mem_access_encrypted(unsigned long phys_addr, 385 unsigned long size); 386 #else 387 static inline bool phys_mem_access_encrypted(unsigned long phys_addr, 388 unsigned long size) 389 { 390 return true; 391 } 392 #endif 393 394 /** 395 * iosubmit_cmds512 - copy data to single MMIO location, in 512-bit units 396 * @dst: destination, in MMIO space (must be 512-bit aligned) 397 * @src: source 398 * @count: number of 512 bits quantities to submit 399 * 400 * Submit data from kernel space to MMIO space, in units of 512 bits at a 401 * time. Order of access is not guaranteed, nor is a memory barrier 402 * performed afterwards. 403 * 404 * Warning: Do not use this helper unless your driver has checked that the CPU 405 * instruction is supported on the platform. 406 */ 407 static inline void iosubmit_cmds512(void __iomem *dst, const void *src, 408 size_t count) 409 { 410 const u8 *from = src; 411 const u8 *end = from + count * 64; 412 413 while (from < end) { 414 movdir64b(dst, from); 415 from += 64; 416 } 417 } 418 419 #endif /* _ASM_X86_IO_H */ 420