1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _ASM_X86_IO_H 3 #define _ASM_X86_IO_H 4 5 /* 6 * This file contains the definitions for the x86 IO instructions 7 * inb/inw/inl/outb/outw/outl and the "string versions" of the same 8 * (insb/insw/insl/outsb/outsw/outsl). You can also use "pausing" 9 * versions of the single-IO instructions (inb_p/inw_p/..). 10 * 11 * This file is not meant to be obfuscating: it's just complicated 12 * to (a) handle it all in a way that makes gcc able to optimize it 13 * as well as possible and (b) trying to avoid writing the same thing 14 * over and over again with slight variations and possibly making a 15 * mistake somewhere. 16 */ 17 18 /* 19 * Thanks to James van Artsdalen for a better timing-fix than 20 * the two short jumps: using outb's to a nonexistent port seems 21 * to guarantee better timings even on fast machines. 22 * 23 * On the other hand, I'd like to be sure of a non-existent port: 24 * I feel a bit unsafe about using 0x80 (should be safe, though) 25 * 26 * Linus 27 */ 28 29 /* 30 * Bit simplified and optimized by Jan Hubicka 31 * Support of BIGMEM added by Gerhard Wichert, Siemens AG, July 1999. 32 * 33 * isa_memset_io, isa_memcpy_fromio, isa_memcpy_toio added, 34 * isa_read[wl] and isa_write[wl] fixed 35 * - Arnaldo Carvalho de Melo <acme@conectiva.com.br> 36 */ 37 38 #define ARCH_HAS_IOREMAP_WC 39 #define ARCH_HAS_IOREMAP_WT 40 41 #include <linux/string.h> 42 #include <linux/compiler.h> 43 #include <asm/page.h> 44 #include <asm/early_ioremap.h> 45 #include <asm/pgtable_types.h> 46 47 #define build_mmio_read(name, size, type, reg, barrier) \ 48 static inline type name(const volatile void __iomem *addr) \ 49 { type ret; asm volatile("mov" size " %1,%0":reg (ret) \ 50 :"m" (*(volatile type __force *)addr) barrier); return ret; } 51 52 #define build_mmio_write(name, size, type, reg, barrier) \ 53 static inline void name(type val, volatile void __iomem *addr) \ 54 { asm volatile("mov" size " %0,%1": :reg (val), \ 55 "m" (*(volatile type __force *)addr) barrier); } 56 57 build_mmio_read(readb, "b", unsigned char, "=q", :"memory") 58 build_mmio_read(readw, "w", unsigned short, "=r", :"memory") 59 build_mmio_read(readl, "l", unsigned int, "=r", :"memory") 60 61 build_mmio_read(__readb, "b", unsigned char, "=q", ) 62 build_mmio_read(__readw, "w", unsigned short, "=r", ) 63 build_mmio_read(__readl, "l", unsigned int, "=r", ) 64 65 build_mmio_write(writeb, "b", unsigned char, "q", :"memory") 66 build_mmio_write(writew, "w", unsigned short, "r", :"memory") 67 build_mmio_write(writel, "l", unsigned int, "r", :"memory") 68 69 build_mmio_write(__writeb, "b", unsigned char, "q", ) 70 build_mmio_write(__writew, "w", unsigned short, "r", ) 71 build_mmio_write(__writel, "l", unsigned int, "r", ) 72 73 #define readb readb 74 #define readw readw 75 #define readl readl 76 #define readb_relaxed(a) __readb(a) 77 #define readw_relaxed(a) __readw(a) 78 #define readl_relaxed(a) __readl(a) 79 #define __raw_readb __readb 80 #define __raw_readw __readw 81 #define __raw_readl __readl 82 83 #define writeb writeb 84 #define writew writew 85 #define writel writel 86 #define writeb_relaxed(v, a) __writeb(v, a) 87 #define writew_relaxed(v, a) __writew(v, a) 88 #define writel_relaxed(v, a) __writel(v, a) 89 #define __raw_writeb __writeb 90 #define __raw_writew __writew 91 #define __raw_writel __writel 92 93 #define mmiowb() barrier() 94 95 #ifdef CONFIG_X86_64 96 97 build_mmio_read(readq, "q", unsigned long, "=r", :"memory") 98 build_mmio_read(__readq, "q", unsigned long, "=r", ) 99 build_mmio_write(writeq, "q", unsigned long, "r", :"memory") 100 build_mmio_write(__writeq, "q", unsigned long, "r", ) 101 102 #define readq_relaxed(a) __readq(a) 103 #define writeq_relaxed(v, a) __writeq(v, a) 104 105 #define __raw_readq __readq 106 #define __raw_writeq __writeq 107 108 /* Let people know that we have them */ 109 #define readq readq 110 #define writeq writeq 111 112 #endif 113 114 /** 115 * virt_to_phys - map virtual addresses to physical 116 * @address: address to remap 117 * 118 * The returned physical address is the physical (CPU) mapping for 119 * the memory address given. It is only valid to use this function on 120 * addresses directly mapped or allocated via kmalloc. 121 * 122 * This function does not give bus mappings for DMA transfers. In 123 * almost all conceivable cases a device driver should not be using 124 * this function 125 */ 126 127 static inline phys_addr_t virt_to_phys(volatile void *address) 128 { 129 return __pa(address); 130 } 131 #define virt_to_phys virt_to_phys 132 133 /** 134 * phys_to_virt - map physical address to virtual 135 * @address: address to remap 136 * 137 * The returned virtual address is a current CPU mapping for 138 * the memory address given. It is only valid to use this function on 139 * addresses that have a kernel mapping 140 * 141 * This function does not handle bus mappings for DMA transfers. In 142 * almost all conceivable cases a device driver should not be using 143 * this function 144 */ 145 146 static inline void *phys_to_virt(phys_addr_t address) 147 { 148 return __va(address); 149 } 150 #define phys_to_virt phys_to_virt 151 152 /* 153 * Change "struct page" to physical address. 154 */ 155 #define page_to_phys(page) ((dma_addr_t)page_to_pfn(page) << PAGE_SHIFT) 156 157 /* 158 * ISA I/O bus memory addresses are 1:1 with the physical address. 159 * However, we truncate the address to unsigned int to avoid undesirable 160 * promitions in legacy drivers. 161 */ 162 static inline unsigned int isa_virt_to_bus(volatile void *address) 163 { 164 return (unsigned int)virt_to_phys(address); 165 } 166 #define isa_page_to_bus(page) ((unsigned int)page_to_phys(page)) 167 #define isa_bus_to_virt phys_to_virt 168 169 /* 170 * However PCI ones are not necessarily 1:1 and therefore these interfaces 171 * are forbidden in portable PCI drivers. 172 * 173 * Allow them on x86 for legacy drivers, though. 174 */ 175 #define virt_to_bus virt_to_phys 176 #define bus_to_virt phys_to_virt 177 178 /* 179 * The default ioremap() behavior is non-cached; if you need something 180 * else, you probably want one of the following. 181 */ 182 extern void __iomem *ioremap_nocache(resource_size_t offset, unsigned long size); 183 #define ioremap_nocache ioremap_nocache 184 extern void __iomem *ioremap_uc(resource_size_t offset, unsigned long size); 185 #define ioremap_uc ioremap_uc 186 187 extern void __iomem *ioremap_cache(resource_size_t offset, unsigned long size); 188 #define ioremap_cache ioremap_cache 189 extern void __iomem *ioremap_prot(resource_size_t offset, unsigned long size, unsigned long prot_val); 190 #define ioremap_prot ioremap_prot 191 192 /** 193 * ioremap - map bus memory into CPU space 194 * @offset: bus address of the memory 195 * @size: size of the resource to map 196 * 197 * ioremap performs a platform specific sequence of operations to 198 * make bus memory CPU accessible via the readb/readw/readl/writeb/ 199 * writew/writel functions and the other mmio helpers. The returned 200 * address is not guaranteed to be usable directly as a virtual 201 * address. 202 * 203 * If the area you are trying to map is a PCI BAR you should have a 204 * look at pci_iomap(). 205 */ 206 static inline void __iomem *ioremap(resource_size_t offset, unsigned long size) 207 { 208 return ioremap_nocache(offset, size); 209 } 210 #define ioremap ioremap 211 212 extern void iounmap(volatile void __iomem *addr); 213 #define iounmap iounmap 214 215 extern void set_iounmap_nonlazy(void); 216 217 #ifdef __KERNEL__ 218 219 #include <asm-generic/iomap.h> 220 221 /* 222 * ISA space is 'always mapped' on a typical x86 system, no need to 223 * explicitly ioremap() it. The fact that the ISA IO space is mapped 224 * to PAGE_OFFSET is pure coincidence - it does not mean ISA values 225 * are physical addresses. The following constant pointer can be 226 * used as the IO-area pointer (it can be iounmapped as well, so the 227 * analogy with PCI is quite large): 228 */ 229 #define __ISA_IO_base ((char __iomem *)(PAGE_OFFSET)) 230 231 /* 232 * Cache management 233 * 234 * This needed for two cases 235 * 1. Out of order aware processors 236 * 2. Accidentally out of order processors (PPro errata #51) 237 */ 238 239 static inline void flush_write_buffers(void) 240 { 241 #if defined(CONFIG_X86_PPRO_FENCE) 242 asm volatile("lock; addl $0,0(%%esp)": : :"memory"); 243 #endif 244 } 245 246 #endif /* __KERNEL__ */ 247 248 extern void native_io_delay(void); 249 250 extern int io_delay_type; 251 extern void io_delay_init(void); 252 253 #if defined(CONFIG_PARAVIRT) 254 #include <asm/paravirt.h> 255 #else 256 257 static inline void slow_down_io(void) 258 { 259 native_io_delay(); 260 #ifdef REALLY_SLOW_IO 261 native_io_delay(); 262 native_io_delay(); 263 native_io_delay(); 264 #endif 265 } 266 267 #endif 268 269 #define BUILDIO(bwl, bw, type) \ 270 static inline void out##bwl(unsigned type value, int port) \ 271 { \ 272 asm volatile("out" #bwl " %" #bw "0, %w1" \ 273 : : "a"(value), "Nd"(port)); \ 274 } \ 275 \ 276 static inline unsigned type in##bwl(int port) \ 277 { \ 278 unsigned type value; \ 279 asm volatile("in" #bwl " %w1, %" #bw "0" \ 280 : "=a"(value) : "Nd"(port)); \ 281 return value; \ 282 } \ 283 \ 284 static inline void out##bwl##_p(unsigned type value, int port) \ 285 { \ 286 out##bwl(value, port); \ 287 slow_down_io(); \ 288 } \ 289 \ 290 static inline unsigned type in##bwl##_p(int port) \ 291 { \ 292 unsigned type value = in##bwl(port); \ 293 slow_down_io(); \ 294 return value; \ 295 } \ 296 \ 297 static inline void outs##bwl(int port, const void *addr, unsigned long count) \ 298 { \ 299 asm volatile("rep; outs" #bwl \ 300 : "+S"(addr), "+c"(count) : "d"(port) : "memory"); \ 301 } \ 302 \ 303 static inline void ins##bwl(int port, void *addr, unsigned long count) \ 304 { \ 305 asm volatile("rep; ins" #bwl \ 306 : "+D"(addr), "+c"(count) : "d"(port) : "memory"); \ 307 } 308 309 BUILDIO(b, b, char) 310 BUILDIO(w, w, short) 311 BUILDIO(l, , int) 312 313 #define inb inb 314 #define inw inw 315 #define inl inl 316 #define inb_p inb_p 317 #define inw_p inw_p 318 #define inl_p inl_p 319 #define insb insb 320 #define insw insw 321 #define insl insl 322 323 #define outb outb 324 #define outw outw 325 #define outl outl 326 #define outb_p outb_p 327 #define outw_p outw_p 328 #define outl_p outl_p 329 #define outsb outsb 330 #define outsw outsw 331 #define outsl outsl 332 333 extern void *xlate_dev_mem_ptr(phys_addr_t phys); 334 extern void unxlate_dev_mem_ptr(phys_addr_t phys, void *addr); 335 336 #define xlate_dev_mem_ptr xlate_dev_mem_ptr 337 #define unxlate_dev_mem_ptr unxlate_dev_mem_ptr 338 339 extern int ioremap_change_attr(unsigned long vaddr, unsigned long size, 340 enum page_cache_mode pcm); 341 extern void __iomem *ioremap_wc(resource_size_t offset, unsigned long size); 342 #define ioremap_wc ioremap_wc 343 extern void __iomem *ioremap_wt(resource_size_t offset, unsigned long size); 344 #define ioremap_wt ioremap_wt 345 346 extern bool is_early_ioremap_ptep(pte_t *ptep); 347 348 #ifdef CONFIG_XEN 349 #include <xen/xen.h> 350 struct bio_vec; 351 352 extern bool xen_biovec_phys_mergeable(const struct bio_vec *vec1, 353 const struct bio_vec *vec2); 354 355 #define BIOVEC_PHYS_MERGEABLE(vec1, vec2) \ 356 (__BIOVEC_PHYS_MERGEABLE(vec1, vec2) && \ 357 (!xen_domain() || xen_biovec_phys_mergeable(vec1, vec2))) 358 #endif /* CONFIG_XEN */ 359 360 #define IO_SPACE_LIMIT 0xffff 361 362 #include <asm-generic/io.h> 363 #undef PCI_IOBASE 364 365 #ifdef CONFIG_MTRR 366 extern int __must_check arch_phys_wc_index(int handle); 367 #define arch_phys_wc_index arch_phys_wc_index 368 369 extern int __must_check arch_phys_wc_add(unsigned long base, 370 unsigned long size); 371 extern void arch_phys_wc_del(int handle); 372 #define arch_phys_wc_add arch_phys_wc_add 373 #endif 374 375 #ifdef CONFIG_X86_PAT 376 extern int arch_io_reserve_memtype_wc(resource_size_t start, resource_size_t size); 377 extern void arch_io_free_memtype_wc(resource_size_t start, resource_size_t size); 378 #define arch_io_reserve_memtype_wc arch_io_reserve_memtype_wc 379 #endif 380 381 extern bool arch_memremap_can_ram_remap(resource_size_t offset, 382 unsigned long size, 383 unsigned long flags); 384 #define arch_memremap_can_ram_remap arch_memremap_can_ram_remap 385 386 extern bool phys_mem_access_encrypted(unsigned long phys_addr, 387 unsigned long size); 388 389 #endif /* _ASM_X86_IO_H */ 390