19a58a333SSreedhara DS #ifndef _ASM_X86_INTEL_SCU_IPC_H_ 29a58a333SSreedhara DS #define _ASM_X86_INTEL_SCU_IPC_H_ 39a58a333SSreedhara DS 435f2915cSFeng Tang #define IPCMSG_VRTC 0xFA /* Set vRTC device */ 535f2915cSFeng Tang 635f2915cSFeng Tang /* Command id associated with message IPCMSG_VRTC */ 735f2915cSFeng Tang #define IPC_CMD_VRTC_SETTIME 1 /* Set time */ 835f2915cSFeng Tang #define IPC_CMD_VRTC_SETALARM 2 /* Set alarm */ 935f2915cSFeng Tang 109a58a333SSreedhara DS /* Read single register */ 119a58a333SSreedhara DS int intel_scu_ipc_ioread8(u16 addr, u8 *data); 129a58a333SSreedhara DS 139a58a333SSreedhara DS /* Read two sequential registers */ 149a58a333SSreedhara DS int intel_scu_ipc_ioread16(u16 addr, u16 *data); 159a58a333SSreedhara DS 169a58a333SSreedhara DS /* Read four sequential registers */ 179a58a333SSreedhara DS int intel_scu_ipc_ioread32(u16 addr, u32 *data); 189a58a333SSreedhara DS 199a58a333SSreedhara DS /* Read a vector */ 209a58a333SSreedhara DS int intel_scu_ipc_readv(u16 *addr, u8 *data, int len); 219a58a333SSreedhara DS 229a58a333SSreedhara DS /* Write single register */ 239a58a333SSreedhara DS int intel_scu_ipc_iowrite8(u16 addr, u8 data); 249a58a333SSreedhara DS 259a58a333SSreedhara DS /* Write two sequential registers */ 269a58a333SSreedhara DS int intel_scu_ipc_iowrite16(u16 addr, u16 data); 279a58a333SSreedhara DS 289a58a333SSreedhara DS /* Write four sequential registers */ 299a58a333SSreedhara DS int intel_scu_ipc_iowrite32(u16 addr, u32 data); 309a58a333SSreedhara DS 319a58a333SSreedhara DS /* Write a vector */ 329a58a333SSreedhara DS int intel_scu_ipc_writev(u16 *addr, u8 *data, int len); 339a58a333SSreedhara DS 349a58a333SSreedhara DS /* Update single register based on the mask */ 359a58a333SSreedhara DS int intel_scu_ipc_update_register(u16 addr, u8 data, u8 mask); 369a58a333SSreedhara DS 379a58a333SSreedhara DS /* 389a58a333SSreedhara DS * Indirect register read 399a58a333SSreedhara DS * Can be used when SCCB(System Controller Configuration Block) register 409a58a333SSreedhara DS * HRIM(Honor Restricted IPC Messages) is set (bit 23) 419a58a333SSreedhara DS */ 429a58a333SSreedhara DS int intel_scu_ipc_register_read(u32 addr, u32 *data); 439a58a333SSreedhara DS 449a58a333SSreedhara DS /* 459a58a333SSreedhara DS * Indirect register write 469a58a333SSreedhara DS * Can be used when SCCB(System Controller Configuration Block) register 479a58a333SSreedhara DS * HRIM(Honor Restricted IPC Messages) is set (bit 23) 489a58a333SSreedhara DS */ 499a58a333SSreedhara DS int intel_scu_ipc_register_write(u32 addr, u32 data); 509a58a333SSreedhara DS 519a58a333SSreedhara DS /* Issue commands to the SCU with or without data */ 529a58a333SSreedhara DS int intel_scu_ipc_simple_command(int cmd, int sub); 539a58a333SSreedhara DS int intel_scu_ipc_command(int cmd, int sub, u32 *in, int inlen, 549a58a333SSreedhara DS u32 *out, int outlen); 559a58a333SSreedhara DS /* I2C control api */ 569a58a333SSreedhara DS int intel_scu_ipc_i2c_cntrl(u32 addr, u32 *data); 579a58a333SSreedhara DS 589a58a333SSreedhara DS /* Update FW version */ 599a58a333SSreedhara DS int intel_scu_ipc_fw_update(u8 *buffer, u32 length); 609a58a333SSreedhara DS 619a58a333SSreedhara DS #endif 62