110043e02SThomas Gleixner #ifndef _ASM_INTEL_DS_H 210043e02SThomas Gleixner #define _ASM_INTEL_DS_H 310043e02SThomas Gleixner 410043e02SThomas Gleixner #include <linux/percpu-defs.h> 510043e02SThomas Gleixner 610043e02SThomas Gleixner #define BTS_BUFFER_SIZE (PAGE_SIZE << 4) 710043e02SThomas Gleixner #define PEBS_BUFFER_SIZE (PAGE_SIZE << 4) 810043e02SThomas Gleixner 910043e02SThomas Gleixner /* The maximal number of PEBS events: */ 1010043e02SThomas Gleixner #define MAX_PEBS_EVENTS 8 11ec71a398SKan Liang #define MAX_FIXED_PEBS_EVENTS 3 1210043e02SThomas Gleixner 1310043e02SThomas Gleixner /* 1410043e02SThomas Gleixner * A debug store configuration. 1510043e02SThomas Gleixner * 1610043e02SThomas Gleixner * We only support architectures that use 64bit fields. 1710043e02SThomas Gleixner */ 1810043e02SThomas Gleixner struct debug_store { 1910043e02SThomas Gleixner u64 bts_buffer_base; 2010043e02SThomas Gleixner u64 bts_index; 2110043e02SThomas Gleixner u64 bts_absolute_maximum; 2210043e02SThomas Gleixner u64 bts_interrupt_threshold; 2310043e02SThomas Gleixner u64 pebs_buffer_base; 2410043e02SThomas Gleixner u64 pebs_index; 2510043e02SThomas Gleixner u64 pebs_absolute_maximum; 2610043e02SThomas Gleixner u64 pebs_interrupt_threshold; 27ec71a398SKan Liang u64 pebs_event_reset[MAX_PEBS_EVENTS + MAX_FIXED_PEBS_EVENTS]; 2810043e02SThomas Gleixner } __aligned(PAGE_SIZE); 2910043e02SThomas Gleixner 3010043e02SThomas Gleixner DECLARE_PER_CPU_PAGE_ALIGNED(struct debug_store, cpu_debug_store); 3110043e02SThomas Gleixner 3210043e02SThomas Gleixner struct debug_store_buffers { 3310043e02SThomas Gleixner char bts_buffer[BTS_BUFFER_SIZE]; 3410043e02SThomas Gleixner char pebs_buffer[PEBS_BUFFER_SIZE]; 3510043e02SThomas Gleixner }; 3610043e02SThomas Gleixner 3710043e02SThomas Gleixner #endif 38