xref: /openbmc/linux/arch/x86/include/asm/intel_ds.h (revision 2145e77f)
110043e02SThomas Gleixner #ifndef _ASM_INTEL_DS_H
210043e02SThomas Gleixner #define _ASM_INTEL_DS_H
310043e02SThomas Gleixner 
410043e02SThomas Gleixner #include <linux/percpu-defs.h>
510043e02SThomas Gleixner 
610043e02SThomas Gleixner #define BTS_BUFFER_SIZE		(PAGE_SIZE << 4)
710043e02SThomas Gleixner #define PEBS_BUFFER_SIZE	(PAGE_SIZE << 4)
810043e02SThomas Gleixner 
910043e02SThomas Gleixner /* The maximal number of PEBS events: */
10*2145e77fSKan Liang #define MAX_PEBS_EVENTS_FMT4	8
11*2145e77fSKan Liang #define MAX_PEBS_EVENTS		32
12*2145e77fSKan Liang #define MAX_FIXED_PEBS_EVENTS	16
1310043e02SThomas Gleixner 
1410043e02SThomas Gleixner /*
1510043e02SThomas Gleixner  * A debug store configuration.
1610043e02SThomas Gleixner  *
1710043e02SThomas Gleixner  * We only support architectures that use 64bit fields.
1810043e02SThomas Gleixner  */
1910043e02SThomas Gleixner struct debug_store {
2010043e02SThomas Gleixner 	u64	bts_buffer_base;
2110043e02SThomas Gleixner 	u64	bts_index;
2210043e02SThomas Gleixner 	u64	bts_absolute_maximum;
2310043e02SThomas Gleixner 	u64	bts_interrupt_threshold;
2410043e02SThomas Gleixner 	u64	pebs_buffer_base;
2510043e02SThomas Gleixner 	u64	pebs_index;
2610043e02SThomas Gleixner 	u64	pebs_absolute_maximum;
2710043e02SThomas Gleixner 	u64	pebs_interrupt_threshold;
28ec71a398SKan Liang 	u64	pebs_event_reset[MAX_PEBS_EVENTS + MAX_FIXED_PEBS_EVENTS];
2910043e02SThomas Gleixner } __aligned(PAGE_SIZE);
3010043e02SThomas Gleixner 
3110043e02SThomas Gleixner DECLARE_PER_CPU_PAGE_ALIGNED(struct debug_store, cpu_debug_store);
3210043e02SThomas Gleixner 
3310043e02SThomas Gleixner struct debug_store_buffers {
3410043e02SThomas Gleixner 	char	bts_buffer[BTS_BUFFER_SIZE];
3510043e02SThomas Gleixner 	char	pebs_buffer[PEBS_BUFFER_SIZE];
3610043e02SThomas Gleixner };
3710043e02SThomas Gleixner 
3810043e02SThomas Gleixner #endif
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