1 /* 2 * intel-mid.h: Intel MID specific setup code 3 * 4 * (C) Copyright 2009 Intel Corporation 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; version 2 9 * of the License. 10 */ 11 #ifndef _ASM_X86_INTEL_MID_H 12 #define _ASM_X86_INTEL_MID_H 13 14 #include <linux/sfi.h> 15 #include <linux/platform_device.h> 16 17 extern int intel_mid_pci_init(void); 18 extern int get_gpio_by_name(const char *name); 19 extern void intel_scu_device_register(struct platform_device *pdev); 20 extern int __init sfi_parse_mrtc(struct sfi_table_header *table); 21 extern int __init sfi_parse_mtmr(struct sfi_table_header *table); 22 extern int sfi_mrtc_num; 23 extern struct sfi_rtc_table_entry sfi_mrtc_array[]; 24 25 /* 26 * Here defines the array of devices platform data that IAFW would export 27 * through SFI "DEVS" table, we use name and type to match the device and 28 * its platform data. 29 */ 30 struct devs_id { 31 char name[SFI_NAME_LEN + 1]; 32 u8 type; 33 u8 delay; 34 void *(*get_platform_data)(void *info); 35 /* Custom handler for devices */ 36 void (*device_handler)(struct sfi_device_table_entry *pentry, 37 struct devs_id *dev); 38 }; 39 40 #define sfi_device(i) \ 41 static const struct devs_id *const __intel_mid_sfi_##i##_dev __used \ 42 __attribute__((__section__(".x86_intel_mid_dev.init"))) = &i 43 44 /* 45 * Medfield is the follow-up of Moorestown, it combines two chip solution into 46 * one. Other than that it also added always-on and constant tsc and lapic 47 * timers. Medfield is the platform name, and the chip name is called Penwell 48 * we treat Medfield/Penwell as a variant of Moorestown. Penwell can be 49 * identified via MSRs. 50 */ 51 enum intel_mid_cpu_type { 52 /* 1 was Moorestown */ 53 INTEL_MID_CPU_CHIP_PENWELL = 2, 54 }; 55 56 extern enum intel_mid_cpu_type __intel_mid_cpu_chip; 57 58 #ifdef CONFIG_X86_INTEL_MID 59 60 static inline enum intel_mid_cpu_type intel_mid_identify_cpu(void) 61 { 62 return __intel_mid_cpu_chip; 63 } 64 65 static inline bool intel_mid_has_msic(void) 66 { 67 return (intel_mid_identify_cpu() == INTEL_MID_CPU_CHIP_PENWELL); 68 } 69 70 #else /* !CONFIG_X86_INTEL_MID */ 71 72 #define intel_mid_identify_cpu() (0) 73 #define intel_mid_has_msic() (0) 74 75 #endif /* !CONFIG_X86_INTEL_MID */ 76 77 enum intel_mid_timer_options { 78 INTEL_MID_TIMER_DEFAULT, 79 INTEL_MID_TIMER_APBT_ONLY, 80 INTEL_MID_TIMER_LAPIC_APBT, 81 }; 82 83 extern enum intel_mid_timer_options intel_mid_timer_options; 84 85 /* 86 * Penwell uses spread spectrum clock, so the freq number is not exactly 87 * the same as reported by MSR based on SDM. 88 */ 89 #define PENWELL_FSB_FREQ_83SKU 83200 90 #define PENWELL_FSB_FREQ_100SKU 99840 91 92 #define SFI_MTMR_MAX_NUM 8 93 #define SFI_MRTC_MAX 8 94 95 extern struct console early_mrst_console; 96 extern void mrst_early_console_init(void); 97 98 extern struct console early_hsu_console; 99 extern void hsu_early_console_init(const char *); 100 101 extern void intel_scu_devices_create(void); 102 extern void intel_scu_devices_destroy(void); 103 104 /* VRTC timer */ 105 #define MRST_VRTC_MAP_SZ (1024) 106 /*#define MRST_VRTC_PGOFFSET (0xc00) */ 107 108 extern void intel_mid_rtc_init(void); 109 110 /* the offset for the mapping of global gpio pin to irq */ 111 #define INTEL_MID_IRQ_OFFSET 0x100 112 113 #endif /* _ASM_X86_INTEL_MID_H */ 114