1 /* 2 * intel-mid.h: Intel MID specific setup code 3 * 4 * (C) Copyright 2009 Intel Corporation 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; version 2 9 * of the License. 10 */ 11 #ifndef _ASM_X86_INTEL_MID_H 12 #define _ASM_X86_INTEL_MID_H 13 14 #include <linux/sfi.h> 15 #include <linux/pci.h> 16 #include <linux/platform_device.h> 17 18 extern int intel_mid_pci_init(void); 19 extern int intel_mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state); 20 21 extern void intel_mid_pwr_power_off(void); 22 23 #define INTEL_MID_PWR_LSS_OFFSET 4 24 #define INTEL_MID_PWR_LSS_TYPE (1 << 7) 25 26 extern int intel_mid_pwr_get_lss_id(struct pci_dev *pdev); 27 28 extern int get_gpio_by_name(const char *name); 29 extern void intel_scu_device_register(struct platform_device *pdev); 30 extern int __init sfi_parse_mrtc(struct sfi_table_header *table); 31 extern int __init sfi_parse_mtmr(struct sfi_table_header *table); 32 extern int sfi_mrtc_num; 33 extern struct sfi_rtc_table_entry sfi_mrtc_array[]; 34 35 /* 36 * Here defines the array of devices platform data that IAFW would export 37 * through SFI "DEVS" table, we use name and type to match the device and 38 * its platform data. 39 */ 40 struct devs_id { 41 char name[SFI_NAME_LEN + 1]; 42 u8 type; 43 u8 delay; 44 void *(*get_platform_data)(void *info); 45 /* Custom handler for devices */ 46 void (*device_handler)(struct sfi_device_table_entry *pentry, 47 struct devs_id *dev); 48 }; 49 50 #define sfi_device(i) \ 51 static const struct devs_id *const __intel_mid_sfi_##i##_dev __used \ 52 __attribute__((__section__(".x86_intel_mid_dev.init"))) = &i 53 54 /** 55 * struct mid_sd_board_info - template for SD device creation 56 * @name: identifies the driver 57 * @bus_num: board-specific identifier for a given SD controller 58 * @max_clk: the maximum frequency device supports 59 * @platform_data: the particular data stored there is driver-specific 60 */ 61 struct mid_sd_board_info { 62 char name[SFI_NAME_LEN]; 63 int bus_num; 64 unsigned short addr; 65 u32 max_clk; 66 void *platform_data; 67 }; 68 69 /* 70 * Medfield is the follow-up of Moorestown, it combines two chip solution into 71 * one. Other than that it also added always-on and constant tsc and lapic 72 * timers. Medfield is the platform name, and the chip name is called Penwell 73 * we treat Medfield/Penwell as a variant of Moorestown. Penwell can be 74 * identified via MSRs. 75 */ 76 enum intel_mid_cpu_type { 77 /* 1 was Moorestown */ 78 INTEL_MID_CPU_CHIP_PENWELL = 2, 79 INTEL_MID_CPU_CHIP_CLOVERVIEW, 80 INTEL_MID_CPU_CHIP_TANGIER, 81 }; 82 83 extern enum intel_mid_cpu_type __intel_mid_cpu_chip; 84 85 /** 86 * struct intel_mid_ops - Interface between intel-mid & sub archs 87 * @arch_setup: arch_setup function to re-initialize platform 88 * structures (x86_init, x86_platform_init) 89 * 90 * This structure can be extended if any new interface is required 91 * between intel-mid & its sub arch files. 92 */ 93 struct intel_mid_ops { 94 void (*arch_setup)(void); 95 }; 96 97 /* Helper API's for INTEL_MID_OPS_INIT */ 98 #define DECLARE_INTEL_MID_OPS_INIT(cpuname, cpuid) \ 99 [cpuid] = get_##cpuname##_ops 100 101 /* Maximum number of CPU ops */ 102 #define MAX_CPU_OPS(a) (sizeof(a)/sizeof(void *)) 103 104 /* 105 * For every new cpu addition, a weak get_<cpuname>_ops() function needs be 106 * declared in arch/x86/platform/intel_mid/intel_mid_weak_decls.h. 107 */ 108 #define INTEL_MID_OPS_INIT { \ 109 DECLARE_INTEL_MID_OPS_INIT(penwell, INTEL_MID_CPU_CHIP_PENWELL), \ 110 DECLARE_INTEL_MID_OPS_INIT(cloverview, INTEL_MID_CPU_CHIP_CLOVERVIEW), \ 111 DECLARE_INTEL_MID_OPS_INIT(tangier, INTEL_MID_CPU_CHIP_TANGIER) \ 112 }; 113 114 #ifdef CONFIG_X86_INTEL_MID 115 116 static inline enum intel_mid_cpu_type intel_mid_identify_cpu(void) 117 { 118 return __intel_mid_cpu_chip; 119 } 120 121 static inline bool intel_mid_has_msic(void) 122 { 123 return (intel_mid_identify_cpu() == INTEL_MID_CPU_CHIP_PENWELL); 124 } 125 126 #else /* !CONFIG_X86_INTEL_MID */ 127 128 #define intel_mid_identify_cpu() 0 129 #define intel_mid_has_msic() 0 130 131 #endif /* !CONFIG_X86_INTEL_MID */ 132 133 enum intel_mid_timer_options { 134 INTEL_MID_TIMER_DEFAULT, 135 INTEL_MID_TIMER_APBT_ONLY, 136 INTEL_MID_TIMER_LAPIC_APBT, 137 }; 138 139 extern enum intel_mid_timer_options intel_mid_timer_options; 140 141 /* 142 * Penwell uses spread spectrum clock, so the freq number is not exactly 143 * the same as reported by MSR based on SDM. 144 */ 145 #define FSB_FREQ_83SKU 83200 146 #define FSB_FREQ_100SKU 99840 147 #define FSB_FREQ_133SKU 133000 148 149 #define FSB_FREQ_167SKU 167000 150 #define FSB_FREQ_200SKU 200000 151 #define FSB_FREQ_267SKU 267000 152 #define FSB_FREQ_333SKU 333000 153 #define FSB_FREQ_400SKU 400000 154 155 /* Bus Select SoC Fuse value */ 156 #define BSEL_SOC_FUSE_MASK 0x7 157 /* FSB 133MHz */ 158 #define BSEL_SOC_FUSE_001 0x1 159 /* FSB 100MHz */ 160 #define BSEL_SOC_FUSE_101 0x5 161 /* FSB 83MHz */ 162 #define BSEL_SOC_FUSE_111 0x7 163 164 #define SFI_MTMR_MAX_NUM 8 165 #define SFI_MRTC_MAX 8 166 167 extern void intel_scu_devices_create(void); 168 extern void intel_scu_devices_destroy(void); 169 170 /* VRTC timer */ 171 #define MRST_VRTC_MAP_SZ 1024 172 /* #define MRST_VRTC_PGOFFSET 0xc00 */ 173 174 extern void intel_mid_rtc_init(void); 175 176 /* The offset for the mapping of global gpio pin to irq */ 177 #define INTEL_MID_IRQ_OFFSET 0x100 178 179 #endif /* _ASM_X86_INTEL_MID_H */ 180