1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * intel-mid.h: Intel MID specific setup code 4 * 5 * (C) Copyright 2009 Intel Corporation 6 */ 7 #ifndef _ASM_X86_INTEL_MID_H 8 #define _ASM_X86_INTEL_MID_H 9 10 #include <linux/sfi.h> 11 #include <linux/pci.h> 12 #include <linux/platform_device.h> 13 14 extern int intel_mid_pci_init(void); 15 extern int intel_mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state); 16 extern pci_power_t intel_mid_pci_get_power_state(struct pci_dev *pdev); 17 18 extern void intel_mid_pwr_power_off(void); 19 20 #define INTEL_MID_PWR_LSS_OFFSET 4 21 #define INTEL_MID_PWR_LSS_TYPE (1 << 7) 22 23 extern int intel_mid_pwr_get_lss_id(struct pci_dev *pdev); 24 25 extern int get_gpio_by_name(const char *name); 26 extern int __init sfi_parse_mrtc(struct sfi_table_header *table); 27 extern int __init sfi_parse_mtmr(struct sfi_table_header *table); 28 extern int sfi_mrtc_num; 29 extern struct sfi_rtc_table_entry sfi_mrtc_array[]; 30 31 /* 32 * Here defines the array of devices platform data that IAFW would export 33 * through SFI "DEVS" table, we use name and type to match the device and 34 * its platform data. 35 */ 36 struct devs_id { 37 char name[SFI_NAME_LEN + 1]; 38 u8 type; 39 u8 delay; 40 void *(*get_platform_data)(void *info); 41 }; 42 43 #define sfi_device(i) \ 44 static const struct devs_id *const __intel_mid_sfi_##i##_dev __used \ 45 __section(".x86_intel_mid_dev.init") = &i 46 47 /** 48 * struct mid_sd_board_info - template for SD device creation 49 * @name: identifies the driver 50 * @bus_num: board-specific identifier for a given SD controller 51 * @max_clk: the maximum frequency device supports 52 * @platform_data: the particular data stored there is driver-specific 53 */ 54 struct mid_sd_board_info { 55 char name[SFI_NAME_LEN]; 56 int bus_num; 57 unsigned short addr; 58 u32 max_clk; 59 void *platform_data; 60 }; 61 62 /* 63 * Medfield is the follow-up of Moorestown, it combines two chip solution into 64 * one. Other than that it also added always-on and constant tsc and lapic 65 * timers. Medfield is the platform name, and the chip name is called Penwell 66 * we treat Medfield/Penwell as a variant of Moorestown. Penwell can be 67 * identified via MSRs. 68 */ 69 enum intel_mid_cpu_type { 70 /* 1 was Moorestown */ 71 INTEL_MID_CPU_CHIP_PENWELL = 2, 72 INTEL_MID_CPU_CHIP_CLOVERVIEW, 73 INTEL_MID_CPU_CHIP_TANGIER, 74 }; 75 76 extern enum intel_mid_cpu_type __intel_mid_cpu_chip; 77 78 #ifdef CONFIG_X86_INTEL_MID 79 80 static inline enum intel_mid_cpu_type intel_mid_identify_cpu(void) 81 { 82 return __intel_mid_cpu_chip; 83 } 84 85 extern void intel_scu_devices_create(void); 86 extern void intel_scu_devices_destroy(void); 87 88 #else /* !CONFIG_X86_INTEL_MID */ 89 90 #define intel_mid_identify_cpu() 0 91 92 static inline void intel_scu_devices_create(void) { } 93 static inline void intel_scu_devices_destroy(void) { } 94 95 #endif /* !CONFIG_X86_INTEL_MID */ 96 97 enum intel_mid_timer_options { 98 INTEL_MID_TIMER_DEFAULT, 99 INTEL_MID_TIMER_APBT_ONLY, 100 INTEL_MID_TIMER_LAPIC_APBT, 101 }; 102 103 extern enum intel_mid_timer_options intel_mid_timer_options; 104 105 /* Bus Select SoC Fuse value */ 106 #define BSEL_SOC_FUSE_MASK 0x7 107 /* FSB 133MHz */ 108 #define BSEL_SOC_FUSE_001 0x1 109 /* FSB 100MHz */ 110 #define BSEL_SOC_FUSE_101 0x5 111 /* FSB 83MHz */ 112 #define BSEL_SOC_FUSE_111 0x7 113 114 #define SFI_MTMR_MAX_NUM 8 115 #define SFI_MRTC_MAX 8 116 117 /* VRTC timer */ 118 #define MRST_VRTC_MAP_SZ 1024 119 /* #define MRST_VRTC_PGOFFSET 0xc00 */ 120 121 extern void intel_mid_rtc_init(void); 122 123 /* The offset for the mapping of global gpio pin to irq */ 124 #define INTEL_MID_IRQ_OFFSET 0x100 125 126 #endif /* _ASM_X86_INTEL_MID_H */ 127