1 /* 2 * intel-mid.h: Intel MID specific setup code 3 * 4 * (C) Copyright 2009 Intel Corporation 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; version 2 9 * of the License. 10 */ 11 #ifndef _ASM_X86_INTEL_MID_H 12 #define _ASM_X86_INTEL_MID_H 13 14 #include <linux/sfi.h> 15 16 extern int intel_mid_pci_init(void); 17 extern int __init sfi_parse_mrtc(struct sfi_table_header *table); 18 extern int sfi_mrtc_num; 19 extern struct sfi_rtc_table_entry sfi_mrtc_array[]; 20 21 /* 22 * Here defines the array of devices platform data that IAFW would export 23 * through SFI "DEVS" table, we use name and type to match the device and 24 * its platform data. 25 */ 26 struct devs_id { 27 char name[SFI_NAME_LEN + 1]; 28 u8 type; 29 u8 delay; 30 void *(*get_platform_data)(void *info); 31 /* Custom handler for devices */ 32 void (*device_handler)(struct sfi_device_table_entry *pentry, 33 struct devs_id *dev); 34 }; 35 36 /* 37 * Medfield is the follow-up of Moorestown, it combines two chip solution into 38 * one. Other than that it also added always-on and constant tsc and lapic 39 * timers. Medfield is the platform name, and the chip name is called Penwell 40 * we treat Medfield/Penwell as a variant of Moorestown. Penwell can be 41 * identified via MSRs. 42 */ 43 enum intel_mid_cpu_type { 44 /* 1 was Moorestown */ 45 INTEL_MID_CPU_CHIP_PENWELL = 2, 46 }; 47 48 extern enum intel_mid_cpu_type __intel_mid_cpu_chip; 49 50 #ifdef CONFIG_X86_INTEL_MID 51 52 static inline enum intel_mid_cpu_type intel_mid_identify_cpu(void) 53 { 54 return __intel_mid_cpu_chip; 55 } 56 57 #else /* !CONFIG_X86_INTEL_MID */ 58 59 #define intel_mid_identify_cpu() (0) 60 61 #endif /* !CONFIG_X86_INTEL_MID */ 62 63 enum intel_mid_timer_options { 64 INTEL_MID_TIMER_DEFAULT, 65 INTEL_MID_TIMER_APBT_ONLY, 66 INTEL_MID_TIMER_LAPIC_APBT, 67 }; 68 69 extern enum intel_mid_timer_options intel_mid_timer_options; 70 71 /* 72 * Penwell uses spread spectrum clock, so the freq number is not exactly 73 * the same as reported by MSR based on SDM. 74 */ 75 #define PENWELL_FSB_FREQ_83SKU 83200 76 #define PENWELL_FSB_FREQ_100SKU 99840 77 78 #define SFI_MTMR_MAX_NUM 8 79 #define SFI_MRTC_MAX 8 80 81 extern struct console early_mrst_console; 82 extern void mrst_early_console_init(void); 83 84 extern struct console early_hsu_console; 85 extern void hsu_early_console_init(const char *); 86 87 extern void intel_scu_devices_create(void); 88 extern void intel_scu_devices_destroy(void); 89 90 /* VRTC timer */ 91 #define MRST_VRTC_MAP_SZ (1024) 92 /*#define MRST_VRTC_PGOFFSET (0xc00) */ 93 94 extern void intel_mid_rtc_init(void); 95 96 #endif /* _ASM_X86_INTEL_MID_H */ 97