1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * intel-mid.h: Intel MID specific setup code 4 * 5 * (C) Copyright 2009 Intel Corporation 6 */ 7 #ifndef _ASM_X86_INTEL_MID_H 8 #define _ASM_X86_INTEL_MID_H 9 10 #include <linux/pci.h> 11 #include <linux/platform_device.h> 12 13 extern int intel_mid_pci_init(void); 14 extern int intel_mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state); 15 extern pci_power_t intel_mid_pci_get_power_state(struct pci_dev *pdev); 16 17 extern void intel_mid_pwr_power_off(void); 18 19 #define INTEL_MID_PWR_LSS_OFFSET 4 20 #define INTEL_MID_PWR_LSS_TYPE (1 << 7) 21 22 extern int intel_mid_pwr_get_lss_id(struct pci_dev *pdev); 23 24 /* 25 * Medfield is the follow-up of Moorestown, it combines two chip solution into 26 * one. Other than that it also added always-on and constant tsc and lapic 27 * timers. Medfield is the platform name, and the chip name is called Penwell 28 * we treat Medfield/Penwell as a variant of Moorestown. Penwell can be 29 * identified via MSRs. 30 */ 31 enum intel_mid_cpu_type { 32 /* 1 was Moorestown */ 33 INTEL_MID_CPU_CHIP_PENWELL = 2, 34 INTEL_MID_CPU_CHIP_CLOVERVIEW, 35 INTEL_MID_CPU_CHIP_TANGIER, 36 }; 37 38 extern enum intel_mid_cpu_type __intel_mid_cpu_chip; 39 40 #ifdef CONFIG_X86_INTEL_MID 41 42 static inline enum intel_mid_cpu_type intel_mid_identify_cpu(void) 43 { 44 return __intel_mid_cpu_chip; 45 } 46 47 extern void intel_scu_devices_create(void); 48 extern void intel_scu_devices_destroy(void); 49 50 #else /* !CONFIG_X86_INTEL_MID */ 51 52 #define intel_mid_identify_cpu() 0 53 54 static inline void intel_scu_devices_create(void) { } 55 static inline void intel_scu_devices_destroy(void) { } 56 57 #endif /* !CONFIG_X86_INTEL_MID */ 58 59 /* Bus Select SoC Fuse value */ 60 #define BSEL_SOC_FUSE_MASK 0x7 61 /* FSB 133MHz */ 62 #define BSEL_SOC_FUSE_001 0x1 63 /* FSB 100MHz */ 64 #define BSEL_SOC_FUSE_101 0x5 65 /* FSB 83MHz */ 66 #define BSEL_SOC_FUSE_111 0x7 67 68 #endif /* _ASM_X86_INTEL_MID_H */ 69