1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * intel-mid.h: Intel MID specific setup code 4 * 5 * (C) Copyright 2009 Intel Corporation 6 */ 7 #ifndef _ASM_X86_INTEL_MID_H 8 #define _ASM_X86_INTEL_MID_H 9 10 #include <linux/sfi.h> 11 #include <linux/pci.h> 12 #include <linux/platform_device.h> 13 14 extern int intel_mid_pci_init(void); 15 extern int intel_mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state); 16 extern pci_power_t intel_mid_pci_get_power_state(struct pci_dev *pdev); 17 18 extern void intel_mid_pwr_power_off(void); 19 20 #define INTEL_MID_PWR_LSS_OFFSET 4 21 #define INTEL_MID_PWR_LSS_TYPE (1 << 7) 22 23 extern int intel_mid_pwr_get_lss_id(struct pci_dev *pdev); 24 25 extern int get_gpio_by_name(const char *name); 26 27 /* 28 * Here defines the array of devices platform data that IAFW would export 29 * through SFI "DEVS" table, we use name and type to match the device and 30 * its platform data. 31 */ 32 struct devs_id { 33 char name[SFI_NAME_LEN + 1]; 34 u8 type; 35 u8 delay; 36 void *(*get_platform_data)(void *info); 37 }; 38 39 #define sfi_device(i) \ 40 static const struct devs_id *const __intel_mid_sfi_##i##_dev __used \ 41 __section(".x86_intel_mid_dev.init") = &i 42 43 /** 44 * struct mid_sd_board_info - template for SD device creation 45 * @name: identifies the driver 46 * @bus_num: board-specific identifier for a given SD controller 47 * @max_clk: the maximum frequency device supports 48 * @platform_data: the particular data stored there is driver-specific 49 */ 50 struct mid_sd_board_info { 51 char name[SFI_NAME_LEN]; 52 int bus_num; 53 unsigned short addr; 54 u32 max_clk; 55 void *platform_data; 56 }; 57 58 /* 59 * Medfield is the follow-up of Moorestown, it combines two chip solution into 60 * one. Other than that it also added always-on and constant tsc and lapic 61 * timers. Medfield is the platform name, and the chip name is called Penwell 62 * we treat Medfield/Penwell as a variant of Moorestown. Penwell can be 63 * identified via MSRs. 64 */ 65 enum intel_mid_cpu_type { 66 /* 1 was Moorestown */ 67 INTEL_MID_CPU_CHIP_PENWELL = 2, 68 INTEL_MID_CPU_CHIP_CLOVERVIEW, 69 INTEL_MID_CPU_CHIP_TANGIER, 70 }; 71 72 extern enum intel_mid_cpu_type __intel_mid_cpu_chip; 73 74 #ifdef CONFIG_X86_INTEL_MID 75 76 static inline enum intel_mid_cpu_type intel_mid_identify_cpu(void) 77 { 78 return __intel_mid_cpu_chip; 79 } 80 81 extern void intel_scu_devices_create(void); 82 extern void intel_scu_devices_destroy(void); 83 84 #else /* !CONFIG_X86_INTEL_MID */ 85 86 #define intel_mid_identify_cpu() 0 87 88 static inline void intel_scu_devices_create(void) { } 89 static inline void intel_scu_devices_destroy(void) { } 90 91 #endif /* !CONFIG_X86_INTEL_MID */ 92 93 /* Bus Select SoC Fuse value */ 94 #define BSEL_SOC_FUSE_MASK 0x7 95 /* FSB 133MHz */ 96 #define BSEL_SOC_FUSE_001 0x1 97 /* FSB 100MHz */ 98 #define BSEL_SOC_FUSE_101 0x5 99 /* FSB 83MHz */ 100 #define BSEL_SOC_FUSE_111 0x7 101 102 /* The offset for the mapping of global gpio pin to irq */ 103 #define INTEL_MID_IRQ_OFFSET 0x100 104 105 #endif /* _ASM_X86_INTEL_MID_H */ 106