1 /* 2 * intel-mid.h: Intel MID specific setup code 3 * 4 * (C) Copyright 2009 Intel Corporation 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; version 2 9 * of the License. 10 */ 11 #ifndef _ASM_X86_INTEL_MID_H 12 #define _ASM_X86_INTEL_MID_H 13 14 #include <linux/sfi.h> 15 #include <linux/pci.h> 16 #include <linux/platform_device.h> 17 18 extern int intel_mid_pci_init(void); 19 extern int intel_mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state); 20 extern pci_power_t intel_mid_pci_get_power_state(struct pci_dev *pdev); 21 22 extern void intel_mid_pwr_power_off(void); 23 24 #define INTEL_MID_PWR_LSS_OFFSET 4 25 #define INTEL_MID_PWR_LSS_TYPE (1 << 7) 26 27 extern int intel_mid_pwr_get_lss_id(struct pci_dev *pdev); 28 29 extern int get_gpio_by_name(const char *name); 30 extern int __init sfi_parse_mrtc(struct sfi_table_header *table); 31 extern int __init sfi_parse_mtmr(struct sfi_table_header *table); 32 extern int sfi_mrtc_num; 33 extern struct sfi_rtc_table_entry sfi_mrtc_array[]; 34 35 /* 36 * Here defines the array of devices platform data that IAFW would export 37 * through SFI "DEVS" table, we use name and type to match the device and 38 * its platform data. 39 */ 40 struct devs_id { 41 char name[SFI_NAME_LEN + 1]; 42 u8 type; 43 u8 delay; 44 u8 msic; 45 void *(*get_platform_data)(void *info); 46 }; 47 48 #define sfi_device(i) \ 49 static const struct devs_id *const __intel_mid_sfi_##i##_dev __used \ 50 __attribute__((__section__(".x86_intel_mid_dev.init"))) = &i 51 52 /** 53 * struct mid_sd_board_info - template for SD device creation 54 * @name: identifies the driver 55 * @bus_num: board-specific identifier for a given SD controller 56 * @max_clk: the maximum frequency device supports 57 * @platform_data: the particular data stored there is driver-specific 58 */ 59 struct mid_sd_board_info { 60 char name[SFI_NAME_LEN]; 61 int bus_num; 62 unsigned short addr; 63 u32 max_clk; 64 void *platform_data; 65 }; 66 67 /* 68 * Medfield is the follow-up of Moorestown, it combines two chip solution into 69 * one. Other than that it also added always-on and constant tsc and lapic 70 * timers. Medfield is the platform name, and the chip name is called Penwell 71 * we treat Medfield/Penwell as a variant of Moorestown. Penwell can be 72 * identified via MSRs. 73 */ 74 enum intel_mid_cpu_type { 75 /* 1 was Moorestown */ 76 INTEL_MID_CPU_CHIP_PENWELL = 2, 77 INTEL_MID_CPU_CHIP_CLOVERVIEW, 78 INTEL_MID_CPU_CHIP_TANGIER, 79 }; 80 81 extern enum intel_mid_cpu_type __intel_mid_cpu_chip; 82 83 #ifdef CONFIG_X86_INTEL_MID 84 85 static inline enum intel_mid_cpu_type intel_mid_identify_cpu(void) 86 { 87 return __intel_mid_cpu_chip; 88 } 89 90 static inline bool intel_mid_has_msic(void) 91 { 92 return (intel_mid_identify_cpu() == INTEL_MID_CPU_CHIP_PENWELL); 93 } 94 95 #else /* !CONFIG_X86_INTEL_MID */ 96 97 #define intel_mid_identify_cpu() 0 98 #define intel_mid_has_msic() 0 99 100 #endif /* !CONFIG_X86_INTEL_MID */ 101 102 enum intel_mid_timer_options { 103 INTEL_MID_TIMER_DEFAULT, 104 INTEL_MID_TIMER_APBT_ONLY, 105 INTEL_MID_TIMER_LAPIC_APBT, 106 }; 107 108 extern enum intel_mid_timer_options intel_mid_timer_options; 109 110 /* Bus Select SoC Fuse value */ 111 #define BSEL_SOC_FUSE_MASK 0x7 112 /* FSB 133MHz */ 113 #define BSEL_SOC_FUSE_001 0x1 114 /* FSB 100MHz */ 115 #define BSEL_SOC_FUSE_101 0x5 116 /* FSB 83MHz */ 117 #define BSEL_SOC_FUSE_111 0x7 118 119 #define SFI_MTMR_MAX_NUM 8 120 #define SFI_MRTC_MAX 8 121 122 extern void intel_scu_devices_create(void); 123 extern void intel_scu_devices_destroy(void); 124 125 /* VRTC timer */ 126 #define MRST_VRTC_MAP_SZ 1024 127 /* #define MRST_VRTC_PGOFFSET 0xc00 */ 128 129 extern void intel_mid_rtc_init(void); 130 131 /* The offset for the mapping of global gpio pin to irq */ 132 #define INTEL_MID_IRQ_OFFSET 0x100 133 134 #endif /* _ASM_X86_INTEL_MID_H */ 135