1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _ASM_X86_INTEL_FAMILY_H
3 #define _ASM_X86_INTEL_FAMILY_H
4 
5 /*
6  * "Big Core" Processors (Branded as Core, Xeon, etc...)
7  *
8  * While adding a new CPUID for a new microarchitecture, add a new
9  * group to keep logically sorted out in chronological order. Within
10  * that group keep the CPUID for the variants sorted by model number.
11  *
12  * The defined symbol names have the following form:
13  *	INTEL_FAM6{OPTFAMILY}_{MICROARCH}{OPTDIFF}
14  * where:
15  * OPTFAMILY	Describes the family of CPUs that this belongs to. Default
16  *		is assumed to be "_CORE" (and should be omitted). Other values
17  *		currently in use are _ATOM and _XEON_PHI
18  * MICROARCH	Is the code name for the micro-architecture for this core.
19  *		N.B. Not the platform name.
20  * OPTDIFF	If needed, a short string to differentiate by market segment.
21  *
22  *		Common OPTDIFFs:
23  *
24  *			- regular client parts
25  *		_L	- regular mobile parts
26  *		_G	- parts with extra graphics on
27  *		_X	- regular server parts
28  *		_D	- micro server parts
29  *
30  *		Historical OPTDIFFs:
31  *
32  *		_EP	- 2 socket server parts
33  *		_EX	- 4+ socket server parts
34  *
35  * The #define line may optionally include a comment including platform names.
36  */
37 
38 #define INTEL_FAM6_CORE_YONAH		0x0E
39 
40 #define INTEL_FAM6_CORE2_MEROM		0x0F
41 #define INTEL_FAM6_CORE2_MEROM_L	0x16
42 #define INTEL_FAM6_CORE2_PENRYN		0x17
43 #define INTEL_FAM6_CORE2_DUNNINGTON	0x1D
44 
45 #define INTEL_FAM6_NEHALEM		0x1E
46 #define INTEL_FAM6_NEHALEM_G		0x1F /* Auburndale / Havendale */
47 #define INTEL_FAM6_NEHALEM_EP		0x1A
48 #define INTEL_FAM6_NEHALEM_EX		0x2E
49 
50 #define INTEL_FAM6_WESTMERE		0x25
51 #define INTEL_FAM6_WESTMERE_EP		0x2C
52 #define INTEL_FAM6_WESTMERE_EX		0x2F
53 
54 #define INTEL_FAM6_SANDYBRIDGE		0x2A
55 #define INTEL_FAM6_SANDYBRIDGE_X	0x2D
56 #define INTEL_FAM6_IVYBRIDGE		0x3A
57 #define INTEL_FAM6_IVYBRIDGE_X		0x3E
58 
59 #define INTEL_FAM6_HASWELL		0x3C
60 #define INTEL_FAM6_HASWELL_X		0x3F
61 #define INTEL_FAM6_HASWELL_L		0x45
62 #define INTEL_FAM6_HASWELL_G		0x46
63 
64 #define INTEL_FAM6_BROADWELL		0x3D
65 #define INTEL_FAM6_BROADWELL_G		0x47
66 #define INTEL_FAM6_BROADWELL_X		0x4F
67 #define INTEL_FAM6_BROADWELL_D		0x56
68 
69 #define INTEL_FAM6_SKYLAKE_L		0x4E
70 #define INTEL_FAM6_SKYLAKE		0x5E
71 #define INTEL_FAM6_SKYLAKE_X		0x55
72 #define INTEL_FAM6_KABYLAKE_L		0x8E
73 #define INTEL_FAM6_KABYLAKE		0x9E
74 
75 #define INTEL_FAM6_CANNONLAKE_L		0x66
76 
77 #define INTEL_FAM6_ICELAKE_X		0x6A
78 #define INTEL_FAM6_ICELAKE_D		0x6C
79 #define INTEL_FAM6_ICELAKE		0x7D
80 #define INTEL_FAM6_ICELAKE_L		0x7E
81 #define INTEL_FAM6_ICELAKE_NNPI		0x9D
82 
83 #define INTEL_FAM6_TIGERLAKE_L		0x8C
84 #define INTEL_FAM6_TIGERLAKE		0x8D
85 
86 #define INTEL_FAM6_COMETLAKE		0xA5
87 #define INTEL_FAM6_COMETLAKE_L		0xA6
88 
89 /* "Small Core" Processors (Atom) */
90 
91 #define INTEL_FAM6_ATOM_BONNELL		0x1C /* Diamondville, Pineview */
92 #define INTEL_FAM6_ATOM_BONNELL_MID	0x26 /* Silverthorne, Lincroft */
93 
94 #define INTEL_FAM6_ATOM_SALTWELL	0x36 /* Cedarview */
95 #define INTEL_FAM6_ATOM_SALTWELL_MID	0x27 /* Penwell */
96 #define INTEL_FAM6_ATOM_SALTWELL_TABLET	0x35 /* Cloverview */
97 
98 #define INTEL_FAM6_ATOM_SILVERMONT	0x37 /* Bay Trail, Valleyview */
99 #define INTEL_FAM6_ATOM_SILVERMONT_D	0x4D /* Avaton, Rangely */
100 #define INTEL_FAM6_ATOM_SILVERMONT_MID	0x4A /* Merriefield */
101 
102 #define INTEL_FAM6_ATOM_AIRMONT		0x4C /* Cherry Trail, Braswell */
103 #define INTEL_FAM6_ATOM_AIRMONT_MID	0x5A /* Moorefield */
104 #define INTEL_FAM6_ATOM_AIRMONT_NP	0x75 /* Lightning Mountain */
105 
106 #define INTEL_FAM6_ATOM_GOLDMONT	0x5C /* Apollo Lake */
107 #define INTEL_FAM6_ATOM_GOLDMONT_D	0x5F /* Denverton */
108 
109 /* Note: the micro-architecture is "Goldmont Plus" */
110 #define INTEL_FAM6_ATOM_GOLDMONT_PLUS	0x7A /* Gemini Lake */
111 
112 #define INTEL_FAM6_ATOM_TREMONT_D	0x86 /* Jacobsville */
113 #define INTEL_FAM6_ATOM_TREMONT		0x96 /* Elkhart Lake */
114 #define INTEL_FAM6_ATOM_TREMONT_L	0x9C /* Jasper Lake */
115 
116 /* Xeon Phi */
117 
118 #define INTEL_FAM6_XEON_PHI_KNL		0x57 /* Knights Landing */
119 #define INTEL_FAM6_XEON_PHI_KNM		0x85 /* Knights Mill */
120 
121 /* Useful macros */
122 #define INTEL_CPU_FAM_ANY(_family, _model, _driver_data)	\
123 {								\
124 	.vendor		= X86_VENDOR_INTEL,			\
125 	.family		= _family,				\
126 	.model		= _model,				\
127 	.feature	= X86_FEATURE_ANY,			\
128 	.driver_data	= (kernel_ulong_t)&_driver_data		\
129 }
130 
131 #define INTEL_CPU_FAM6(_model, _driver_data)			\
132 	INTEL_CPU_FAM_ANY(6, INTEL_FAM6_##_model, _driver_data)
133 
134 #endif /* _ASM_X86_INTEL_FAMILY_H */
135