1 /* SPDX-License-Identifier: GPL-2.0 */ 2 3 /* 4 * This file contains definitions from Hyper-V Hypervisor Top-Level Functional 5 * Specification (TLFS): 6 * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs 7 */ 8 9 #ifndef _ASM_X86_HYPERV_TLFS_H 10 #define _ASM_X86_HYPERV_TLFS_H 11 12 #include <linux/types.h> 13 #include <asm/page.h> 14 /* 15 * The below CPUID leaves are present if VersionAndFeatures.HypervisorPresent 16 * is set by CPUID(HvCpuIdFunctionVersionAndFeatures). 17 */ 18 #define HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS 0x40000000 19 #define HYPERV_CPUID_INTERFACE 0x40000001 20 #define HYPERV_CPUID_VERSION 0x40000002 21 #define HYPERV_CPUID_FEATURES 0x40000003 22 #define HYPERV_CPUID_ENLIGHTMENT_INFO 0x40000004 23 #define HYPERV_CPUID_IMPLEMENT_LIMITS 0x40000005 24 #define HYPERV_CPUID_CPU_MANAGEMENT_FEATURES 0x40000007 25 #define HYPERV_CPUID_NESTED_FEATURES 0x4000000A 26 #define HYPERV_CPUID_ISOLATION_CONFIG 0x4000000C 27 28 #define HYPERV_CPUID_VIRT_STACK_INTERFACE 0x40000081 29 #define HYPERV_VS_INTERFACE_EAX_SIGNATURE 0x31235356 /* "VS#1" */ 30 31 #define HYPERV_CPUID_VIRT_STACK_PROPERTIES 0x40000082 32 /* Support for the extended IOAPIC RTE format */ 33 #define HYPERV_VS_PROPERTIES_EAX_EXTENDED_IOAPIC_RTE BIT(2) 34 35 #define HYPERV_HYPERVISOR_PRESENT_BIT 0x80000000 36 #define HYPERV_CPUID_MIN 0x40000005 37 #define HYPERV_CPUID_MAX 0x4000ffff 38 39 /* 40 * Group D Features. The bit assignments are custom to each architecture. 41 * On x86/x64 these are HYPERV_CPUID_FEATURES.EDX bits. 42 */ 43 /* The MWAIT instruction is available (per section MONITOR / MWAIT) */ 44 #define HV_X64_MWAIT_AVAILABLE BIT(0) 45 /* Guest debugging support is available */ 46 #define HV_X64_GUEST_DEBUGGING_AVAILABLE BIT(1) 47 /* Performance Monitor support is available*/ 48 #define HV_X64_PERF_MONITOR_AVAILABLE BIT(2) 49 /* Support for physical CPU dynamic partitioning events is available*/ 50 #define HV_X64_CPU_DYNAMIC_PARTITIONING_AVAILABLE BIT(3) 51 /* 52 * Support for passing hypercall input parameter block via XMM 53 * registers is available 54 */ 55 #define HV_X64_HYPERCALL_XMM_INPUT_AVAILABLE BIT(4) 56 /* Support for a virtual guest idle state is available */ 57 #define HV_X64_GUEST_IDLE_STATE_AVAILABLE BIT(5) 58 /* Frequency MSRs available */ 59 #define HV_FEATURE_FREQUENCY_MSRS_AVAILABLE BIT(8) 60 /* Crash MSR available */ 61 #define HV_FEATURE_GUEST_CRASH_MSR_AVAILABLE BIT(10) 62 /* Support for debug MSRs available */ 63 #define HV_FEATURE_DEBUG_MSRS_AVAILABLE BIT(11) 64 /* Support for extended gva ranges for flush hypercalls available */ 65 #define HV_FEATURE_EXT_GVA_RANGES_FLUSH BIT(14) 66 /* 67 * Support for returning hypercall output block via XMM 68 * registers is available 69 */ 70 #define HV_X64_HYPERCALL_XMM_OUTPUT_AVAILABLE BIT(15) 71 /* stimer Direct Mode is available */ 72 #define HV_STIMER_DIRECT_MODE_AVAILABLE BIT(19) 73 74 /* 75 * Implementation recommendations. Indicates which behaviors the hypervisor 76 * recommends the OS implement for optimal performance. 77 * These are HYPERV_CPUID_ENLIGHTMENT_INFO.EAX bits. 78 */ 79 /* 80 * Recommend using hypercall for address space switches rather 81 * than MOV to CR3 instruction 82 */ 83 #define HV_X64_AS_SWITCH_RECOMMENDED BIT(0) 84 /* Recommend using hypercall for local TLB flushes rather 85 * than INVLPG or MOV to CR3 instructions */ 86 #define HV_X64_LOCAL_TLB_FLUSH_RECOMMENDED BIT(1) 87 /* 88 * Recommend using hypercall for remote TLB flushes rather 89 * than inter-processor interrupts 90 */ 91 #define HV_X64_REMOTE_TLB_FLUSH_RECOMMENDED BIT(2) 92 /* 93 * Recommend using MSRs for accessing APIC registers 94 * EOI, ICR and TPR rather than their memory-mapped counterparts 95 */ 96 #define HV_X64_APIC_ACCESS_RECOMMENDED BIT(3) 97 /* Recommend using the hypervisor-provided MSR to initiate a system RESET */ 98 #define HV_X64_SYSTEM_RESET_RECOMMENDED BIT(4) 99 /* 100 * Recommend using relaxed timing for this partition. If used, 101 * the VM should disable any watchdog timeouts that rely on the 102 * timely delivery of external interrupts 103 */ 104 #define HV_X64_RELAXED_TIMING_RECOMMENDED BIT(5) 105 106 /* 107 * Recommend not using Auto End-Of-Interrupt feature 108 */ 109 #define HV_DEPRECATING_AEOI_RECOMMENDED BIT(9) 110 111 /* 112 * Recommend using cluster IPI hypercalls. 113 */ 114 #define HV_X64_CLUSTER_IPI_RECOMMENDED BIT(10) 115 116 /* Recommend using the newer ExProcessorMasks interface */ 117 #define HV_X64_EX_PROCESSOR_MASKS_RECOMMENDED BIT(11) 118 119 /* Indicates that the hypervisor is nested within a Hyper-V partition. */ 120 #define HV_X64_HYPERV_NESTED BIT(12) 121 122 /* Recommend using enlightened VMCS */ 123 #define HV_X64_ENLIGHTENED_VMCS_RECOMMENDED BIT(14) 124 125 /* 126 * CPU management features identification. 127 * These are HYPERV_CPUID_CPU_MANAGEMENT_FEATURES.EAX bits. 128 */ 129 #define HV_X64_START_LOGICAL_PROCESSOR BIT(0) 130 #define HV_X64_CREATE_ROOT_VIRTUAL_PROCESSOR BIT(1) 131 #define HV_X64_PERFORMANCE_COUNTER_SYNC BIT(2) 132 #define HV_X64_RESERVED_IDENTITY_BIT BIT(31) 133 134 /* 135 * Virtual processor will never share a physical core with another virtual 136 * processor, except for virtual processors that are reported as sibling SMT 137 * threads. 138 */ 139 #define HV_X64_NO_NONARCH_CORESHARING BIT(18) 140 141 /* Nested features. These are HYPERV_CPUID_NESTED_FEATURES.EAX bits. */ 142 #define HV_X64_NESTED_DIRECT_FLUSH BIT(17) 143 #define HV_X64_NESTED_GUEST_MAPPING_FLUSH BIT(18) 144 #define HV_X64_NESTED_MSR_BITMAP BIT(19) 145 146 /* Nested features #2. These are HYPERV_CPUID_NESTED_FEATURES.EBX bits. */ 147 #define HV_X64_NESTED_EVMCS1_PERF_GLOBAL_CTRL BIT(0) 148 149 /* 150 * This is specific to AMD and specifies that enlightened TLB flush is 151 * supported. If guest opts in to this feature, ASID invalidations only 152 * flushes gva -> hpa mapping entries. To flush the TLB entries derived 153 * from NPT, hypercalls should be used (HvFlushGuestPhysicalAddressSpace 154 * or HvFlushGuestPhysicalAddressList). 155 */ 156 #define HV_X64_NESTED_ENLIGHTENED_TLB BIT(22) 157 158 /* HYPERV_CPUID_ISOLATION_CONFIG.EAX bits. */ 159 #define HV_PARAVISOR_PRESENT BIT(0) 160 161 /* HYPERV_CPUID_ISOLATION_CONFIG.EBX bits. */ 162 #define HV_ISOLATION_TYPE GENMASK(3, 0) 163 #define HV_SHARED_GPA_BOUNDARY_ACTIVE BIT(5) 164 #define HV_SHARED_GPA_BOUNDARY_BITS GENMASK(11, 6) 165 166 enum hv_isolation_type { 167 HV_ISOLATION_TYPE_NONE = 0, 168 HV_ISOLATION_TYPE_VBS = 1, 169 HV_ISOLATION_TYPE_SNP = 2 170 }; 171 172 /* Hyper-V specific model specific registers (MSRs) */ 173 174 /* MSR used to identify the guest OS. */ 175 #define HV_X64_MSR_GUEST_OS_ID 0x40000000 176 177 /* MSR used to setup pages used to communicate with the hypervisor. */ 178 #define HV_X64_MSR_HYPERCALL 0x40000001 179 180 /* MSR used to provide vcpu index */ 181 #define HV_REGISTER_VP_INDEX 0x40000002 182 183 /* MSR used to reset the guest OS. */ 184 #define HV_X64_MSR_RESET 0x40000003 185 186 /* MSR used to provide vcpu runtime in 100ns units */ 187 #define HV_X64_MSR_VP_RUNTIME 0x40000010 188 189 /* MSR used to read the per-partition time reference counter */ 190 #define HV_REGISTER_TIME_REF_COUNT 0x40000020 191 192 /* A partition's reference time stamp counter (TSC) page */ 193 #define HV_REGISTER_REFERENCE_TSC 0x40000021 194 195 /* MSR used to retrieve the TSC frequency */ 196 #define HV_X64_MSR_TSC_FREQUENCY 0x40000022 197 198 /* MSR used to retrieve the local APIC timer frequency */ 199 #define HV_X64_MSR_APIC_FREQUENCY 0x40000023 200 201 /* Define the virtual APIC registers */ 202 #define HV_X64_MSR_EOI 0x40000070 203 #define HV_X64_MSR_ICR 0x40000071 204 #define HV_X64_MSR_TPR 0x40000072 205 #define HV_X64_MSR_VP_ASSIST_PAGE 0x40000073 206 207 /* Define synthetic interrupt controller model specific registers. */ 208 #define HV_REGISTER_SCONTROL 0x40000080 209 #define HV_REGISTER_SVERSION 0x40000081 210 #define HV_REGISTER_SIEFP 0x40000082 211 #define HV_REGISTER_SIMP 0x40000083 212 #define HV_REGISTER_EOM 0x40000084 213 #define HV_REGISTER_SINT0 0x40000090 214 #define HV_REGISTER_SINT1 0x40000091 215 #define HV_REGISTER_SINT2 0x40000092 216 #define HV_REGISTER_SINT3 0x40000093 217 #define HV_REGISTER_SINT4 0x40000094 218 #define HV_REGISTER_SINT5 0x40000095 219 #define HV_REGISTER_SINT6 0x40000096 220 #define HV_REGISTER_SINT7 0x40000097 221 #define HV_REGISTER_SINT8 0x40000098 222 #define HV_REGISTER_SINT9 0x40000099 223 #define HV_REGISTER_SINT10 0x4000009A 224 #define HV_REGISTER_SINT11 0x4000009B 225 #define HV_REGISTER_SINT12 0x4000009C 226 #define HV_REGISTER_SINT13 0x4000009D 227 #define HV_REGISTER_SINT14 0x4000009E 228 #define HV_REGISTER_SINT15 0x4000009F 229 230 /* 231 * Define synthetic interrupt controller model specific registers for 232 * nested hypervisor. 233 */ 234 #define HV_REGISTER_NESTED_SCONTROL 0x40001080 235 #define HV_REGISTER_NESTED_SVERSION 0x40001081 236 #define HV_REGISTER_NESTED_SIEFP 0x40001082 237 #define HV_REGISTER_NESTED_SIMP 0x40001083 238 #define HV_REGISTER_NESTED_EOM 0x40001084 239 #define HV_REGISTER_NESTED_SINT0 0x40001090 240 241 /* 242 * Synthetic Timer MSRs. Four timers per vcpu. 243 */ 244 #define HV_REGISTER_STIMER0_CONFIG 0x400000B0 245 #define HV_REGISTER_STIMER0_COUNT 0x400000B1 246 #define HV_REGISTER_STIMER1_CONFIG 0x400000B2 247 #define HV_REGISTER_STIMER1_COUNT 0x400000B3 248 #define HV_REGISTER_STIMER2_CONFIG 0x400000B4 249 #define HV_REGISTER_STIMER2_COUNT 0x400000B5 250 #define HV_REGISTER_STIMER3_CONFIG 0x400000B6 251 #define HV_REGISTER_STIMER3_COUNT 0x400000B7 252 253 /* Hyper-V guest idle MSR */ 254 #define HV_X64_MSR_GUEST_IDLE 0x400000F0 255 256 /* Hyper-V guest crash notification MSR's */ 257 #define HV_REGISTER_CRASH_P0 0x40000100 258 #define HV_REGISTER_CRASH_P1 0x40000101 259 #define HV_REGISTER_CRASH_P2 0x40000102 260 #define HV_REGISTER_CRASH_P3 0x40000103 261 #define HV_REGISTER_CRASH_P4 0x40000104 262 #define HV_REGISTER_CRASH_CTL 0x40000105 263 264 /* TSC emulation after migration */ 265 #define HV_X64_MSR_REENLIGHTENMENT_CONTROL 0x40000106 266 #define HV_X64_MSR_TSC_EMULATION_CONTROL 0x40000107 267 #define HV_X64_MSR_TSC_EMULATION_STATUS 0x40000108 268 269 /* TSC invariant control */ 270 #define HV_X64_MSR_TSC_INVARIANT_CONTROL 0x40000118 271 272 /* HV_X64_MSR_TSC_INVARIANT_CONTROL bits */ 273 #define HV_EXPOSE_INVARIANT_TSC BIT_ULL(0) 274 275 /* Register name aliases for temporary compatibility */ 276 #define HV_X64_MSR_STIMER0_COUNT HV_REGISTER_STIMER0_COUNT 277 #define HV_X64_MSR_STIMER0_CONFIG HV_REGISTER_STIMER0_CONFIG 278 #define HV_X64_MSR_STIMER1_COUNT HV_REGISTER_STIMER1_COUNT 279 #define HV_X64_MSR_STIMER1_CONFIG HV_REGISTER_STIMER1_CONFIG 280 #define HV_X64_MSR_STIMER2_COUNT HV_REGISTER_STIMER2_COUNT 281 #define HV_X64_MSR_STIMER2_CONFIG HV_REGISTER_STIMER2_CONFIG 282 #define HV_X64_MSR_STIMER3_COUNT HV_REGISTER_STIMER3_COUNT 283 #define HV_X64_MSR_STIMER3_CONFIG HV_REGISTER_STIMER3_CONFIG 284 #define HV_X64_MSR_SCONTROL HV_REGISTER_SCONTROL 285 #define HV_X64_MSR_SVERSION HV_REGISTER_SVERSION 286 #define HV_X64_MSR_SIMP HV_REGISTER_SIMP 287 #define HV_X64_MSR_SIEFP HV_REGISTER_SIEFP 288 #define HV_X64_MSR_VP_INDEX HV_REGISTER_VP_INDEX 289 #define HV_X64_MSR_EOM HV_REGISTER_EOM 290 #define HV_X64_MSR_SINT0 HV_REGISTER_SINT0 291 #define HV_X64_MSR_SINT15 HV_REGISTER_SINT15 292 #define HV_X64_MSR_CRASH_P0 HV_REGISTER_CRASH_P0 293 #define HV_X64_MSR_CRASH_P1 HV_REGISTER_CRASH_P1 294 #define HV_X64_MSR_CRASH_P2 HV_REGISTER_CRASH_P2 295 #define HV_X64_MSR_CRASH_P3 HV_REGISTER_CRASH_P3 296 #define HV_X64_MSR_CRASH_P4 HV_REGISTER_CRASH_P4 297 #define HV_X64_MSR_CRASH_CTL HV_REGISTER_CRASH_CTL 298 #define HV_X64_MSR_TIME_REF_COUNT HV_REGISTER_TIME_REF_COUNT 299 #define HV_X64_MSR_REFERENCE_TSC HV_REGISTER_REFERENCE_TSC 300 301 /* Hyper-V memory host visibility */ 302 enum hv_mem_host_visibility { 303 VMBUS_PAGE_NOT_VISIBLE = 0, 304 VMBUS_PAGE_VISIBLE_READ_ONLY = 1, 305 VMBUS_PAGE_VISIBLE_READ_WRITE = 3 306 }; 307 308 /* HvCallModifySparseGpaPageHostVisibility hypercall */ 309 #define HV_MAX_MODIFY_GPA_REP_COUNT ((PAGE_SIZE / sizeof(u64)) - 2) 310 struct hv_gpa_range_for_visibility { 311 u64 partition_id; 312 u32 host_visibility:2; 313 u32 reserved0:30; 314 u32 reserved1; 315 u64 gpa_page_list[HV_MAX_MODIFY_GPA_REP_COUNT]; 316 } __packed; 317 318 /* 319 * Declare the MSR used to setup pages used to communicate with the hypervisor. 320 */ 321 union hv_x64_msr_hypercall_contents { 322 u64 as_uint64; 323 struct { 324 u64 enable:1; 325 u64 reserved:11; 326 u64 guest_physical_address:52; 327 } __packed; 328 }; 329 330 union hv_vp_assist_msr_contents { 331 u64 as_uint64; 332 struct { 333 u64 enable:1; 334 u64 reserved:11; 335 u64 pfn:52; 336 } __packed; 337 }; 338 339 struct hv_reenlightenment_control { 340 __u64 vector:8; 341 __u64 reserved1:8; 342 __u64 enabled:1; 343 __u64 reserved2:15; 344 __u64 target_vp:32; 345 } __packed; 346 347 struct hv_tsc_emulation_control { 348 __u64 enabled:1; 349 __u64 reserved:63; 350 } __packed; 351 352 struct hv_tsc_emulation_status { 353 __u64 inprogress:1; 354 __u64 reserved:63; 355 } __packed; 356 357 #define HV_X64_MSR_HYPERCALL_ENABLE 0x00000001 358 #define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT 12 359 #define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_MASK \ 360 (~((1ull << HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT) - 1)) 361 362 #define HV_X64_MSR_CRASH_PARAMS \ 363 (1 + (HV_X64_MSR_CRASH_P4 - HV_X64_MSR_CRASH_P0)) 364 365 #define HV_IPI_LOW_VECTOR 0x10 366 #define HV_IPI_HIGH_VECTOR 0xff 367 368 #define HV_X64_MSR_VP_ASSIST_PAGE_ENABLE 0x00000001 369 #define HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_SHIFT 12 370 #define HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_MASK \ 371 (~((1ull << HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_SHIFT) - 1)) 372 373 /* Hyper-V Enlightened VMCS version mask in nested features CPUID */ 374 #define HV_X64_ENLIGHTENED_VMCS_VERSION 0xff 375 376 #define HV_X64_MSR_TSC_REFERENCE_ENABLE 0x00000001 377 #define HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT 12 378 379 /* Number of XMM registers used in hypercall input/output */ 380 #define HV_HYPERCALL_MAX_XMM_REGISTERS 6 381 382 struct hv_nested_enlightenments_control { 383 struct { 384 __u32 directhypercall:1; 385 __u32 reserved:31; 386 } features; 387 struct { 388 __u32 inter_partition_comm:1; 389 __u32 reserved:31; 390 } hypercallControls; 391 } __packed; 392 393 /* Define virtual processor assist page structure. */ 394 struct hv_vp_assist_page { 395 __u32 apic_assist; 396 __u32 reserved1; 397 __u32 vtl_entry_reason; 398 __u32 vtl_reserved; 399 __u64 vtl_ret_x64rax; 400 __u64 vtl_ret_x64rcx; 401 struct hv_nested_enlightenments_control nested_control; 402 __u8 enlighten_vmentry; 403 __u8 reserved2[7]; 404 __u64 current_nested_vmcs; 405 __u8 synthetic_time_unhalted_timer_expired; 406 __u8 reserved3[7]; 407 __u8 virtualization_fault_information[40]; 408 __u8 reserved4[8]; 409 __u8 intercept_message[256]; 410 __u8 vtl_ret_actions[256]; 411 } __packed; 412 413 struct hv_enlightened_vmcs { 414 u32 revision_id; 415 u32 abort; 416 417 u16 host_es_selector; 418 u16 host_cs_selector; 419 u16 host_ss_selector; 420 u16 host_ds_selector; 421 u16 host_fs_selector; 422 u16 host_gs_selector; 423 u16 host_tr_selector; 424 425 u16 padding16_1; 426 427 u64 host_ia32_pat; 428 u64 host_ia32_efer; 429 430 u64 host_cr0; 431 u64 host_cr3; 432 u64 host_cr4; 433 434 u64 host_ia32_sysenter_esp; 435 u64 host_ia32_sysenter_eip; 436 u64 host_rip; 437 u32 host_ia32_sysenter_cs; 438 439 u32 pin_based_vm_exec_control; 440 u32 vm_exit_controls; 441 u32 secondary_vm_exec_control; 442 443 u64 io_bitmap_a; 444 u64 io_bitmap_b; 445 u64 msr_bitmap; 446 447 u16 guest_es_selector; 448 u16 guest_cs_selector; 449 u16 guest_ss_selector; 450 u16 guest_ds_selector; 451 u16 guest_fs_selector; 452 u16 guest_gs_selector; 453 u16 guest_ldtr_selector; 454 u16 guest_tr_selector; 455 456 u32 guest_es_limit; 457 u32 guest_cs_limit; 458 u32 guest_ss_limit; 459 u32 guest_ds_limit; 460 u32 guest_fs_limit; 461 u32 guest_gs_limit; 462 u32 guest_ldtr_limit; 463 u32 guest_tr_limit; 464 u32 guest_gdtr_limit; 465 u32 guest_idtr_limit; 466 467 u32 guest_es_ar_bytes; 468 u32 guest_cs_ar_bytes; 469 u32 guest_ss_ar_bytes; 470 u32 guest_ds_ar_bytes; 471 u32 guest_fs_ar_bytes; 472 u32 guest_gs_ar_bytes; 473 u32 guest_ldtr_ar_bytes; 474 u32 guest_tr_ar_bytes; 475 476 u64 guest_es_base; 477 u64 guest_cs_base; 478 u64 guest_ss_base; 479 u64 guest_ds_base; 480 u64 guest_fs_base; 481 u64 guest_gs_base; 482 u64 guest_ldtr_base; 483 u64 guest_tr_base; 484 u64 guest_gdtr_base; 485 u64 guest_idtr_base; 486 487 u64 padding64_1[3]; 488 489 u64 vm_exit_msr_store_addr; 490 u64 vm_exit_msr_load_addr; 491 u64 vm_entry_msr_load_addr; 492 493 u64 cr3_target_value0; 494 u64 cr3_target_value1; 495 u64 cr3_target_value2; 496 u64 cr3_target_value3; 497 498 u32 page_fault_error_code_mask; 499 u32 page_fault_error_code_match; 500 501 u32 cr3_target_count; 502 u32 vm_exit_msr_store_count; 503 u32 vm_exit_msr_load_count; 504 u32 vm_entry_msr_load_count; 505 506 u64 tsc_offset; 507 u64 virtual_apic_page_addr; 508 u64 vmcs_link_pointer; 509 510 u64 guest_ia32_debugctl; 511 u64 guest_ia32_pat; 512 u64 guest_ia32_efer; 513 514 u64 guest_pdptr0; 515 u64 guest_pdptr1; 516 u64 guest_pdptr2; 517 u64 guest_pdptr3; 518 519 u64 guest_pending_dbg_exceptions; 520 u64 guest_sysenter_esp; 521 u64 guest_sysenter_eip; 522 523 u32 guest_activity_state; 524 u32 guest_sysenter_cs; 525 526 u64 cr0_guest_host_mask; 527 u64 cr4_guest_host_mask; 528 u64 cr0_read_shadow; 529 u64 cr4_read_shadow; 530 u64 guest_cr0; 531 u64 guest_cr3; 532 u64 guest_cr4; 533 u64 guest_dr7; 534 535 u64 host_fs_base; 536 u64 host_gs_base; 537 u64 host_tr_base; 538 u64 host_gdtr_base; 539 u64 host_idtr_base; 540 u64 host_rsp; 541 542 u64 ept_pointer; 543 544 u16 virtual_processor_id; 545 u16 padding16_2[3]; 546 547 u64 padding64_2[5]; 548 u64 guest_physical_address; 549 550 u32 vm_instruction_error; 551 u32 vm_exit_reason; 552 u32 vm_exit_intr_info; 553 u32 vm_exit_intr_error_code; 554 u32 idt_vectoring_info_field; 555 u32 idt_vectoring_error_code; 556 u32 vm_exit_instruction_len; 557 u32 vmx_instruction_info; 558 559 u64 exit_qualification; 560 u64 exit_io_instruction_ecx; 561 u64 exit_io_instruction_esi; 562 u64 exit_io_instruction_edi; 563 u64 exit_io_instruction_eip; 564 565 u64 guest_linear_address; 566 u64 guest_rsp; 567 u64 guest_rflags; 568 569 u32 guest_interruptibility_info; 570 u32 cpu_based_vm_exec_control; 571 u32 exception_bitmap; 572 u32 vm_entry_controls; 573 u32 vm_entry_intr_info_field; 574 u32 vm_entry_exception_error_code; 575 u32 vm_entry_instruction_len; 576 u32 tpr_threshold; 577 578 u64 guest_rip; 579 580 u32 hv_clean_fields; 581 u32 padding32_1; 582 u32 hv_synthetic_controls; 583 struct { 584 u32 nested_flush_hypercall:1; 585 u32 msr_bitmap:1; 586 u32 reserved:30; 587 } __packed hv_enlightenments_control; 588 u32 hv_vp_id; 589 u32 padding32_2; 590 u64 hv_vm_id; 591 u64 partition_assist_page; 592 u64 padding64_4[4]; 593 u64 guest_bndcfgs; 594 u64 guest_ia32_perf_global_ctrl; 595 u64 guest_ia32_s_cet; 596 u64 guest_ssp; 597 u64 guest_ia32_int_ssp_table_addr; 598 u64 guest_ia32_lbr_ctl; 599 u64 padding64_5[2]; 600 u64 xss_exit_bitmap; 601 u64 encls_exiting_bitmap; 602 u64 host_ia32_perf_global_ctrl; 603 u64 tsc_multiplier; 604 u64 host_ia32_s_cet; 605 u64 host_ssp; 606 u64 host_ia32_int_ssp_table_addr; 607 u64 padding64_6; 608 } __packed; 609 610 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_NONE 0 611 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_IO_BITMAP BIT(0) 612 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_MSR_BITMAP BIT(1) 613 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_GRP2 BIT(2) 614 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_GRP1 BIT(3) 615 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_PROC BIT(4) 616 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_EVENT BIT(5) 617 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_ENTRY BIT(6) 618 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_EXCPN BIT(7) 619 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CRDR BIT(8) 620 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_XLAT BIT(9) 621 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_BASIC BIT(10) 622 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_GRP1 BIT(11) 623 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_GRP2 BIT(12) 624 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_HOST_POINTER BIT(13) 625 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_HOST_GRP1 BIT(14) 626 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_ENLIGHTENMENTSCONTROL BIT(15) 627 628 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL 0xFFFF 629 630 /* 631 * Note, Hyper-V isn't actually stealing bit 28 from Intel, just abusing it by 632 * pairing it with architecturally impossible exit reasons. Bit 28 is set only 633 * on SMI exits to a SMI transfer monitor (STM) and if and only if a MTF VM-Exit 634 * is pending. I.e. it will never be set by hardware for non-SMI exits (there 635 * are only three), nor will it ever be set unless the VMM is an STM. 636 */ 637 #define HV_VMX_SYNTHETIC_EXIT_REASON_TRAP_AFTER_FLUSH 0x10000031 638 639 /* 640 * Hyper-V uses the software reserved 32 bytes in VMCB control area to expose 641 * SVM enlightenments to guests. 642 */ 643 struct hv_vmcb_enlightenments { 644 struct __packed hv_enlightenments_control { 645 u32 nested_flush_hypercall:1; 646 u32 msr_bitmap:1; 647 u32 enlightened_npt_tlb: 1; 648 u32 reserved:29; 649 } __packed hv_enlightenments_control; 650 u32 hv_vp_id; 651 u64 hv_vm_id; 652 u64 partition_assist_page; 653 u64 reserved; 654 } __packed; 655 656 /* 657 * Hyper-V uses the software reserved clean bit in VMCB. 658 */ 659 #define HV_VMCB_NESTED_ENLIGHTENMENTS 31 660 661 /* Synthetic VM-Exit */ 662 #define HV_SVM_EXITCODE_ENL 0xf0000000 663 #define HV_SVM_ENL_EXITCODE_TRAP_AFTER_FLUSH (1) 664 665 struct hv_partition_assist_pg { 666 u32 tlb_lock_count; 667 }; 668 669 enum hv_interrupt_type { 670 HV_X64_INTERRUPT_TYPE_FIXED = 0x0000, 671 HV_X64_INTERRUPT_TYPE_LOWESTPRIORITY = 0x0001, 672 HV_X64_INTERRUPT_TYPE_SMI = 0x0002, 673 HV_X64_INTERRUPT_TYPE_REMOTEREAD = 0x0003, 674 HV_X64_INTERRUPT_TYPE_NMI = 0x0004, 675 HV_X64_INTERRUPT_TYPE_INIT = 0x0005, 676 HV_X64_INTERRUPT_TYPE_SIPI = 0x0006, 677 HV_X64_INTERRUPT_TYPE_EXTINT = 0x0007, 678 HV_X64_INTERRUPT_TYPE_LOCALINT0 = 0x0008, 679 HV_X64_INTERRUPT_TYPE_LOCALINT1 = 0x0009, 680 HV_X64_INTERRUPT_TYPE_MAXIMUM = 0x000A, 681 }; 682 683 union hv_msi_address_register { 684 u32 as_uint32; 685 struct { 686 u32 reserved1:2; 687 u32 destination_mode:1; 688 u32 redirection_hint:1; 689 u32 reserved2:8; 690 u32 destination_id:8; 691 u32 msi_base:12; 692 }; 693 } __packed; 694 695 union hv_msi_data_register { 696 u32 as_uint32; 697 struct { 698 u32 vector:8; 699 u32 delivery_mode:3; 700 u32 reserved1:3; 701 u32 level_assert:1; 702 u32 trigger_mode:1; 703 u32 reserved2:16; 704 }; 705 } __packed; 706 707 /* HvRetargetDeviceInterrupt hypercall */ 708 union hv_msi_entry { 709 u64 as_uint64; 710 struct { 711 union hv_msi_address_register address; 712 union hv_msi_data_register data; 713 } __packed; 714 }; 715 716 #include <asm-generic/hyperv-tlfs.h> 717 718 #endif 719