1 /* SPDX-License-Identifier: GPL-2.0 */ 2 3 /* 4 * This file contains definitions from Hyper-V Hypervisor Top-Level Functional 5 * Specification (TLFS): 6 * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs 7 */ 8 9 #ifndef _ASM_X86_HYPERV_TLFS_H 10 #define _ASM_X86_HYPERV_TLFS_H 11 12 #include <linux/types.h> 13 #include <asm/page.h> 14 /* 15 * The below CPUID leaves are present if VersionAndFeatures.HypervisorPresent 16 * is set by CPUID(HvCpuIdFunctionVersionAndFeatures). 17 */ 18 #define HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS 0x40000000 19 #define HYPERV_CPUID_INTERFACE 0x40000001 20 #define HYPERV_CPUID_VERSION 0x40000002 21 #define HYPERV_CPUID_FEATURES 0x40000003 22 #define HYPERV_CPUID_ENLIGHTMENT_INFO 0x40000004 23 #define HYPERV_CPUID_IMPLEMENT_LIMITS 0x40000005 24 #define HYPERV_CPUID_CPU_MANAGEMENT_FEATURES 0x40000007 25 #define HYPERV_CPUID_NESTED_FEATURES 0x4000000A 26 #define HYPERV_CPUID_ISOLATION_CONFIG 0x4000000C 27 28 #define HYPERV_CPUID_VIRT_STACK_INTERFACE 0x40000081 29 #define HYPERV_VS_INTERFACE_EAX_SIGNATURE 0x31235356 /* "VS#1" */ 30 31 #define HYPERV_CPUID_VIRT_STACK_PROPERTIES 0x40000082 32 /* Support for the extended IOAPIC RTE format */ 33 #define HYPERV_VS_PROPERTIES_EAX_EXTENDED_IOAPIC_RTE BIT(2) 34 35 #define HYPERV_HYPERVISOR_PRESENT_BIT 0x80000000 36 #define HYPERV_CPUID_MIN 0x40000005 37 #define HYPERV_CPUID_MAX 0x4000ffff 38 39 /* 40 * Group D Features. The bit assignments are custom to each architecture. 41 * On x86/x64 these are HYPERV_CPUID_FEATURES.EDX bits. 42 */ 43 /* The MWAIT instruction is available (per section MONITOR / MWAIT) */ 44 #define HV_X64_MWAIT_AVAILABLE BIT(0) 45 /* Guest debugging support is available */ 46 #define HV_X64_GUEST_DEBUGGING_AVAILABLE BIT(1) 47 /* Performance Monitor support is available*/ 48 #define HV_X64_PERF_MONITOR_AVAILABLE BIT(2) 49 /* Support for physical CPU dynamic partitioning events is available*/ 50 #define HV_X64_CPU_DYNAMIC_PARTITIONING_AVAILABLE BIT(3) 51 /* 52 * Support for passing hypercall input parameter block via XMM 53 * registers is available 54 */ 55 #define HV_X64_HYPERCALL_PARAMS_XMM_AVAILABLE BIT(4) 56 /* Support for a virtual guest idle state is available */ 57 #define HV_X64_GUEST_IDLE_STATE_AVAILABLE BIT(5) 58 /* Frequency MSRs available */ 59 #define HV_FEATURE_FREQUENCY_MSRS_AVAILABLE BIT(8) 60 /* Crash MSR available */ 61 #define HV_FEATURE_GUEST_CRASH_MSR_AVAILABLE BIT(10) 62 /* Support for debug MSRs available */ 63 #define HV_FEATURE_DEBUG_MSRS_AVAILABLE BIT(11) 64 /* stimer Direct Mode is available */ 65 #define HV_STIMER_DIRECT_MODE_AVAILABLE BIT(19) 66 67 /* 68 * Implementation recommendations. Indicates which behaviors the hypervisor 69 * recommends the OS implement for optimal performance. 70 * These are HYPERV_CPUID_ENLIGHTMENT_INFO.EAX bits. 71 */ 72 /* 73 * Recommend using hypercall for address space switches rather 74 * than MOV to CR3 instruction 75 */ 76 #define HV_X64_AS_SWITCH_RECOMMENDED BIT(0) 77 /* Recommend using hypercall for local TLB flushes rather 78 * than INVLPG or MOV to CR3 instructions */ 79 #define HV_X64_LOCAL_TLB_FLUSH_RECOMMENDED BIT(1) 80 /* 81 * Recommend using hypercall for remote TLB flushes rather 82 * than inter-processor interrupts 83 */ 84 #define HV_X64_REMOTE_TLB_FLUSH_RECOMMENDED BIT(2) 85 /* 86 * Recommend using MSRs for accessing APIC registers 87 * EOI, ICR and TPR rather than their memory-mapped counterparts 88 */ 89 #define HV_X64_APIC_ACCESS_RECOMMENDED BIT(3) 90 /* Recommend using the hypervisor-provided MSR to initiate a system RESET */ 91 #define HV_X64_SYSTEM_RESET_RECOMMENDED BIT(4) 92 /* 93 * Recommend using relaxed timing for this partition. If used, 94 * the VM should disable any watchdog timeouts that rely on the 95 * timely delivery of external interrupts 96 */ 97 #define HV_X64_RELAXED_TIMING_RECOMMENDED BIT(5) 98 99 /* 100 * Recommend not using Auto End-Of-Interrupt feature 101 */ 102 #define HV_DEPRECATING_AEOI_RECOMMENDED BIT(9) 103 104 /* 105 * Recommend using cluster IPI hypercalls. 106 */ 107 #define HV_X64_CLUSTER_IPI_RECOMMENDED BIT(10) 108 109 /* Recommend using the newer ExProcessorMasks interface */ 110 #define HV_X64_EX_PROCESSOR_MASKS_RECOMMENDED BIT(11) 111 112 /* Recommend using enlightened VMCS */ 113 #define HV_X64_ENLIGHTENED_VMCS_RECOMMENDED BIT(14) 114 115 /* 116 * CPU management features identification. 117 * These are HYPERV_CPUID_CPU_MANAGEMENT_FEATURES.EAX bits. 118 */ 119 #define HV_X64_START_LOGICAL_PROCESSOR BIT(0) 120 #define HV_X64_CREATE_ROOT_VIRTUAL_PROCESSOR BIT(1) 121 #define HV_X64_PERFORMANCE_COUNTER_SYNC BIT(2) 122 #define HV_X64_RESERVED_IDENTITY_BIT BIT(31) 123 124 /* 125 * Virtual processor will never share a physical core with another virtual 126 * processor, except for virtual processors that are reported as sibling SMT 127 * threads. 128 */ 129 #define HV_X64_NO_NONARCH_CORESHARING BIT(18) 130 131 /* Nested features. These are HYPERV_CPUID_NESTED_FEATURES.EAX bits. */ 132 #define HV_X64_NESTED_DIRECT_FLUSH BIT(17) 133 #define HV_X64_NESTED_GUEST_MAPPING_FLUSH BIT(18) 134 #define HV_X64_NESTED_MSR_BITMAP BIT(19) 135 136 /* HYPERV_CPUID_ISOLATION_CONFIG.EAX bits. */ 137 #define HV_PARAVISOR_PRESENT BIT(0) 138 139 /* HYPERV_CPUID_ISOLATION_CONFIG.EBX bits. */ 140 #define HV_ISOLATION_TYPE GENMASK(3, 0) 141 #define HV_SHARED_GPA_BOUNDARY_ACTIVE BIT(5) 142 #define HV_SHARED_GPA_BOUNDARY_BITS GENMASK(11, 6) 143 144 enum hv_isolation_type { 145 HV_ISOLATION_TYPE_NONE = 0, 146 HV_ISOLATION_TYPE_VBS = 1, 147 HV_ISOLATION_TYPE_SNP = 2 148 }; 149 150 /* Hyper-V specific model specific registers (MSRs) */ 151 152 /* MSR used to identify the guest OS. */ 153 #define HV_X64_MSR_GUEST_OS_ID 0x40000000 154 155 /* MSR used to setup pages used to communicate with the hypervisor. */ 156 #define HV_X64_MSR_HYPERCALL 0x40000001 157 158 /* MSR used to provide vcpu index */ 159 #define HV_REGISTER_VP_INDEX 0x40000002 160 161 /* MSR used to reset the guest OS. */ 162 #define HV_X64_MSR_RESET 0x40000003 163 164 /* MSR used to provide vcpu runtime in 100ns units */ 165 #define HV_X64_MSR_VP_RUNTIME 0x40000010 166 167 /* MSR used to read the per-partition time reference counter */ 168 #define HV_REGISTER_TIME_REF_COUNT 0x40000020 169 170 /* A partition's reference time stamp counter (TSC) page */ 171 #define HV_REGISTER_REFERENCE_TSC 0x40000021 172 173 /* MSR used to retrieve the TSC frequency */ 174 #define HV_X64_MSR_TSC_FREQUENCY 0x40000022 175 176 /* MSR used to retrieve the local APIC timer frequency */ 177 #define HV_X64_MSR_APIC_FREQUENCY 0x40000023 178 179 /* Define the virtual APIC registers */ 180 #define HV_X64_MSR_EOI 0x40000070 181 #define HV_X64_MSR_ICR 0x40000071 182 #define HV_X64_MSR_TPR 0x40000072 183 #define HV_X64_MSR_VP_ASSIST_PAGE 0x40000073 184 185 /* Define synthetic interrupt controller model specific registers. */ 186 #define HV_REGISTER_SCONTROL 0x40000080 187 #define HV_REGISTER_SVERSION 0x40000081 188 #define HV_REGISTER_SIEFP 0x40000082 189 #define HV_REGISTER_SIMP 0x40000083 190 #define HV_REGISTER_EOM 0x40000084 191 #define HV_REGISTER_SINT0 0x40000090 192 #define HV_REGISTER_SINT1 0x40000091 193 #define HV_REGISTER_SINT2 0x40000092 194 #define HV_REGISTER_SINT3 0x40000093 195 #define HV_REGISTER_SINT4 0x40000094 196 #define HV_REGISTER_SINT5 0x40000095 197 #define HV_REGISTER_SINT6 0x40000096 198 #define HV_REGISTER_SINT7 0x40000097 199 #define HV_REGISTER_SINT8 0x40000098 200 #define HV_REGISTER_SINT9 0x40000099 201 #define HV_REGISTER_SINT10 0x4000009A 202 #define HV_REGISTER_SINT11 0x4000009B 203 #define HV_REGISTER_SINT12 0x4000009C 204 #define HV_REGISTER_SINT13 0x4000009D 205 #define HV_REGISTER_SINT14 0x4000009E 206 #define HV_REGISTER_SINT15 0x4000009F 207 208 /* 209 * Synthetic Timer MSRs. Four timers per vcpu. 210 */ 211 #define HV_REGISTER_STIMER0_CONFIG 0x400000B0 212 #define HV_REGISTER_STIMER0_COUNT 0x400000B1 213 #define HV_REGISTER_STIMER1_CONFIG 0x400000B2 214 #define HV_REGISTER_STIMER1_COUNT 0x400000B3 215 #define HV_REGISTER_STIMER2_CONFIG 0x400000B4 216 #define HV_REGISTER_STIMER2_COUNT 0x400000B5 217 #define HV_REGISTER_STIMER3_CONFIG 0x400000B6 218 #define HV_REGISTER_STIMER3_COUNT 0x400000B7 219 220 /* Hyper-V guest idle MSR */ 221 #define HV_X64_MSR_GUEST_IDLE 0x400000F0 222 223 /* Hyper-V guest crash notification MSR's */ 224 #define HV_REGISTER_CRASH_P0 0x40000100 225 #define HV_REGISTER_CRASH_P1 0x40000101 226 #define HV_REGISTER_CRASH_P2 0x40000102 227 #define HV_REGISTER_CRASH_P3 0x40000103 228 #define HV_REGISTER_CRASH_P4 0x40000104 229 #define HV_REGISTER_CRASH_CTL 0x40000105 230 231 /* TSC emulation after migration */ 232 #define HV_X64_MSR_REENLIGHTENMENT_CONTROL 0x40000106 233 #define HV_X64_MSR_TSC_EMULATION_CONTROL 0x40000107 234 #define HV_X64_MSR_TSC_EMULATION_STATUS 0x40000108 235 236 /* TSC invariant control */ 237 #define HV_X64_MSR_TSC_INVARIANT_CONTROL 0x40000118 238 239 /* Register name aliases for temporary compatibility */ 240 #define HV_X64_MSR_STIMER0_COUNT HV_REGISTER_STIMER0_COUNT 241 #define HV_X64_MSR_STIMER0_CONFIG HV_REGISTER_STIMER0_CONFIG 242 #define HV_X64_MSR_STIMER1_COUNT HV_REGISTER_STIMER1_COUNT 243 #define HV_X64_MSR_STIMER1_CONFIG HV_REGISTER_STIMER1_CONFIG 244 #define HV_X64_MSR_STIMER2_COUNT HV_REGISTER_STIMER2_COUNT 245 #define HV_X64_MSR_STIMER2_CONFIG HV_REGISTER_STIMER2_CONFIG 246 #define HV_X64_MSR_STIMER3_COUNT HV_REGISTER_STIMER3_COUNT 247 #define HV_X64_MSR_STIMER3_CONFIG HV_REGISTER_STIMER3_CONFIG 248 #define HV_X64_MSR_SCONTROL HV_REGISTER_SCONTROL 249 #define HV_X64_MSR_SVERSION HV_REGISTER_SVERSION 250 #define HV_X64_MSR_SIMP HV_REGISTER_SIMP 251 #define HV_X64_MSR_SIEFP HV_REGISTER_SIEFP 252 #define HV_X64_MSR_VP_INDEX HV_REGISTER_VP_INDEX 253 #define HV_X64_MSR_EOM HV_REGISTER_EOM 254 #define HV_X64_MSR_SINT0 HV_REGISTER_SINT0 255 #define HV_X64_MSR_SINT15 HV_REGISTER_SINT15 256 #define HV_X64_MSR_CRASH_P0 HV_REGISTER_CRASH_P0 257 #define HV_X64_MSR_CRASH_P1 HV_REGISTER_CRASH_P1 258 #define HV_X64_MSR_CRASH_P2 HV_REGISTER_CRASH_P2 259 #define HV_X64_MSR_CRASH_P3 HV_REGISTER_CRASH_P3 260 #define HV_X64_MSR_CRASH_P4 HV_REGISTER_CRASH_P4 261 #define HV_X64_MSR_CRASH_CTL HV_REGISTER_CRASH_CTL 262 #define HV_X64_MSR_TIME_REF_COUNT HV_REGISTER_TIME_REF_COUNT 263 #define HV_X64_MSR_REFERENCE_TSC HV_REGISTER_REFERENCE_TSC 264 265 /* 266 * Declare the MSR used to setup pages used to communicate with the hypervisor. 267 */ 268 union hv_x64_msr_hypercall_contents { 269 u64 as_uint64; 270 struct { 271 u64 enable:1; 272 u64 reserved:11; 273 u64 guest_physical_address:52; 274 } __packed; 275 }; 276 277 struct hv_reenlightenment_control { 278 __u64 vector:8; 279 __u64 reserved1:8; 280 __u64 enabled:1; 281 __u64 reserved2:15; 282 __u64 target_vp:32; 283 } __packed; 284 285 struct hv_tsc_emulation_control { 286 __u64 enabled:1; 287 __u64 reserved:63; 288 } __packed; 289 290 struct hv_tsc_emulation_status { 291 __u64 inprogress:1; 292 __u64 reserved:63; 293 } __packed; 294 295 #define HV_X64_MSR_HYPERCALL_ENABLE 0x00000001 296 #define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT 12 297 #define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_MASK \ 298 (~((1ull << HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT) - 1)) 299 300 #define HV_X64_MSR_CRASH_PARAMS \ 301 (1 + (HV_X64_MSR_CRASH_P4 - HV_X64_MSR_CRASH_P0)) 302 303 #define HV_IPI_LOW_VECTOR 0x10 304 #define HV_IPI_HIGH_VECTOR 0xff 305 306 #define HV_X64_MSR_VP_ASSIST_PAGE_ENABLE 0x00000001 307 #define HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_SHIFT 12 308 #define HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_MASK \ 309 (~((1ull << HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_SHIFT) - 1)) 310 311 /* Hyper-V Enlightened VMCS version mask in nested features CPUID */ 312 #define HV_X64_ENLIGHTENED_VMCS_VERSION 0xff 313 314 #define HV_X64_MSR_TSC_REFERENCE_ENABLE 0x00000001 315 #define HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT 12 316 317 struct hv_nested_enlightenments_control { 318 struct { 319 __u32 directhypercall:1; 320 __u32 reserved:31; 321 } features; 322 struct { 323 __u32 reserved; 324 } hypercallControls; 325 } __packed; 326 327 /* Define virtual processor assist page structure. */ 328 struct hv_vp_assist_page { 329 __u32 apic_assist; 330 __u32 reserved1; 331 __u64 vtl_control[3]; 332 struct hv_nested_enlightenments_control nested_control; 333 __u8 enlighten_vmentry; 334 __u8 reserved2[7]; 335 __u64 current_nested_vmcs; 336 } __packed; 337 338 struct hv_enlightened_vmcs { 339 u32 revision_id; 340 u32 abort; 341 342 u16 host_es_selector; 343 u16 host_cs_selector; 344 u16 host_ss_selector; 345 u16 host_ds_selector; 346 u16 host_fs_selector; 347 u16 host_gs_selector; 348 u16 host_tr_selector; 349 350 u16 padding16_1; 351 352 u64 host_ia32_pat; 353 u64 host_ia32_efer; 354 355 u64 host_cr0; 356 u64 host_cr3; 357 u64 host_cr4; 358 359 u64 host_ia32_sysenter_esp; 360 u64 host_ia32_sysenter_eip; 361 u64 host_rip; 362 u32 host_ia32_sysenter_cs; 363 364 u32 pin_based_vm_exec_control; 365 u32 vm_exit_controls; 366 u32 secondary_vm_exec_control; 367 368 u64 io_bitmap_a; 369 u64 io_bitmap_b; 370 u64 msr_bitmap; 371 372 u16 guest_es_selector; 373 u16 guest_cs_selector; 374 u16 guest_ss_selector; 375 u16 guest_ds_selector; 376 u16 guest_fs_selector; 377 u16 guest_gs_selector; 378 u16 guest_ldtr_selector; 379 u16 guest_tr_selector; 380 381 u32 guest_es_limit; 382 u32 guest_cs_limit; 383 u32 guest_ss_limit; 384 u32 guest_ds_limit; 385 u32 guest_fs_limit; 386 u32 guest_gs_limit; 387 u32 guest_ldtr_limit; 388 u32 guest_tr_limit; 389 u32 guest_gdtr_limit; 390 u32 guest_idtr_limit; 391 392 u32 guest_es_ar_bytes; 393 u32 guest_cs_ar_bytes; 394 u32 guest_ss_ar_bytes; 395 u32 guest_ds_ar_bytes; 396 u32 guest_fs_ar_bytes; 397 u32 guest_gs_ar_bytes; 398 u32 guest_ldtr_ar_bytes; 399 u32 guest_tr_ar_bytes; 400 401 u64 guest_es_base; 402 u64 guest_cs_base; 403 u64 guest_ss_base; 404 u64 guest_ds_base; 405 u64 guest_fs_base; 406 u64 guest_gs_base; 407 u64 guest_ldtr_base; 408 u64 guest_tr_base; 409 u64 guest_gdtr_base; 410 u64 guest_idtr_base; 411 412 u64 padding64_1[3]; 413 414 u64 vm_exit_msr_store_addr; 415 u64 vm_exit_msr_load_addr; 416 u64 vm_entry_msr_load_addr; 417 418 u64 cr3_target_value0; 419 u64 cr3_target_value1; 420 u64 cr3_target_value2; 421 u64 cr3_target_value3; 422 423 u32 page_fault_error_code_mask; 424 u32 page_fault_error_code_match; 425 426 u32 cr3_target_count; 427 u32 vm_exit_msr_store_count; 428 u32 vm_exit_msr_load_count; 429 u32 vm_entry_msr_load_count; 430 431 u64 tsc_offset; 432 u64 virtual_apic_page_addr; 433 u64 vmcs_link_pointer; 434 435 u64 guest_ia32_debugctl; 436 u64 guest_ia32_pat; 437 u64 guest_ia32_efer; 438 439 u64 guest_pdptr0; 440 u64 guest_pdptr1; 441 u64 guest_pdptr2; 442 u64 guest_pdptr3; 443 444 u64 guest_pending_dbg_exceptions; 445 u64 guest_sysenter_esp; 446 u64 guest_sysenter_eip; 447 448 u32 guest_activity_state; 449 u32 guest_sysenter_cs; 450 451 u64 cr0_guest_host_mask; 452 u64 cr4_guest_host_mask; 453 u64 cr0_read_shadow; 454 u64 cr4_read_shadow; 455 u64 guest_cr0; 456 u64 guest_cr3; 457 u64 guest_cr4; 458 u64 guest_dr7; 459 460 u64 host_fs_base; 461 u64 host_gs_base; 462 u64 host_tr_base; 463 u64 host_gdtr_base; 464 u64 host_idtr_base; 465 u64 host_rsp; 466 467 u64 ept_pointer; 468 469 u16 virtual_processor_id; 470 u16 padding16_2[3]; 471 472 u64 padding64_2[5]; 473 u64 guest_physical_address; 474 475 u32 vm_instruction_error; 476 u32 vm_exit_reason; 477 u32 vm_exit_intr_info; 478 u32 vm_exit_intr_error_code; 479 u32 idt_vectoring_info_field; 480 u32 idt_vectoring_error_code; 481 u32 vm_exit_instruction_len; 482 u32 vmx_instruction_info; 483 484 u64 exit_qualification; 485 u64 exit_io_instruction_ecx; 486 u64 exit_io_instruction_esi; 487 u64 exit_io_instruction_edi; 488 u64 exit_io_instruction_eip; 489 490 u64 guest_linear_address; 491 u64 guest_rsp; 492 u64 guest_rflags; 493 494 u32 guest_interruptibility_info; 495 u32 cpu_based_vm_exec_control; 496 u32 exception_bitmap; 497 u32 vm_entry_controls; 498 u32 vm_entry_intr_info_field; 499 u32 vm_entry_exception_error_code; 500 u32 vm_entry_instruction_len; 501 u32 tpr_threshold; 502 503 u64 guest_rip; 504 505 u32 hv_clean_fields; 506 u32 hv_padding_32; 507 u32 hv_synthetic_controls; 508 struct { 509 u32 nested_flush_hypercall:1; 510 u32 msr_bitmap:1; 511 u32 reserved:30; 512 } __packed hv_enlightenments_control; 513 u32 hv_vp_id; 514 515 u64 hv_vm_id; 516 u64 partition_assist_page; 517 u64 padding64_4[4]; 518 u64 guest_bndcfgs; 519 u64 padding64_5[7]; 520 u64 xss_exit_bitmap; 521 u64 padding64_6[7]; 522 } __packed; 523 524 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_NONE 0 525 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_IO_BITMAP BIT(0) 526 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_MSR_BITMAP BIT(1) 527 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_GRP2 BIT(2) 528 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_GRP1 BIT(3) 529 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_PROC BIT(4) 530 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_EVENT BIT(5) 531 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_ENTRY BIT(6) 532 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_EXCPN BIT(7) 533 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CRDR BIT(8) 534 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_XLAT BIT(9) 535 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_BASIC BIT(10) 536 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_GRP1 BIT(11) 537 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_GRP2 BIT(12) 538 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_HOST_POINTER BIT(13) 539 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_HOST_GRP1 BIT(14) 540 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_ENLIGHTENMENTSCONTROL BIT(15) 541 542 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL 0xFFFF 543 544 struct hv_partition_assist_pg { 545 u32 tlb_lock_count; 546 }; 547 548 enum hv_interrupt_type { 549 HV_X64_INTERRUPT_TYPE_FIXED = 0x0000, 550 HV_X64_INTERRUPT_TYPE_LOWESTPRIORITY = 0x0001, 551 HV_X64_INTERRUPT_TYPE_SMI = 0x0002, 552 HV_X64_INTERRUPT_TYPE_REMOTEREAD = 0x0003, 553 HV_X64_INTERRUPT_TYPE_NMI = 0x0004, 554 HV_X64_INTERRUPT_TYPE_INIT = 0x0005, 555 HV_X64_INTERRUPT_TYPE_SIPI = 0x0006, 556 HV_X64_INTERRUPT_TYPE_EXTINT = 0x0007, 557 HV_X64_INTERRUPT_TYPE_LOCALINT0 = 0x0008, 558 HV_X64_INTERRUPT_TYPE_LOCALINT1 = 0x0009, 559 HV_X64_INTERRUPT_TYPE_MAXIMUM = 0x000A, 560 }; 561 562 #include <asm-generic/hyperv-tlfs.h> 563 564 #endif 565