1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ 2 3 /* 4 * This file contains definitions from Hyper-V Hypervisor Top-Level Functional 5 * Specification (TLFS): 6 * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs 7 */ 8 9 #ifndef _ASM_X86_HYPERV_TLFS_H 10 #define _ASM_X86_HYPERV_TLFS_H 11 12 #include <linux/types.h> 13 14 /* 15 * The below CPUID leaves are present if VersionAndFeatures.HypervisorPresent 16 * is set by CPUID(HvCpuIdFunctionVersionAndFeatures). 17 */ 18 #define HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS 0x40000000 19 #define HYPERV_CPUID_INTERFACE 0x40000001 20 #define HYPERV_CPUID_VERSION 0x40000002 21 #define HYPERV_CPUID_FEATURES 0x40000003 22 #define HYPERV_CPUID_ENLIGHTMENT_INFO 0x40000004 23 #define HYPERV_CPUID_IMPLEMENT_LIMITS 0x40000005 24 #define HYPERV_CPUID_NESTED_FEATURES 0x4000000A 25 26 #define HYPERV_HYPERVISOR_PRESENT_BIT 0x80000000 27 #define HYPERV_CPUID_MIN 0x40000005 28 #define HYPERV_CPUID_MAX 0x4000ffff 29 30 /* 31 * Feature identification. EAX indicates which features are available 32 * to the partition based upon the current partition privileges. 33 */ 34 35 /* VP Runtime (HV_X64_MSR_VP_RUNTIME) available */ 36 #define HV_X64_MSR_VP_RUNTIME_AVAILABLE (1 << 0) 37 /* Partition Reference Counter (HV_X64_MSR_TIME_REF_COUNT) available*/ 38 #define HV_X64_MSR_TIME_REF_COUNT_AVAILABLE (1 << 1) 39 /* Partition reference TSC MSR is available */ 40 #define HV_X64_MSR_REFERENCE_TSC_AVAILABLE (1 << 9) 41 42 /* A partition's reference time stamp counter (TSC) page */ 43 #define HV_X64_MSR_REFERENCE_TSC 0x40000021 44 45 /* 46 * There is a single feature flag that signifies if the partition has access 47 * to MSRs with local APIC and TSC frequencies. 48 */ 49 #define HV_X64_ACCESS_FREQUENCY_MSRS (1 << 11) 50 51 /* AccessReenlightenmentControls privilege */ 52 #define HV_X64_ACCESS_REENLIGHTENMENT BIT(13) 53 54 /* 55 * Basic SynIC MSRs (HV_X64_MSR_SCONTROL through HV_X64_MSR_EOM 56 * and HV_X64_MSR_SINT0 through HV_X64_MSR_SINT15) available 57 */ 58 #define HV_X64_MSR_SYNIC_AVAILABLE (1 << 2) 59 /* 60 * Synthetic Timer MSRs (HV_X64_MSR_STIMER0_CONFIG through 61 * HV_X64_MSR_STIMER3_COUNT) available 62 */ 63 #define HV_X64_MSR_SYNTIMER_AVAILABLE (1 << 3) 64 /* 65 * APIC access MSRs (HV_X64_MSR_EOI, HV_X64_MSR_ICR and HV_X64_MSR_TPR) 66 * are available 67 */ 68 #define HV_X64_MSR_APIC_ACCESS_AVAILABLE (1 << 4) 69 /* Hypercall MSRs (HV_X64_MSR_GUEST_OS_ID and HV_X64_MSR_HYPERCALL) available*/ 70 #define HV_X64_MSR_HYPERCALL_AVAILABLE (1 << 5) 71 /* Access virtual processor index MSR (HV_X64_MSR_VP_INDEX) available*/ 72 #define HV_X64_MSR_VP_INDEX_AVAILABLE (1 << 6) 73 /* Virtual system reset MSR (HV_X64_MSR_RESET) is available*/ 74 #define HV_X64_MSR_RESET_AVAILABLE (1 << 7) 75 /* 76 * Access statistics pages MSRs (HV_X64_MSR_STATS_PARTITION_RETAIL_PAGE, 77 * HV_X64_MSR_STATS_PARTITION_INTERNAL_PAGE, HV_X64_MSR_STATS_VP_RETAIL_PAGE, 78 * HV_X64_MSR_STATS_VP_INTERNAL_PAGE) available 79 */ 80 #define HV_X64_MSR_STAT_PAGES_AVAILABLE (1 << 8) 81 82 /* Frequency MSRs available */ 83 #define HV_FEATURE_FREQUENCY_MSRS_AVAILABLE (1 << 8) 84 85 /* Crash MSR available */ 86 #define HV_FEATURE_GUEST_CRASH_MSR_AVAILABLE (1 << 10) 87 88 /* stimer Direct Mode is available */ 89 #define HV_X64_STIMER_DIRECT_MODE_AVAILABLE (1 << 19) 90 91 /* 92 * Feature identification: EBX indicates which flags were specified at 93 * partition creation. The format is the same as the partition creation 94 * flag structure defined in section Partition Creation Flags. 95 */ 96 #define HV_X64_CREATE_PARTITIONS (1 << 0) 97 #define HV_X64_ACCESS_PARTITION_ID (1 << 1) 98 #define HV_X64_ACCESS_MEMORY_POOL (1 << 2) 99 #define HV_X64_ADJUST_MESSAGE_BUFFERS (1 << 3) 100 #define HV_X64_POST_MESSAGES (1 << 4) 101 #define HV_X64_SIGNAL_EVENTS (1 << 5) 102 #define HV_X64_CREATE_PORT (1 << 6) 103 #define HV_X64_CONNECT_PORT (1 << 7) 104 #define HV_X64_ACCESS_STATS (1 << 8) 105 #define HV_X64_DEBUGGING (1 << 11) 106 #define HV_X64_CPU_POWER_MANAGEMENT (1 << 12) 107 #define HV_X64_CONFIGURE_PROFILER (1 << 13) 108 109 /* 110 * Feature identification. EDX indicates which miscellaneous features 111 * are available to the partition. 112 */ 113 /* The MWAIT instruction is available (per section MONITOR / MWAIT) */ 114 #define HV_X64_MWAIT_AVAILABLE (1 << 0) 115 /* Guest debugging support is available */ 116 #define HV_X64_GUEST_DEBUGGING_AVAILABLE (1 << 1) 117 /* Performance Monitor support is available*/ 118 #define HV_X64_PERF_MONITOR_AVAILABLE (1 << 2) 119 /* Support for physical CPU dynamic partitioning events is available*/ 120 #define HV_X64_CPU_DYNAMIC_PARTITIONING_AVAILABLE (1 << 3) 121 /* 122 * Support for passing hypercall input parameter block via XMM 123 * registers is available 124 */ 125 #define HV_X64_HYPERCALL_PARAMS_XMM_AVAILABLE (1 << 4) 126 /* Support for a virtual guest idle state is available */ 127 #define HV_X64_GUEST_IDLE_STATE_AVAILABLE (1 << 5) 128 /* Guest crash data handler available */ 129 #define HV_X64_GUEST_CRASH_MSR_AVAILABLE (1 << 10) 130 131 /* 132 * Implementation recommendations. Indicates which behaviors the hypervisor 133 * recommends the OS implement for optimal performance. 134 */ 135 /* 136 * Recommend using hypercall for address space switches rather 137 * than MOV to CR3 instruction 138 */ 139 #define HV_X64_AS_SWITCH_RECOMMENDED (1 << 0) 140 /* Recommend using hypercall for local TLB flushes rather 141 * than INVLPG or MOV to CR3 instructions */ 142 #define HV_X64_LOCAL_TLB_FLUSH_RECOMMENDED (1 << 1) 143 /* 144 * Recommend using hypercall for remote TLB flushes rather 145 * than inter-processor interrupts 146 */ 147 #define HV_X64_REMOTE_TLB_FLUSH_RECOMMENDED (1 << 2) 148 /* 149 * Recommend using MSRs for accessing APIC registers 150 * EOI, ICR and TPR rather than their memory-mapped counterparts 151 */ 152 #define HV_X64_APIC_ACCESS_RECOMMENDED (1 << 3) 153 /* Recommend using the hypervisor-provided MSR to initiate a system RESET */ 154 #define HV_X64_SYSTEM_RESET_RECOMMENDED (1 << 4) 155 /* 156 * Recommend using relaxed timing for this partition. If used, 157 * the VM should disable any watchdog timeouts that rely on the 158 * timely delivery of external interrupts 159 */ 160 #define HV_X64_RELAXED_TIMING_RECOMMENDED (1 << 5) 161 162 /* 163 * Virtual APIC support 164 */ 165 #define HV_X64_DEPRECATING_AEOI_RECOMMENDED (1 << 9) 166 167 /* Recommend using the newer ExProcessorMasks interface */ 168 #define HV_X64_EX_PROCESSOR_MASKS_RECOMMENDED (1 << 11) 169 170 /* Recommend using enlightened VMCS */ 171 #define HV_X64_ENLIGHTENED_VMCS_RECOMMENDED (1 << 14) 172 173 /* 174 * Crash notification flag. 175 */ 176 #define HV_CRASH_CTL_CRASH_NOTIFY (1ULL << 63) 177 178 /* MSR used to identify the guest OS. */ 179 #define HV_X64_MSR_GUEST_OS_ID 0x40000000 180 181 /* MSR used to setup pages used to communicate with the hypervisor. */ 182 #define HV_X64_MSR_HYPERCALL 0x40000001 183 184 /* MSR used to provide vcpu index */ 185 #define HV_X64_MSR_VP_INDEX 0x40000002 186 187 /* MSR used to reset the guest OS. */ 188 #define HV_X64_MSR_RESET 0x40000003 189 190 /* MSR used to provide vcpu runtime in 100ns units */ 191 #define HV_X64_MSR_VP_RUNTIME 0x40000010 192 193 /* MSR used to read the per-partition time reference counter */ 194 #define HV_X64_MSR_TIME_REF_COUNT 0x40000020 195 196 /* MSR used to retrieve the TSC frequency */ 197 #define HV_X64_MSR_TSC_FREQUENCY 0x40000022 198 199 /* MSR used to retrieve the local APIC timer frequency */ 200 #define HV_X64_MSR_APIC_FREQUENCY 0x40000023 201 202 /* Define the virtual APIC registers */ 203 #define HV_X64_MSR_EOI 0x40000070 204 #define HV_X64_MSR_ICR 0x40000071 205 #define HV_X64_MSR_TPR 0x40000072 206 #define HV_X64_MSR_VP_ASSIST_PAGE 0x40000073 207 208 /* Define synthetic interrupt controller model specific registers. */ 209 #define HV_X64_MSR_SCONTROL 0x40000080 210 #define HV_X64_MSR_SVERSION 0x40000081 211 #define HV_X64_MSR_SIEFP 0x40000082 212 #define HV_X64_MSR_SIMP 0x40000083 213 #define HV_X64_MSR_EOM 0x40000084 214 #define HV_X64_MSR_SINT0 0x40000090 215 #define HV_X64_MSR_SINT1 0x40000091 216 #define HV_X64_MSR_SINT2 0x40000092 217 #define HV_X64_MSR_SINT3 0x40000093 218 #define HV_X64_MSR_SINT4 0x40000094 219 #define HV_X64_MSR_SINT5 0x40000095 220 #define HV_X64_MSR_SINT6 0x40000096 221 #define HV_X64_MSR_SINT7 0x40000097 222 #define HV_X64_MSR_SINT8 0x40000098 223 #define HV_X64_MSR_SINT9 0x40000099 224 #define HV_X64_MSR_SINT10 0x4000009A 225 #define HV_X64_MSR_SINT11 0x4000009B 226 #define HV_X64_MSR_SINT12 0x4000009C 227 #define HV_X64_MSR_SINT13 0x4000009D 228 #define HV_X64_MSR_SINT14 0x4000009E 229 #define HV_X64_MSR_SINT15 0x4000009F 230 231 /* 232 * Synthetic Timer MSRs. Four timers per vcpu. 233 */ 234 #define HV_X64_MSR_STIMER0_CONFIG 0x400000B0 235 #define HV_X64_MSR_STIMER0_COUNT 0x400000B1 236 #define HV_X64_MSR_STIMER1_CONFIG 0x400000B2 237 #define HV_X64_MSR_STIMER1_COUNT 0x400000B3 238 #define HV_X64_MSR_STIMER2_CONFIG 0x400000B4 239 #define HV_X64_MSR_STIMER2_COUNT 0x400000B5 240 #define HV_X64_MSR_STIMER3_CONFIG 0x400000B6 241 #define HV_X64_MSR_STIMER3_COUNT 0x400000B7 242 243 /* Hyper-V guest crash notification MSR's */ 244 #define HV_X64_MSR_CRASH_P0 0x40000100 245 #define HV_X64_MSR_CRASH_P1 0x40000101 246 #define HV_X64_MSR_CRASH_P2 0x40000102 247 #define HV_X64_MSR_CRASH_P3 0x40000103 248 #define HV_X64_MSR_CRASH_P4 0x40000104 249 #define HV_X64_MSR_CRASH_CTL 0x40000105 250 #define HV_X64_MSR_CRASH_CTL_NOTIFY (1ULL << 63) 251 #define HV_X64_MSR_CRASH_PARAMS \ 252 (1 + (HV_X64_MSR_CRASH_P4 - HV_X64_MSR_CRASH_P0)) 253 254 /* 255 * Declare the MSR used to setup pages used to communicate with the hypervisor. 256 */ 257 union hv_x64_msr_hypercall_contents { 258 u64 as_uint64; 259 struct { 260 u64 enable:1; 261 u64 reserved:11; 262 u64 guest_physical_address:52; 263 }; 264 }; 265 266 /* 267 * TSC page layout. 268 */ 269 struct ms_hyperv_tsc_page { 270 volatile u32 tsc_sequence; 271 u32 reserved1; 272 volatile u64 tsc_scale; 273 volatile s64 tsc_offset; 274 u64 reserved2[509]; 275 }; 276 277 /* 278 * The guest OS needs to register the guest ID with the hypervisor. 279 * The guest ID is a 64 bit entity and the structure of this ID is 280 * specified in the Hyper-V specification: 281 * 282 * msdn.microsoft.com/en-us/library/windows/hardware/ff542653%28v=vs.85%29.aspx 283 * 284 * While the current guideline does not specify how Linux guest ID(s) 285 * need to be generated, our plan is to publish the guidelines for 286 * Linux and other guest operating systems that currently are hosted 287 * on Hyper-V. The implementation here conforms to this yet 288 * unpublished guidelines. 289 * 290 * 291 * Bit(s) 292 * 63 - Indicates if the OS is Open Source or not; 1 is Open Source 293 * 62:56 - Os Type; Linux is 0x100 294 * 55:48 - Distro specific identification 295 * 47:16 - Linux kernel version number 296 * 15:0 - Distro specific identification 297 * 298 * 299 */ 300 301 #define HV_LINUX_VENDOR_ID 0x8100 302 303 /* TSC emulation after migration */ 304 #define HV_X64_MSR_REENLIGHTENMENT_CONTROL 0x40000106 305 306 struct hv_reenlightenment_control { 307 __u64 vector:8; 308 __u64 reserved1:8; 309 __u64 enabled:1; 310 __u64 reserved2:15; 311 __u64 target_vp:32; 312 }; 313 314 #define HV_X64_MSR_TSC_EMULATION_CONTROL 0x40000107 315 #define HV_X64_MSR_TSC_EMULATION_STATUS 0x40000108 316 317 struct hv_tsc_emulation_control { 318 __u64 enabled:1; 319 __u64 reserved:63; 320 }; 321 322 struct hv_tsc_emulation_status { 323 __u64 inprogress:1; 324 __u64 reserved:63; 325 }; 326 327 #define HV_X64_MSR_HYPERCALL_ENABLE 0x00000001 328 #define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT 12 329 #define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_MASK \ 330 (~((1ull << HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT) - 1)) 331 332 /* Declare the various hypercall operations. */ 333 #define HVCALL_FLUSH_VIRTUAL_ADDRESS_SPACE 0x0002 334 #define HVCALL_FLUSH_VIRTUAL_ADDRESS_LIST 0x0003 335 #define HVCALL_NOTIFY_LONG_SPIN_WAIT 0x0008 336 #define HVCALL_FLUSH_VIRTUAL_ADDRESS_SPACE_EX 0x0013 337 #define HVCALL_FLUSH_VIRTUAL_ADDRESS_LIST_EX 0x0014 338 #define HVCALL_POST_MESSAGE 0x005c 339 #define HVCALL_SIGNAL_EVENT 0x005d 340 341 #define HV_X64_MSR_VP_ASSIST_PAGE_ENABLE 0x00000001 342 #define HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_SHIFT 12 343 #define HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_MASK \ 344 (~((1ull << HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_SHIFT) - 1)) 345 346 /* Hyper-V Enlightened VMCS version mask in nested features CPUID */ 347 #define HV_X64_ENLIGHTENED_VMCS_VERSION 0xff 348 349 #define HV_X64_MSR_TSC_REFERENCE_ENABLE 0x00000001 350 #define HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT 12 351 352 #define HV_PROCESSOR_POWER_STATE_C0 0 353 #define HV_PROCESSOR_POWER_STATE_C1 1 354 #define HV_PROCESSOR_POWER_STATE_C2 2 355 #define HV_PROCESSOR_POWER_STATE_C3 3 356 357 #define HV_FLUSH_ALL_PROCESSORS BIT(0) 358 #define HV_FLUSH_ALL_VIRTUAL_ADDRESS_SPACES BIT(1) 359 #define HV_FLUSH_NON_GLOBAL_MAPPINGS_ONLY BIT(2) 360 #define HV_FLUSH_USE_EXTENDED_RANGE_FORMAT BIT(3) 361 362 enum HV_GENERIC_SET_FORMAT { 363 HV_GENERIC_SET_SPARCE_4K, 364 HV_GENERIC_SET_ALL, 365 }; 366 367 #define HV_HYPERCALL_RESULT_MASK GENMASK_ULL(15, 0) 368 #define HV_HYPERCALL_FAST_BIT BIT(16) 369 #define HV_HYPERCALL_VARHEAD_OFFSET 17 370 #define HV_HYPERCALL_REP_COMP_OFFSET 32 371 #define HV_HYPERCALL_REP_COMP_MASK GENMASK_ULL(43, 32) 372 #define HV_HYPERCALL_REP_START_OFFSET 48 373 #define HV_HYPERCALL_REP_START_MASK GENMASK_ULL(59, 48) 374 375 /* hypercall status code */ 376 #define HV_STATUS_SUCCESS 0 377 #define HV_STATUS_INVALID_HYPERCALL_CODE 2 378 #define HV_STATUS_INVALID_HYPERCALL_INPUT 3 379 #define HV_STATUS_INVALID_ALIGNMENT 4 380 #define HV_STATUS_INVALID_PARAMETER 5 381 #define HV_STATUS_INSUFFICIENT_MEMORY 11 382 #define HV_STATUS_INVALID_PORT_ID 17 383 #define HV_STATUS_INVALID_CONNECTION_ID 18 384 #define HV_STATUS_INSUFFICIENT_BUFFERS 19 385 386 typedef struct _HV_REFERENCE_TSC_PAGE { 387 __u32 tsc_sequence; 388 __u32 res1; 389 __u64 tsc_scale; 390 __s64 tsc_offset; 391 } HV_REFERENCE_TSC_PAGE, *PHV_REFERENCE_TSC_PAGE; 392 393 /* Define the number of synthetic interrupt sources. */ 394 #define HV_SYNIC_SINT_COUNT (16) 395 /* Define the expected SynIC version. */ 396 #define HV_SYNIC_VERSION_1 (0x1) 397 /* Valid SynIC vectors are 16-255. */ 398 #define HV_SYNIC_FIRST_VALID_VECTOR (16) 399 400 #define HV_SYNIC_CONTROL_ENABLE (1ULL << 0) 401 #define HV_SYNIC_SIMP_ENABLE (1ULL << 0) 402 #define HV_SYNIC_SIEFP_ENABLE (1ULL << 0) 403 #define HV_SYNIC_SINT_MASKED (1ULL << 16) 404 #define HV_SYNIC_SINT_AUTO_EOI (1ULL << 17) 405 #define HV_SYNIC_SINT_VECTOR_MASK (0xFF) 406 407 #define HV_SYNIC_STIMER_COUNT (4) 408 409 /* Define synthetic interrupt controller message constants. */ 410 #define HV_MESSAGE_SIZE (256) 411 #define HV_MESSAGE_PAYLOAD_BYTE_COUNT (240) 412 #define HV_MESSAGE_PAYLOAD_QWORD_COUNT (30) 413 414 /* Define hypervisor message types. */ 415 enum hv_message_type { 416 HVMSG_NONE = 0x00000000, 417 418 /* Memory access messages. */ 419 HVMSG_UNMAPPED_GPA = 0x80000000, 420 HVMSG_GPA_INTERCEPT = 0x80000001, 421 422 /* Timer notification messages. */ 423 HVMSG_TIMER_EXPIRED = 0x80000010, 424 425 /* Error messages. */ 426 HVMSG_INVALID_VP_REGISTER_VALUE = 0x80000020, 427 HVMSG_UNRECOVERABLE_EXCEPTION = 0x80000021, 428 HVMSG_UNSUPPORTED_FEATURE = 0x80000022, 429 430 /* Trace buffer complete messages. */ 431 HVMSG_EVENTLOG_BUFFERCOMPLETE = 0x80000040, 432 433 /* Platform-specific processor intercept messages. */ 434 HVMSG_X64_IOPORT_INTERCEPT = 0x80010000, 435 HVMSG_X64_MSR_INTERCEPT = 0x80010001, 436 HVMSG_X64_CPUID_INTERCEPT = 0x80010002, 437 HVMSG_X64_EXCEPTION_INTERCEPT = 0x80010003, 438 HVMSG_X64_APIC_EOI = 0x80010004, 439 HVMSG_X64_LEGACY_FP_ERROR = 0x80010005 440 }; 441 442 /* Define synthetic interrupt controller message flags. */ 443 union hv_message_flags { 444 __u8 asu8; 445 struct { 446 __u8 msg_pending:1; 447 __u8 reserved:7; 448 }; 449 }; 450 451 /* Define port identifier type. */ 452 union hv_port_id { 453 __u32 asu32; 454 struct { 455 __u32 id:24; 456 __u32 reserved:8; 457 } u; 458 }; 459 460 /* Define synthetic interrupt controller message header. */ 461 struct hv_message_header { 462 __u32 message_type; 463 __u8 payload_size; 464 union hv_message_flags message_flags; 465 __u8 reserved[2]; 466 union { 467 __u64 sender; 468 union hv_port_id port; 469 }; 470 }; 471 472 /* Define synthetic interrupt controller message format. */ 473 struct hv_message { 474 struct hv_message_header header; 475 union { 476 __u64 payload[HV_MESSAGE_PAYLOAD_QWORD_COUNT]; 477 } u; 478 }; 479 480 /* Define the synthetic interrupt message page layout. */ 481 struct hv_message_page { 482 struct hv_message sint_message[HV_SYNIC_SINT_COUNT]; 483 }; 484 485 /* Define timer message payload structure. */ 486 struct hv_timer_message_payload { 487 __u32 timer_index; 488 __u32 reserved; 489 __u64 expiration_time; /* When the timer expired */ 490 __u64 delivery_time; /* When the message was delivered */ 491 }; 492 493 /* Define virtual processor assist page structure. */ 494 struct hv_vp_assist_page { 495 __u32 apic_assist; 496 __u32 reserved; 497 __u64 vtl_control[2]; 498 __u64 nested_enlightenments_control[2]; 499 __u32 enlighten_vmentry; 500 __u64 current_nested_vmcs; 501 }; 502 503 struct hv_enlightened_vmcs { 504 u32 revision_id; 505 u32 abort; 506 507 u16 host_es_selector; 508 u16 host_cs_selector; 509 u16 host_ss_selector; 510 u16 host_ds_selector; 511 u16 host_fs_selector; 512 u16 host_gs_selector; 513 u16 host_tr_selector; 514 515 u64 host_ia32_pat; 516 u64 host_ia32_efer; 517 518 u64 host_cr0; 519 u64 host_cr3; 520 u64 host_cr4; 521 522 u64 host_ia32_sysenter_esp; 523 u64 host_ia32_sysenter_eip; 524 u64 host_rip; 525 u32 host_ia32_sysenter_cs; 526 527 u32 pin_based_vm_exec_control; 528 u32 vm_exit_controls; 529 u32 secondary_vm_exec_control; 530 531 u64 io_bitmap_a; 532 u64 io_bitmap_b; 533 u64 msr_bitmap; 534 535 u16 guest_es_selector; 536 u16 guest_cs_selector; 537 u16 guest_ss_selector; 538 u16 guest_ds_selector; 539 u16 guest_fs_selector; 540 u16 guest_gs_selector; 541 u16 guest_ldtr_selector; 542 u16 guest_tr_selector; 543 544 u32 guest_es_limit; 545 u32 guest_cs_limit; 546 u32 guest_ss_limit; 547 u32 guest_ds_limit; 548 u32 guest_fs_limit; 549 u32 guest_gs_limit; 550 u32 guest_ldtr_limit; 551 u32 guest_tr_limit; 552 u32 guest_gdtr_limit; 553 u32 guest_idtr_limit; 554 555 u32 guest_es_ar_bytes; 556 u32 guest_cs_ar_bytes; 557 u32 guest_ss_ar_bytes; 558 u32 guest_ds_ar_bytes; 559 u32 guest_fs_ar_bytes; 560 u32 guest_gs_ar_bytes; 561 u32 guest_ldtr_ar_bytes; 562 u32 guest_tr_ar_bytes; 563 564 u64 guest_es_base; 565 u64 guest_cs_base; 566 u64 guest_ss_base; 567 u64 guest_ds_base; 568 u64 guest_fs_base; 569 u64 guest_gs_base; 570 u64 guest_ldtr_base; 571 u64 guest_tr_base; 572 u64 guest_gdtr_base; 573 u64 guest_idtr_base; 574 575 u64 padding64_1[3]; 576 577 u64 vm_exit_msr_store_addr; 578 u64 vm_exit_msr_load_addr; 579 u64 vm_entry_msr_load_addr; 580 581 u64 cr3_target_value0; 582 u64 cr3_target_value1; 583 u64 cr3_target_value2; 584 u64 cr3_target_value3; 585 586 u32 page_fault_error_code_mask; 587 u32 page_fault_error_code_match; 588 589 u32 cr3_target_count; 590 u32 vm_exit_msr_store_count; 591 u32 vm_exit_msr_load_count; 592 u32 vm_entry_msr_load_count; 593 594 u64 tsc_offset; 595 u64 virtual_apic_page_addr; 596 u64 vmcs_link_pointer; 597 598 u64 guest_ia32_debugctl; 599 u64 guest_ia32_pat; 600 u64 guest_ia32_efer; 601 602 u64 guest_pdptr0; 603 u64 guest_pdptr1; 604 u64 guest_pdptr2; 605 u64 guest_pdptr3; 606 607 u64 guest_pending_dbg_exceptions; 608 u64 guest_sysenter_esp; 609 u64 guest_sysenter_eip; 610 611 u32 guest_activity_state; 612 u32 guest_sysenter_cs; 613 614 u64 cr0_guest_host_mask; 615 u64 cr4_guest_host_mask; 616 u64 cr0_read_shadow; 617 u64 cr4_read_shadow; 618 u64 guest_cr0; 619 u64 guest_cr3; 620 u64 guest_cr4; 621 u64 guest_dr7; 622 623 u64 host_fs_base; 624 u64 host_gs_base; 625 u64 host_tr_base; 626 u64 host_gdtr_base; 627 u64 host_idtr_base; 628 u64 host_rsp; 629 630 u64 ept_pointer; 631 632 u16 virtual_processor_id; 633 u16 padding16[3]; 634 635 u64 padding64_2[5]; 636 u64 guest_physical_address; 637 638 u32 vm_instruction_error; 639 u32 vm_exit_reason; 640 u32 vm_exit_intr_info; 641 u32 vm_exit_intr_error_code; 642 u32 idt_vectoring_info_field; 643 u32 idt_vectoring_error_code; 644 u32 vm_exit_instruction_len; 645 u32 vmx_instruction_info; 646 647 u64 exit_qualification; 648 u64 exit_io_instruction_ecx; 649 u64 exit_io_instruction_esi; 650 u64 exit_io_instruction_edi; 651 u64 exit_io_instruction_eip; 652 653 u64 guest_linear_address; 654 u64 guest_rsp; 655 u64 guest_rflags; 656 657 u32 guest_interruptibility_info; 658 u32 cpu_based_vm_exec_control; 659 u32 exception_bitmap; 660 u32 vm_entry_controls; 661 u32 vm_entry_intr_info_field; 662 u32 vm_entry_exception_error_code; 663 u32 vm_entry_instruction_len; 664 u32 tpr_threshold; 665 666 u64 guest_rip; 667 668 u32 hv_clean_fields; 669 u32 hv_padding_32; 670 u32 hv_synthetic_controls; 671 u32 hv_enlightenments_control; 672 u32 hv_vp_id; 673 674 u64 hv_vm_id; 675 u64 partition_assist_page; 676 u64 padding64_4[4]; 677 u64 guest_bndcfgs; 678 u64 padding64_5[7]; 679 u64 xss_exit_bitmap; 680 u64 padding64_6[7]; 681 }; 682 683 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_NONE 0 684 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_IO_BITMAP BIT(0) 685 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_MSR_BITMAP BIT(1) 686 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_GRP2 BIT(2) 687 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_GRP1 BIT(3) 688 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_PROC BIT(4) 689 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_EVENT BIT(5) 690 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_ENTRY BIT(6) 691 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_EXCPN BIT(7) 692 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CRDR BIT(8) 693 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_XLAT BIT(9) 694 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_BASIC BIT(10) 695 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_GRP1 BIT(11) 696 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_GRP2 BIT(12) 697 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_HOST_POINTER BIT(13) 698 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_HOST_GRP1 BIT(14) 699 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_ENLIGHTENMENTSCONTROL BIT(15) 700 701 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL 0xFFFF 702 703 #define HV_STIMER_ENABLE (1ULL << 0) 704 #define HV_STIMER_PERIODIC (1ULL << 1) 705 #define HV_STIMER_LAZY (1ULL << 2) 706 #define HV_STIMER_AUTOENABLE (1ULL << 3) 707 #define HV_STIMER_SINT(config) (__u8)(((config) >> 16) & 0x0F) 708 709 #endif 710