1 /* SPDX-License-Identifier: GPL-2.0 */ 2 3 /* 4 * This file contains definitions from Hyper-V Hypervisor Top-Level Functional 5 * Specification (TLFS): 6 * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs 7 */ 8 9 #ifndef _ASM_X86_HYPERV_TLFS_H 10 #define _ASM_X86_HYPERV_TLFS_H 11 12 #include <linux/types.h> 13 #include <asm/page.h> 14 /* 15 * The below CPUID leaves are present if VersionAndFeatures.HypervisorPresent 16 * is set by CPUID(HvCpuIdFunctionVersionAndFeatures). 17 */ 18 #define HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS 0x40000000 19 #define HYPERV_CPUID_INTERFACE 0x40000001 20 #define HYPERV_CPUID_VERSION 0x40000002 21 #define HYPERV_CPUID_FEATURES 0x40000003 22 #define HYPERV_CPUID_ENLIGHTMENT_INFO 0x40000004 23 #define HYPERV_CPUID_IMPLEMENT_LIMITS 0x40000005 24 #define HYPERV_CPUID_CPU_MANAGEMENT_FEATURES 0x40000007 25 #define HYPERV_CPUID_NESTED_FEATURES 0x4000000A 26 #define HYPERV_CPUID_ISOLATION_CONFIG 0x4000000C 27 28 #define HYPERV_CPUID_VIRT_STACK_INTERFACE 0x40000081 29 #define HYPERV_VS_INTERFACE_EAX_SIGNATURE 0x31235356 /* "VS#1" */ 30 31 #define HYPERV_CPUID_VIRT_STACK_PROPERTIES 0x40000082 32 /* Support for the extended IOAPIC RTE format */ 33 #define HYPERV_VS_PROPERTIES_EAX_EXTENDED_IOAPIC_RTE BIT(2) 34 35 #define HYPERV_HYPERVISOR_PRESENT_BIT 0x80000000 36 #define HYPERV_CPUID_MIN 0x40000005 37 #define HYPERV_CPUID_MAX 0x4000ffff 38 39 /* 40 * Group D Features. The bit assignments are custom to each architecture. 41 * On x86/x64 these are HYPERV_CPUID_FEATURES.EDX bits. 42 */ 43 /* The MWAIT instruction is available (per section MONITOR / MWAIT) */ 44 #define HV_X64_MWAIT_AVAILABLE BIT(0) 45 /* Guest debugging support is available */ 46 #define HV_X64_GUEST_DEBUGGING_AVAILABLE BIT(1) 47 /* Performance Monitor support is available*/ 48 #define HV_X64_PERF_MONITOR_AVAILABLE BIT(2) 49 /* Support for physical CPU dynamic partitioning events is available*/ 50 #define HV_X64_CPU_DYNAMIC_PARTITIONING_AVAILABLE BIT(3) 51 /* 52 * Support for passing hypercall input parameter block via XMM 53 * registers is available 54 */ 55 #define HV_X64_HYPERCALL_XMM_INPUT_AVAILABLE BIT(4) 56 /* Support for a virtual guest idle state is available */ 57 #define HV_X64_GUEST_IDLE_STATE_AVAILABLE BIT(5) 58 /* Frequency MSRs available */ 59 #define HV_FEATURE_FREQUENCY_MSRS_AVAILABLE BIT(8) 60 /* Crash MSR available */ 61 #define HV_FEATURE_GUEST_CRASH_MSR_AVAILABLE BIT(10) 62 /* Support for debug MSRs available */ 63 #define HV_FEATURE_DEBUG_MSRS_AVAILABLE BIT(11) 64 /* 65 * Support for returning hypercall output block via XMM 66 * registers is available 67 */ 68 #define HV_X64_HYPERCALL_XMM_OUTPUT_AVAILABLE BIT(15) 69 /* stimer Direct Mode is available */ 70 #define HV_STIMER_DIRECT_MODE_AVAILABLE BIT(19) 71 72 /* 73 * Implementation recommendations. Indicates which behaviors the hypervisor 74 * recommends the OS implement for optimal performance. 75 * These are HYPERV_CPUID_ENLIGHTMENT_INFO.EAX bits. 76 */ 77 /* 78 * Recommend using hypercall for address space switches rather 79 * than MOV to CR3 instruction 80 */ 81 #define HV_X64_AS_SWITCH_RECOMMENDED BIT(0) 82 /* Recommend using hypercall for local TLB flushes rather 83 * than INVLPG or MOV to CR3 instructions */ 84 #define HV_X64_LOCAL_TLB_FLUSH_RECOMMENDED BIT(1) 85 /* 86 * Recommend using hypercall for remote TLB flushes rather 87 * than inter-processor interrupts 88 */ 89 #define HV_X64_REMOTE_TLB_FLUSH_RECOMMENDED BIT(2) 90 /* 91 * Recommend using MSRs for accessing APIC registers 92 * EOI, ICR and TPR rather than their memory-mapped counterparts 93 */ 94 #define HV_X64_APIC_ACCESS_RECOMMENDED BIT(3) 95 /* Recommend using the hypervisor-provided MSR to initiate a system RESET */ 96 #define HV_X64_SYSTEM_RESET_RECOMMENDED BIT(4) 97 /* 98 * Recommend using relaxed timing for this partition. If used, 99 * the VM should disable any watchdog timeouts that rely on the 100 * timely delivery of external interrupts 101 */ 102 #define HV_X64_RELAXED_TIMING_RECOMMENDED BIT(5) 103 104 /* 105 * Recommend not using Auto End-Of-Interrupt feature 106 */ 107 #define HV_DEPRECATING_AEOI_RECOMMENDED BIT(9) 108 109 /* 110 * Recommend using cluster IPI hypercalls. 111 */ 112 #define HV_X64_CLUSTER_IPI_RECOMMENDED BIT(10) 113 114 /* Recommend using the newer ExProcessorMasks interface */ 115 #define HV_X64_EX_PROCESSOR_MASKS_RECOMMENDED BIT(11) 116 117 /* Recommend using enlightened VMCS */ 118 #define HV_X64_ENLIGHTENED_VMCS_RECOMMENDED BIT(14) 119 120 /* 121 * CPU management features identification. 122 * These are HYPERV_CPUID_CPU_MANAGEMENT_FEATURES.EAX bits. 123 */ 124 #define HV_X64_START_LOGICAL_PROCESSOR BIT(0) 125 #define HV_X64_CREATE_ROOT_VIRTUAL_PROCESSOR BIT(1) 126 #define HV_X64_PERFORMANCE_COUNTER_SYNC BIT(2) 127 #define HV_X64_RESERVED_IDENTITY_BIT BIT(31) 128 129 /* 130 * Virtual processor will never share a physical core with another virtual 131 * processor, except for virtual processors that are reported as sibling SMT 132 * threads. 133 */ 134 #define HV_X64_NO_NONARCH_CORESHARING BIT(18) 135 136 /* Nested features. These are HYPERV_CPUID_NESTED_FEATURES.EAX bits. */ 137 #define HV_X64_NESTED_DIRECT_FLUSH BIT(17) 138 #define HV_X64_NESTED_GUEST_MAPPING_FLUSH BIT(18) 139 #define HV_X64_NESTED_MSR_BITMAP BIT(19) 140 141 /* 142 * This is specific to AMD and specifies that enlightened TLB flush is 143 * supported. If guest opts in to this feature, ASID invalidations only 144 * flushes gva -> hpa mapping entries. To flush the TLB entries derived 145 * from NPT, hypercalls should be used (HvFlushGuestPhysicalAddressSpace 146 * or HvFlushGuestPhysicalAddressList). 147 */ 148 #define HV_X64_NESTED_ENLIGHTENED_TLB BIT(22) 149 150 /* HYPERV_CPUID_ISOLATION_CONFIG.EAX bits. */ 151 #define HV_PARAVISOR_PRESENT BIT(0) 152 153 /* HYPERV_CPUID_ISOLATION_CONFIG.EBX bits. */ 154 #define HV_ISOLATION_TYPE GENMASK(3, 0) 155 #define HV_SHARED_GPA_BOUNDARY_ACTIVE BIT(5) 156 #define HV_SHARED_GPA_BOUNDARY_BITS GENMASK(11, 6) 157 158 enum hv_isolation_type { 159 HV_ISOLATION_TYPE_NONE = 0, 160 HV_ISOLATION_TYPE_VBS = 1, 161 HV_ISOLATION_TYPE_SNP = 2 162 }; 163 164 /* Hyper-V specific model specific registers (MSRs) */ 165 166 /* MSR used to identify the guest OS. */ 167 #define HV_X64_MSR_GUEST_OS_ID 0x40000000 168 169 /* MSR used to setup pages used to communicate with the hypervisor. */ 170 #define HV_X64_MSR_HYPERCALL 0x40000001 171 172 /* MSR used to provide vcpu index */ 173 #define HV_REGISTER_VP_INDEX 0x40000002 174 175 /* MSR used to reset the guest OS. */ 176 #define HV_X64_MSR_RESET 0x40000003 177 178 /* MSR used to provide vcpu runtime in 100ns units */ 179 #define HV_X64_MSR_VP_RUNTIME 0x40000010 180 181 /* MSR used to read the per-partition time reference counter */ 182 #define HV_REGISTER_TIME_REF_COUNT 0x40000020 183 184 /* A partition's reference time stamp counter (TSC) page */ 185 #define HV_REGISTER_REFERENCE_TSC 0x40000021 186 187 /* MSR used to retrieve the TSC frequency */ 188 #define HV_X64_MSR_TSC_FREQUENCY 0x40000022 189 190 /* MSR used to retrieve the local APIC timer frequency */ 191 #define HV_X64_MSR_APIC_FREQUENCY 0x40000023 192 193 /* Define the virtual APIC registers */ 194 #define HV_X64_MSR_EOI 0x40000070 195 #define HV_X64_MSR_ICR 0x40000071 196 #define HV_X64_MSR_TPR 0x40000072 197 #define HV_X64_MSR_VP_ASSIST_PAGE 0x40000073 198 199 /* Define synthetic interrupt controller model specific registers. */ 200 #define HV_REGISTER_SCONTROL 0x40000080 201 #define HV_REGISTER_SVERSION 0x40000081 202 #define HV_REGISTER_SIEFP 0x40000082 203 #define HV_REGISTER_SIMP 0x40000083 204 #define HV_REGISTER_EOM 0x40000084 205 #define HV_REGISTER_SINT0 0x40000090 206 #define HV_REGISTER_SINT1 0x40000091 207 #define HV_REGISTER_SINT2 0x40000092 208 #define HV_REGISTER_SINT3 0x40000093 209 #define HV_REGISTER_SINT4 0x40000094 210 #define HV_REGISTER_SINT5 0x40000095 211 #define HV_REGISTER_SINT6 0x40000096 212 #define HV_REGISTER_SINT7 0x40000097 213 #define HV_REGISTER_SINT8 0x40000098 214 #define HV_REGISTER_SINT9 0x40000099 215 #define HV_REGISTER_SINT10 0x4000009A 216 #define HV_REGISTER_SINT11 0x4000009B 217 #define HV_REGISTER_SINT12 0x4000009C 218 #define HV_REGISTER_SINT13 0x4000009D 219 #define HV_REGISTER_SINT14 0x4000009E 220 #define HV_REGISTER_SINT15 0x4000009F 221 222 /* 223 * Synthetic Timer MSRs. Four timers per vcpu. 224 */ 225 #define HV_REGISTER_STIMER0_CONFIG 0x400000B0 226 #define HV_REGISTER_STIMER0_COUNT 0x400000B1 227 #define HV_REGISTER_STIMER1_CONFIG 0x400000B2 228 #define HV_REGISTER_STIMER1_COUNT 0x400000B3 229 #define HV_REGISTER_STIMER2_CONFIG 0x400000B4 230 #define HV_REGISTER_STIMER2_COUNT 0x400000B5 231 #define HV_REGISTER_STIMER3_CONFIG 0x400000B6 232 #define HV_REGISTER_STIMER3_COUNT 0x400000B7 233 234 /* Hyper-V guest idle MSR */ 235 #define HV_X64_MSR_GUEST_IDLE 0x400000F0 236 237 /* Hyper-V guest crash notification MSR's */ 238 #define HV_REGISTER_CRASH_P0 0x40000100 239 #define HV_REGISTER_CRASH_P1 0x40000101 240 #define HV_REGISTER_CRASH_P2 0x40000102 241 #define HV_REGISTER_CRASH_P3 0x40000103 242 #define HV_REGISTER_CRASH_P4 0x40000104 243 #define HV_REGISTER_CRASH_CTL 0x40000105 244 245 /* TSC emulation after migration */ 246 #define HV_X64_MSR_REENLIGHTENMENT_CONTROL 0x40000106 247 #define HV_X64_MSR_TSC_EMULATION_CONTROL 0x40000107 248 #define HV_X64_MSR_TSC_EMULATION_STATUS 0x40000108 249 250 /* TSC invariant control */ 251 #define HV_X64_MSR_TSC_INVARIANT_CONTROL 0x40000118 252 253 /* Register name aliases for temporary compatibility */ 254 #define HV_X64_MSR_STIMER0_COUNT HV_REGISTER_STIMER0_COUNT 255 #define HV_X64_MSR_STIMER0_CONFIG HV_REGISTER_STIMER0_CONFIG 256 #define HV_X64_MSR_STIMER1_COUNT HV_REGISTER_STIMER1_COUNT 257 #define HV_X64_MSR_STIMER1_CONFIG HV_REGISTER_STIMER1_CONFIG 258 #define HV_X64_MSR_STIMER2_COUNT HV_REGISTER_STIMER2_COUNT 259 #define HV_X64_MSR_STIMER2_CONFIG HV_REGISTER_STIMER2_CONFIG 260 #define HV_X64_MSR_STIMER3_COUNT HV_REGISTER_STIMER3_COUNT 261 #define HV_X64_MSR_STIMER3_CONFIG HV_REGISTER_STIMER3_CONFIG 262 #define HV_X64_MSR_SCONTROL HV_REGISTER_SCONTROL 263 #define HV_X64_MSR_SVERSION HV_REGISTER_SVERSION 264 #define HV_X64_MSR_SIMP HV_REGISTER_SIMP 265 #define HV_X64_MSR_SIEFP HV_REGISTER_SIEFP 266 #define HV_X64_MSR_VP_INDEX HV_REGISTER_VP_INDEX 267 #define HV_X64_MSR_EOM HV_REGISTER_EOM 268 #define HV_X64_MSR_SINT0 HV_REGISTER_SINT0 269 #define HV_X64_MSR_SINT15 HV_REGISTER_SINT15 270 #define HV_X64_MSR_CRASH_P0 HV_REGISTER_CRASH_P0 271 #define HV_X64_MSR_CRASH_P1 HV_REGISTER_CRASH_P1 272 #define HV_X64_MSR_CRASH_P2 HV_REGISTER_CRASH_P2 273 #define HV_X64_MSR_CRASH_P3 HV_REGISTER_CRASH_P3 274 #define HV_X64_MSR_CRASH_P4 HV_REGISTER_CRASH_P4 275 #define HV_X64_MSR_CRASH_CTL HV_REGISTER_CRASH_CTL 276 #define HV_X64_MSR_TIME_REF_COUNT HV_REGISTER_TIME_REF_COUNT 277 #define HV_X64_MSR_REFERENCE_TSC HV_REGISTER_REFERENCE_TSC 278 279 /* Hyper-V memory host visibility */ 280 enum hv_mem_host_visibility { 281 VMBUS_PAGE_NOT_VISIBLE = 0, 282 VMBUS_PAGE_VISIBLE_READ_ONLY = 1, 283 VMBUS_PAGE_VISIBLE_READ_WRITE = 3 284 }; 285 286 /* HvCallModifySparseGpaPageHostVisibility hypercall */ 287 #define HV_MAX_MODIFY_GPA_REP_COUNT ((PAGE_SIZE / sizeof(u64)) - 2) 288 struct hv_gpa_range_for_visibility { 289 u64 partition_id; 290 u32 host_visibility:2; 291 u32 reserved0:30; 292 u32 reserved1; 293 u64 gpa_page_list[HV_MAX_MODIFY_GPA_REP_COUNT]; 294 } __packed; 295 296 /* 297 * Declare the MSR used to setup pages used to communicate with the hypervisor. 298 */ 299 union hv_x64_msr_hypercall_contents { 300 u64 as_uint64; 301 struct { 302 u64 enable:1; 303 u64 reserved:11; 304 u64 guest_physical_address:52; 305 } __packed; 306 }; 307 308 union hv_vp_assist_msr_contents { 309 u64 as_uint64; 310 struct { 311 u64 enable:1; 312 u64 reserved:11; 313 u64 pfn:52; 314 } __packed; 315 }; 316 317 struct hv_reenlightenment_control { 318 __u64 vector:8; 319 __u64 reserved1:8; 320 __u64 enabled:1; 321 __u64 reserved2:15; 322 __u64 target_vp:32; 323 } __packed; 324 325 struct hv_tsc_emulation_control { 326 __u64 enabled:1; 327 __u64 reserved:63; 328 } __packed; 329 330 struct hv_tsc_emulation_status { 331 __u64 inprogress:1; 332 __u64 reserved:63; 333 } __packed; 334 335 #define HV_X64_MSR_HYPERCALL_ENABLE 0x00000001 336 #define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT 12 337 #define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_MASK \ 338 (~((1ull << HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT) - 1)) 339 340 #define HV_X64_MSR_CRASH_PARAMS \ 341 (1 + (HV_X64_MSR_CRASH_P4 - HV_X64_MSR_CRASH_P0)) 342 343 #define HV_IPI_LOW_VECTOR 0x10 344 #define HV_IPI_HIGH_VECTOR 0xff 345 346 #define HV_X64_MSR_VP_ASSIST_PAGE_ENABLE 0x00000001 347 #define HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_SHIFT 12 348 #define HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_MASK \ 349 (~((1ull << HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_SHIFT) - 1)) 350 351 /* Hyper-V Enlightened VMCS version mask in nested features CPUID */ 352 #define HV_X64_ENLIGHTENED_VMCS_VERSION 0xff 353 354 #define HV_X64_MSR_TSC_REFERENCE_ENABLE 0x00000001 355 #define HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT 12 356 357 /* Number of XMM registers used in hypercall input/output */ 358 #define HV_HYPERCALL_MAX_XMM_REGISTERS 6 359 360 struct hv_nested_enlightenments_control { 361 struct { 362 __u32 directhypercall:1; 363 __u32 reserved:31; 364 } features; 365 struct { 366 __u32 reserved; 367 } hypercallControls; 368 } __packed; 369 370 /* Define virtual processor assist page structure. */ 371 struct hv_vp_assist_page { 372 __u32 apic_assist; 373 __u32 reserved1; 374 __u64 vtl_control[3]; 375 struct hv_nested_enlightenments_control nested_control; 376 __u8 enlighten_vmentry; 377 __u8 reserved2[7]; 378 __u64 current_nested_vmcs; 379 } __packed; 380 381 struct hv_enlightened_vmcs { 382 u32 revision_id; 383 u32 abort; 384 385 u16 host_es_selector; 386 u16 host_cs_selector; 387 u16 host_ss_selector; 388 u16 host_ds_selector; 389 u16 host_fs_selector; 390 u16 host_gs_selector; 391 u16 host_tr_selector; 392 393 u16 padding16_1; 394 395 u64 host_ia32_pat; 396 u64 host_ia32_efer; 397 398 u64 host_cr0; 399 u64 host_cr3; 400 u64 host_cr4; 401 402 u64 host_ia32_sysenter_esp; 403 u64 host_ia32_sysenter_eip; 404 u64 host_rip; 405 u32 host_ia32_sysenter_cs; 406 407 u32 pin_based_vm_exec_control; 408 u32 vm_exit_controls; 409 u32 secondary_vm_exec_control; 410 411 u64 io_bitmap_a; 412 u64 io_bitmap_b; 413 u64 msr_bitmap; 414 415 u16 guest_es_selector; 416 u16 guest_cs_selector; 417 u16 guest_ss_selector; 418 u16 guest_ds_selector; 419 u16 guest_fs_selector; 420 u16 guest_gs_selector; 421 u16 guest_ldtr_selector; 422 u16 guest_tr_selector; 423 424 u32 guest_es_limit; 425 u32 guest_cs_limit; 426 u32 guest_ss_limit; 427 u32 guest_ds_limit; 428 u32 guest_fs_limit; 429 u32 guest_gs_limit; 430 u32 guest_ldtr_limit; 431 u32 guest_tr_limit; 432 u32 guest_gdtr_limit; 433 u32 guest_idtr_limit; 434 435 u32 guest_es_ar_bytes; 436 u32 guest_cs_ar_bytes; 437 u32 guest_ss_ar_bytes; 438 u32 guest_ds_ar_bytes; 439 u32 guest_fs_ar_bytes; 440 u32 guest_gs_ar_bytes; 441 u32 guest_ldtr_ar_bytes; 442 u32 guest_tr_ar_bytes; 443 444 u64 guest_es_base; 445 u64 guest_cs_base; 446 u64 guest_ss_base; 447 u64 guest_ds_base; 448 u64 guest_fs_base; 449 u64 guest_gs_base; 450 u64 guest_ldtr_base; 451 u64 guest_tr_base; 452 u64 guest_gdtr_base; 453 u64 guest_idtr_base; 454 455 u64 padding64_1[3]; 456 457 u64 vm_exit_msr_store_addr; 458 u64 vm_exit_msr_load_addr; 459 u64 vm_entry_msr_load_addr; 460 461 u64 cr3_target_value0; 462 u64 cr3_target_value1; 463 u64 cr3_target_value2; 464 u64 cr3_target_value3; 465 466 u32 page_fault_error_code_mask; 467 u32 page_fault_error_code_match; 468 469 u32 cr3_target_count; 470 u32 vm_exit_msr_store_count; 471 u32 vm_exit_msr_load_count; 472 u32 vm_entry_msr_load_count; 473 474 u64 tsc_offset; 475 u64 virtual_apic_page_addr; 476 u64 vmcs_link_pointer; 477 478 u64 guest_ia32_debugctl; 479 u64 guest_ia32_pat; 480 u64 guest_ia32_efer; 481 482 u64 guest_pdptr0; 483 u64 guest_pdptr1; 484 u64 guest_pdptr2; 485 u64 guest_pdptr3; 486 487 u64 guest_pending_dbg_exceptions; 488 u64 guest_sysenter_esp; 489 u64 guest_sysenter_eip; 490 491 u32 guest_activity_state; 492 u32 guest_sysenter_cs; 493 494 u64 cr0_guest_host_mask; 495 u64 cr4_guest_host_mask; 496 u64 cr0_read_shadow; 497 u64 cr4_read_shadow; 498 u64 guest_cr0; 499 u64 guest_cr3; 500 u64 guest_cr4; 501 u64 guest_dr7; 502 503 u64 host_fs_base; 504 u64 host_gs_base; 505 u64 host_tr_base; 506 u64 host_gdtr_base; 507 u64 host_idtr_base; 508 u64 host_rsp; 509 510 u64 ept_pointer; 511 512 u16 virtual_processor_id; 513 u16 padding16_2[3]; 514 515 u64 padding64_2[5]; 516 u64 guest_physical_address; 517 518 u32 vm_instruction_error; 519 u32 vm_exit_reason; 520 u32 vm_exit_intr_info; 521 u32 vm_exit_intr_error_code; 522 u32 idt_vectoring_info_field; 523 u32 idt_vectoring_error_code; 524 u32 vm_exit_instruction_len; 525 u32 vmx_instruction_info; 526 527 u64 exit_qualification; 528 u64 exit_io_instruction_ecx; 529 u64 exit_io_instruction_esi; 530 u64 exit_io_instruction_edi; 531 u64 exit_io_instruction_eip; 532 533 u64 guest_linear_address; 534 u64 guest_rsp; 535 u64 guest_rflags; 536 537 u32 guest_interruptibility_info; 538 u32 cpu_based_vm_exec_control; 539 u32 exception_bitmap; 540 u32 vm_entry_controls; 541 u32 vm_entry_intr_info_field; 542 u32 vm_entry_exception_error_code; 543 u32 vm_entry_instruction_len; 544 u32 tpr_threshold; 545 546 u64 guest_rip; 547 548 u32 hv_clean_fields; 549 u32 hv_padding_32; 550 u32 hv_synthetic_controls; 551 struct { 552 u32 nested_flush_hypercall:1; 553 u32 msr_bitmap:1; 554 u32 reserved:30; 555 } __packed hv_enlightenments_control; 556 u32 hv_vp_id; 557 558 u64 hv_vm_id; 559 u64 partition_assist_page; 560 u64 padding64_4[4]; 561 u64 guest_bndcfgs; 562 u64 padding64_5[7]; 563 u64 xss_exit_bitmap; 564 u64 padding64_6[7]; 565 } __packed; 566 567 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_NONE 0 568 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_IO_BITMAP BIT(0) 569 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_MSR_BITMAP BIT(1) 570 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_GRP2 BIT(2) 571 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_GRP1 BIT(3) 572 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_PROC BIT(4) 573 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_EVENT BIT(5) 574 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_ENTRY BIT(6) 575 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_EXCPN BIT(7) 576 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CRDR BIT(8) 577 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_XLAT BIT(9) 578 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_BASIC BIT(10) 579 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_GRP1 BIT(11) 580 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_GRP2 BIT(12) 581 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_HOST_POINTER BIT(13) 582 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_HOST_GRP1 BIT(14) 583 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_ENLIGHTENMENTSCONTROL BIT(15) 584 585 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL 0xFFFF 586 587 struct hv_partition_assist_pg { 588 u32 tlb_lock_count; 589 }; 590 591 enum hv_interrupt_type { 592 HV_X64_INTERRUPT_TYPE_FIXED = 0x0000, 593 HV_X64_INTERRUPT_TYPE_LOWESTPRIORITY = 0x0001, 594 HV_X64_INTERRUPT_TYPE_SMI = 0x0002, 595 HV_X64_INTERRUPT_TYPE_REMOTEREAD = 0x0003, 596 HV_X64_INTERRUPT_TYPE_NMI = 0x0004, 597 HV_X64_INTERRUPT_TYPE_INIT = 0x0005, 598 HV_X64_INTERRUPT_TYPE_SIPI = 0x0006, 599 HV_X64_INTERRUPT_TYPE_EXTINT = 0x0007, 600 HV_X64_INTERRUPT_TYPE_LOCALINT0 = 0x0008, 601 HV_X64_INTERRUPT_TYPE_LOCALINT1 = 0x0009, 602 HV_X64_INTERRUPT_TYPE_MAXIMUM = 0x000A, 603 }; 604 605 #include <asm-generic/hyperv-tlfs.h> 606 607 #endif 608