1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ 2 3 /* 4 * This file contains definitions from Hyper-V Hypervisor Top-Level Functional 5 * Specification (TLFS): 6 * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs 7 */ 8 9 #ifndef _ASM_X86_HYPERV_TLFS_H 10 #define _ASM_X86_HYPERV_TLFS_H 11 12 #include <linux/types.h> 13 14 /* 15 * The below CPUID leaves are present if VersionAndFeatures.HypervisorPresent 16 * is set by CPUID(HvCpuIdFunctionVersionAndFeatures). 17 */ 18 #define HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS 0x40000000 19 #define HYPERV_CPUID_INTERFACE 0x40000001 20 #define HYPERV_CPUID_VERSION 0x40000002 21 #define HYPERV_CPUID_FEATURES 0x40000003 22 #define HYPERV_CPUID_ENLIGHTMENT_INFO 0x40000004 23 #define HYPERV_CPUID_IMPLEMENT_LIMITS 0x40000005 24 #define HYPERV_CPUID_NESTED_FEATURES 0x4000000A 25 26 #define HYPERV_HYPERVISOR_PRESENT_BIT 0x80000000 27 #define HYPERV_CPUID_MIN 0x40000005 28 #define HYPERV_CPUID_MAX 0x4000ffff 29 30 /* 31 * Feature identification. EAX indicates which features are available 32 * to the partition based upon the current partition privileges. 33 */ 34 35 /* VP Runtime (HV_X64_MSR_VP_RUNTIME) available */ 36 #define HV_X64_MSR_VP_RUNTIME_AVAILABLE (1 << 0) 37 /* Partition Reference Counter (HV_X64_MSR_TIME_REF_COUNT) available*/ 38 #define HV_X64_MSR_TIME_REF_COUNT_AVAILABLE (1 << 1) 39 /* Partition reference TSC MSR is available */ 40 #define HV_X64_MSR_REFERENCE_TSC_AVAILABLE (1 << 9) 41 42 /* A partition's reference time stamp counter (TSC) page */ 43 #define HV_X64_MSR_REFERENCE_TSC 0x40000021 44 45 /* 46 * There is a single feature flag that signifies if the partition has access 47 * to MSRs with local APIC and TSC frequencies. 48 */ 49 #define HV_X64_ACCESS_FREQUENCY_MSRS (1 << 11) 50 51 /* AccessReenlightenmentControls privilege */ 52 #define HV_X64_ACCESS_REENLIGHTENMENT BIT(13) 53 54 /* 55 * Basic SynIC MSRs (HV_X64_MSR_SCONTROL through HV_X64_MSR_EOM 56 * and HV_X64_MSR_SINT0 through HV_X64_MSR_SINT15) available 57 */ 58 #define HV_X64_MSR_SYNIC_AVAILABLE (1 << 2) 59 /* 60 * Synthetic Timer MSRs (HV_X64_MSR_STIMER0_CONFIG through 61 * HV_X64_MSR_STIMER3_COUNT) available 62 */ 63 #define HV_X64_MSR_SYNTIMER_AVAILABLE (1 << 3) 64 /* 65 * APIC access MSRs (HV_X64_MSR_EOI, HV_X64_MSR_ICR and HV_X64_MSR_TPR) 66 * are available 67 */ 68 #define HV_X64_MSR_APIC_ACCESS_AVAILABLE (1 << 4) 69 /* Hypercall MSRs (HV_X64_MSR_GUEST_OS_ID and HV_X64_MSR_HYPERCALL) available*/ 70 #define HV_X64_MSR_HYPERCALL_AVAILABLE (1 << 5) 71 /* Access virtual processor index MSR (HV_X64_MSR_VP_INDEX) available*/ 72 #define HV_X64_MSR_VP_INDEX_AVAILABLE (1 << 6) 73 /* Virtual system reset MSR (HV_X64_MSR_RESET) is available*/ 74 #define HV_X64_MSR_RESET_AVAILABLE (1 << 7) 75 /* 76 * Access statistics pages MSRs (HV_X64_MSR_STATS_PARTITION_RETAIL_PAGE, 77 * HV_X64_MSR_STATS_PARTITION_INTERNAL_PAGE, HV_X64_MSR_STATS_VP_RETAIL_PAGE, 78 * HV_X64_MSR_STATS_VP_INTERNAL_PAGE) available 79 */ 80 #define HV_X64_MSR_STAT_PAGES_AVAILABLE (1 << 8) 81 82 /* Frequency MSRs available */ 83 #define HV_FEATURE_FREQUENCY_MSRS_AVAILABLE (1 << 8) 84 85 /* Crash MSR available */ 86 #define HV_FEATURE_GUEST_CRASH_MSR_AVAILABLE (1 << 10) 87 88 /* stimer Direct Mode is available */ 89 #define HV_X64_STIMER_DIRECT_MODE_AVAILABLE (1 << 19) 90 91 /* 92 * Feature identification: EBX indicates which flags were specified at 93 * partition creation. The format is the same as the partition creation 94 * flag structure defined in section Partition Creation Flags. 95 */ 96 #define HV_X64_CREATE_PARTITIONS (1 << 0) 97 #define HV_X64_ACCESS_PARTITION_ID (1 << 1) 98 #define HV_X64_ACCESS_MEMORY_POOL (1 << 2) 99 #define HV_X64_ADJUST_MESSAGE_BUFFERS (1 << 3) 100 #define HV_X64_POST_MESSAGES (1 << 4) 101 #define HV_X64_SIGNAL_EVENTS (1 << 5) 102 #define HV_X64_CREATE_PORT (1 << 6) 103 #define HV_X64_CONNECT_PORT (1 << 7) 104 #define HV_X64_ACCESS_STATS (1 << 8) 105 #define HV_X64_DEBUGGING (1 << 11) 106 #define HV_X64_CPU_POWER_MANAGEMENT (1 << 12) 107 #define HV_X64_CONFIGURE_PROFILER (1 << 13) 108 109 /* 110 * Feature identification. EDX indicates which miscellaneous features 111 * are available to the partition. 112 */ 113 /* The MWAIT instruction is available (per section MONITOR / MWAIT) */ 114 #define HV_X64_MWAIT_AVAILABLE (1 << 0) 115 /* Guest debugging support is available */ 116 #define HV_X64_GUEST_DEBUGGING_AVAILABLE (1 << 1) 117 /* Performance Monitor support is available*/ 118 #define HV_X64_PERF_MONITOR_AVAILABLE (1 << 2) 119 /* Support for physical CPU dynamic partitioning events is available*/ 120 #define HV_X64_CPU_DYNAMIC_PARTITIONING_AVAILABLE (1 << 3) 121 /* 122 * Support for passing hypercall input parameter block via XMM 123 * registers is available 124 */ 125 #define HV_X64_HYPERCALL_PARAMS_XMM_AVAILABLE (1 << 4) 126 /* Support for a virtual guest idle state is available */ 127 #define HV_X64_GUEST_IDLE_STATE_AVAILABLE (1 << 5) 128 /* Guest crash data handler available */ 129 #define HV_X64_GUEST_CRASH_MSR_AVAILABLE (1 << 10) 130 131 /* 132 * Implementation recommendations. Indicates which behaviors the hypervisor 133 * recommends the OS implement for optimal performance. 134 */ 135 /* 136 * Recommend using hypercall for address space switches rather 137 * than MOV to CR3 instruction 138 */ 139 #define HV_X64_AS_SWITCH_RECOMMENDED (1 << 0) 140 /* Recommend using hypercall for local TLB flushes rather 141 * than INVLPG or MOV to CR3 instructions */ 142 #define HV_X64_LOCAL_TLB_FLUSH_RECOMMENDED (1 << 1) 143 /* 144 * Recommend using hypercall for remote TLB flushes rather 145 * than inter-processor interrupts 146 */ 147 #define HV_X64_REMOTE_TLB_FLUSH_RECOMMENDED (1 << 2) 148 /* 149 * Recommend using MSRs for accessing APIC registers 150 * EOI, ICR and TPR rather than their memory-mapped counterparts 151 */ 152 #define HV_X64_APIC_ACCESS_RECOMMENDED (1 << 3) 153 /* Recommend using the hypervisor-provided MSR to initiate a system RESET */ 154 #define HV_X64_SYSTEM_RESET_RECOMMENDED (1 << 4) 155 /* 156 * Recommend using relaxed timing for this partition. If used, 157 * the VM should disable any watchdog timeouts that rely on the 158 * timely delivery of external interrupts 159 */ 160 #define HV_X64_RELAXED_TIMING_RECOMMENDED (1 << 5) 161 162 /* 163 * Virtual APIC support 164 */ 165 #define HV_X64_DEPRECATING_AEOI_RECOMMENDED (1 << 9) 166 167 /* 168 * Recommend using cluster IPI hypercalls. 169 */ 170 #define HV_X64_CLUSTER_IPI_RECOMMENDED (1 << 10) 171 172 /* Recommend using the newer ExProcessorMasks interface */ 173 #define HV_X64_EX_PROCESSOR_MASKS_RECOMMENDED (1 << 11) 174 175 /* Recommend using enlightened VMCS */ 176 #define HV_X64_ENLIGHTENED_VMCS_RECOMMENDED (1 << 14) 177 178 /* 179 * Crash notification flag. 180 */ 181 #define HV_CRASH_CTL_CRASH_NOTIFY (1ULL << 63) 182 183 /* MSR used to identify the guest OS. */ 184 #define HV_X64_MSR_GUEST_OS_ID 0x40000000 185 186 /* MSR used to setup pages used to communicate with the hypervisor. */ 187 #define HV_X64_MSR_HYPERCALL 0x40000001 188 189 /* MSR used to provide vcpu index */ 190 #define HV_X64_MSR_VP_INDEX 0x40000002 191 192 /* MSR used to reset the guest OS. */ 193 #define HV_X64_MSR_RESET 0x40000003 194 195 /* MSR used to provide vcpu runtime in 100ns units */ 196 #define HV_X64_MSR_VP_RUNTIME 0x40000010 197 198 /* MSR used to read the per-partition time reference counter */ 199 #define HV_X64_MSR_TIME_REF_COUNT 0x40000020 200 201 /* MSR used to retrieve the TSC frequency */ 202 #define HV_X64_MSR_TSC_FREQUENCY 0x40000022 203 204 /* MSR used to retrieve the local APIC timer frequency */ 205 #define HV_X64_MSR_APIC_FREQUENCY 0x40000023 206 207 /* Define the virtual APIC registers */ 208 #define HV_X64_MSR_EOI 0x40000070 209 #define HV_X64_MSR_ICR 0x40000071 210 #define HV_X64_MSR_TPR 0x40000072 211 #define HV_X64_MSR_VP_ASSIST_PAGE 0x40000073 212 213 /* Define synthetic interrupt controller model specific registers. */ 214 #define HV_X64_MSR_SCONTROL 0x40000080 215 #define HV_X64_MSR_SVERSION 0x40000081 216 #define HV_X64_MSR_SIEFP 0x40000082 217 #define HV_X64_MSR_SIMP 0x40000083 218 #define HV_X64_MSR_EOM 0x40000084 219 #define HV_X64_MSR_SINT0 0x40000090 220 #define HV_X64_MSR_SINT1 0x40000091 221 #define HV_X64_MSR_SINT2 0x40000092 222 #define HV_X64_MSR_SINT3 0x40000093 223 #define HV_X64_MSR_SINT4 0x40000094 224 #define HV_X64_MSR_SINT5 0x40000095 225 #define HV_X64_MSR_SINT6 0x40000096 226 #define HV_X64_MSR_SINT7 0x40000097 227 #define HV_X64_MSR_SINT8 0x40000098 228 #define HV_X64_MSR_SINT9 0x40000099 229 #define HV_X64_MSR_SINT10 0x4000009A 230 #define HV_X64_MSR_SINT11 0x4000009B 231 #define HV_X64_MSR_SINT12 0x4000009C 232 #define HV_X64_MSR_SINT13 0x4000009D 233 #define HV_X64_MSR_SINT14 0x4000009E 234 #define HV_X64_MSR_SINT15 0x4000009F 235 236 /* 237 * Synthetic Timer MSRs. Four timers per vcpu. 238 */ 239 #define HV_X64_MSR_STIMER0_CONFIG 0x400000B0 240 #define HV_X64_MSR_STIMER0_COUNT 0x400000B1 241 #define HV_X64_MSR_STIMER1_CONFIG 0x400000B2 242 #define HV_X64_MSR_STIMER1_COUNT 0x400000B3 243 #define HV_X64_MSR_STIMER2_CONFIG 0x400000B4 244 #define HV_X64_MSR_STIMER2_COUNT 0x400000B5 245 #define HV_X64_MSR_STIMER3_CONFIG 0x400000B6 246 #define HV_X64_MSR_STIMER3_COUNT 0x400000B7 247 248 /* Hyper-V guest crash notification MSR's */ 249 #define HV_X64_MSR_CRASH_P0 0x40000100 250 #define HV_X64_MSR_CRASH_P1 0x40000101 251 #define HV_X64_MSR_CRASH_P2 0x40000102 252 #define HV_X64_MSR_CRASH_P3 0x40000103 253 #define HV_X64_MSR_CRASH_P4 0x40000104 254 #define HV_X64_MSR_CRASH_CTL 0x40000105 255 #define HV_X64_MSR_CRASH_CTL_NOTIFY (1ULL << 63) 256 #define HV_X64_MSR_CRASH_PARAMS \ 257 (1 + (HV_X64_MSR_CRASH_P4 - HV_X64_MSR_CRASH_P0)) 258 259 /* 260 * Declare the MSR used to setup pages used to communicate with the hypervisor. 261 */ 262 union hv_x64_msr_hypercall_contents { 263 u64 as_uint64; 264 struct { 265 u64 enable:1; 266 u64 reserved:11; 267 u64 guest_physical_address:52; 268 }; 269 }; 270 271 /* 272 * TSC page layout. 273 */ 274 struct ms_hyperv_tsc_page { 275 volatile u32 tsc_sequence; 276 u32 reserved1; 277 volatile u64 tsc_scale; 278 volatile s64 tsc_offset; 279 u64 reserved2[509]; 280 }; 281 282 /* 283 * The guest OS needs to register the guest ID with the hypervisor. 284 * The guest ID is a 64 bit entity and the structure of this ID is 285 * specified in the Hyper-V specification: 286 * 287 * msdn.microsoft.com/en-us/library/windows/hardware/ff542653%28v=vs.85%29.aspx 288 * 289 * While the current guideline does not specify how Linux guest ID(s) 290 * need to be generated, our plan is to publish the guidelines for 291 * Linux and other guest operating systems that currently are hosted 292 * on Hyper-V. The implementation here conforms to this yet 293 * unpublished guidelines. 294 * 295 * 296 * Bit(s) 297 * 63 - Indicates if the OS is Open Source or not; 1 is Open Source 298 * 62:56 - Os Type; Linux is 0x100 299 * 55:48 - Distro specific identification 300 * 47:16 - Linux kernel version number 301 * 15:0 - Distro specific identification 302 * 303 * 304 */ 305 306 #define HV_LINUX_VENDOR_ID 0x8100 307 308 /* TSC emulation after migration */ 309 #define HV_X64_MSR_REENLIGHTENMENT_CONTROL 0x40000106 310 311 struct hv_reenlightenment_control { 312 __u64 vector:8; 313 __u64 reserved1:8; 314 __u64 enabled:1; 315 __u64 reserved2:15; 316 __u64 target_vp:32; 317 }; 318 319 #define HV_X64_MSR_TSC_EMULATION_CONTROL 0x40000107 320 #define HV_X64_MSR_TSC_EMULATION_STATUS 0x40000108 321 322 struct hv_tsc_emulation_control { 323 __u64 enabled:1; 324 __u64 reserved:63; 325 }; 326 327 struct hv_tsc_emulation_status { 328 __u64 inprogress:1; 329 __u64 reserved:63; 330 }; 331 332 #define HV_X64_MSR_HYPERCALL_ENABLE 0x00000001 333 #define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT 12 334 #define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_MASK \ 335 (~((1ull << HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT) - 1)) 336 337 #define HV_IPI_LOW_VECTOR 0x10 338 #define HV_IPI_HIGH_VECTOR 0xff 339 340 /* Declare the various hypercall operations. */ 341 #define HVCALL_FLUSH_VIRTUAL_ADDRESS_SPACE 0x0002 342 #define HVCALL_FLUSH_VIRTUAL_ADDRESS_LIST 0x0003 343 #define HVCALL_NOTIFY_LONG_SPIN_WAIT 0x0008 344 #define HVCALL_SEND_IPI 0x000b 345 #define HVCALL_FLUSH_VIRTUAL_ADDRESS_SPACE_EX 0x0013 346 #define HVCALL_FLUSH_VIRTUAL_ADDRESS_LIST_EX 0x0014 347 #define HVCALL_SEND_IPI_EX 0x0015 348 #define HVCALL_POST_MESSAGE 0x005c 349 #define HVCALL_SIGNAL_EVENT 0x005d 350 351 #define HV_X64_MSR_VP_ASSIST_PAGE_ENABLE 0x00000001 352 #define HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_SHIFT 12 353 #define HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_MASK \ 354 (~((1ull << HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_SHIFT) - 1)) 355 356 /* Hyper-V Enlightened VMCS version mask in nested features CPUID */ 357 #define HV_X64_ENLIGHTENED_VMCS_VERSION 0xff 358 359 #define HV_X64_MSR_TSC_REFERENCE_ENABLE 0x00000001 360 #define HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT 12 361 362 #define HV_PROCESSOR_POWER_STATE_C0 0 363 #define HV_PROCESSOR_POWER_STATE_C1 1 364 #define HV_PROCESSOR_POWER_STATE_C2 2 365 #define HV_PROCESSOR_POWER_STATE_C3 3 366 367 #define HV_FLUSH_ALL_PROCESSORS BIT(0) 368 #define HV_FLUSH_ALL_VIRTUAL_ADDRESS_SPACES BIT(1) 369 #define HV_FLUSH_NON_GLOBAL_MAPPINGS_ONLY BIT(2) 370 #define HV_FLUSH_USE_EXTENDED_RANGE_FORMAT BIT(3) 371 372 enum HV_GENERIC_SET_FORMAT { 373 HV_GENERIC_SET_SPARSE_4K, 374 HV_GENERIC_SET_ALL, 375 }; 376 377 #define HV_HYPERCALL_RESULT_MASK GENMASK_ULL(15, 0) 378 #define HV_HYPERCALL_FAST_BIT BIT(16) 379 #define HV_HYPERCALL_VARHEAD_OFFSET 17 380 #define HV_HYPERCALL_REP_COMP_OFFSET 32 381 #define HV_HYPERCALL_REP_COMP_MASK GENMASK_ULL(43, 32) 382 #define HV_HYPERCALL_REP_START_OFFSET 48 383 #define HV_HYPERCALL_REP_START_MASK GENMASK_ULL(59, 48) 384 385 /* hypercall status code */ 386 #define HV_STATUS_SUCCESS 0 387 #define HV_STATUS_INVALID_HYPERCALL_CODE 2 388 #define HV_STATUS_INVALID_HYPERCALL_INPUT 3 389 #define HV_STATUS_INVALID_ALIGNMENT 4 390 #define HV_STATUS_INVALID_PARAMETER 5 391 #define HV_STATUS_INSUFFICIENT_MEMORY 11 392 #define HV_STATUS_INVALID_PORT_ID 17 393 #define HV_STATUS_INVALID_CONNECTION_ID 18 394 #define HV_STATUS_INSUFFICIENT_BUFFERS 19 395 396 typedef struct _HV_REFERENCE_TSC_PAGE { 397 __u32 tsc_sequence; 398 __u32 res1; 399 __u64 tsc_scale; 400 __s64 tsc_offset; 401 } HV_REFERENCE_TSC_PAGE, *PHV_REFERENCE_TSC_PAGE; 402 403 /* Define the number of synthetic interrupt sources. */ 404 #define HV_SYNIC_SINT_COUNT (16) 405 /* Define the expected SynIC version. */ 406 #define HV_SYNIC_VERSION_1 (0x1) 407 /* Valid SynIC vectors are 16-255. */ 408 #define HV_SYNIC_FIRST_VALID_VECTOR (16) 409 410 #define HV_SYNIC_CONTROL_ENABLE (1ULL << 0) 411 #define HV_SYNIC_SIMP_ENABLE (1ULL << 0) 412 #define HV_SYNIC_SIEFP_ENABLE (1ULL << 0) 413 #define HV_SYNIC_SINT_MASKED (1ULL << 16) 414 #define HV_SYNIC_SINT_AUTO_EOI (1ULL << 17) 415 #define HV_SYNIC_SINT_VECTOR_MASK (0xFF) 416 417 #define HV_SYNIC_STIMER_COUNT (4) 418 419 /* Define synthetic interrupt controller message constants. */ 420 #define HV_MESSAGE_SIZE (256) 421 #define HV_MESSAGE_PAYLOAD_BYTE_COUNT (240) 422 #define HV_MESSAGE_PAYLOAD_QWORD_COUNT (30) 423 424 /* Define hypervisor message types. */ 425 enum hv_message_type { 426 HVMSG_NONE = 0x00000000, 427 428 /* Memory access messages. */ 429 HVMSG_UNMAPPED_GPA = 0x80000000, 430 HVMSG_GPA_INTERCEPT = 0x80000001, 431 432 /* Timer notification messages. */ 433 HVMSG_TIMER_EXPIRED = 0x80000010, 434 435 /* Error messages. */ 436 HVMSG_INVALID_VP_REGISTER_VALUE = 0x80000020, 437 HVMSG_UNRECOVERABLE_EXCEPTION = 0x80000021, 438 HVMSG_UNSUPPORTED_FEATURE = 0x80000022, 439 440 /* Trace buffer complete messages. */ 441 HVMSG_EVENTLOG_BUFFERCOMPLETE = 0x80000040, 442 443 /* Platform-specific processor intercept messages. */ 444 HVMSG_X64_IOPORT_INTERCEPT = 0x80010000, 445 HVMSG_X64_MSR_INTERCEPT = 0x80010001, 446 HVMSG_X64_CPUID_INTERCEPT = 0x80010002, 447 HVMSG_X64_EXCEPTION_INTERCEPT = 0x80010003, 448 HVMSG_X64_APIC_EOI = 0x80010004, 449 HVMSG_X64_LEGACY_FP_ERROR = 0x80010005 450 }; 451 452 /* Define synthetic interrupt controller message flags. */ 453 union hv_message_flags { 454 __u8 asu8; 455 struct { 456 __u8 msg_pending:1; 457 __u8 reserved:7; 458 }; 459 }; 460 461 /* Define port identifier type. */ 462 union hv_port_id { 463 __u32 asu32; 464 struct { 465 __u32 id:24; 466 __u32 reserved:8; 467 } u; 468 }; 469 470 /* Define synthetic interrupt controller message header. */ 471 struct hv_message_header { 472 __u32 message_type; 473 __u8 payload_size; 474 union hv_message_flags message_flags; 475 __u8 reserved[2]; 476 union { 477 __u64 sender; 478 union hv_port_id port; 479 }; 480 }; 481 482 /* Define synthetic interrupt controller message format. */ 483 struct hv_message { 484 struct hv_message_header header; 485 union { 486 __u64 payload[HV_MESSAGE_PAYLOAD_QWORD_COUNT]; 487 } u; 488 }; 489 490 /* Define the synthetic interrupt message page layout. */ 491 struct hv_message_page { 492 struct hv_message sint_message[HV_SYNIC_SINT_COUNT]; 493 }; 494 495 /* Define timer message payload structure. */ 496 struct hv_timer_message_payload { 497 __u32 timer_index; 498 __u32 reserved; 499 __u64 expiration_time; /* When the timer expired */ 500 __u64 delivery_time; /* When the message was delivered */ 501 }; 502 503 /* Define virtual processor assist page structure. */ 504 struct hv_vp_assist_page { 505 __u32 apic_assist; 506 __u32 reserved; 507 __u64 vtl_control[2]; 508 __u64 nested_enlightenments_control[2]; 509 __u32 enlighten_vmentry; 510 __u64 current_nested_vmcs; 511 }; 512 513 struct hv_enlightened_vmcs { 514 u32 revision_id; 515 u32 abort; 516 517 u16 host_es_selector; 518 u16 host_cs_selector; 519 u16 host_ss_selector; 520 u16 host_ds_selector; 521 u16 host_fs_selector; 522 u16 host_gs_selector; 523 u16 host_tr_selector; 524 525 u64 host_ia32_pat; 526 u64 host_ia32_efer; 527 528 u64 host_cr0; 529 u64 host_cr3; 530 u64 host_cr4; 531 532 u64 host_ia32_sysenter_esp; 533 u64 host_ia32_sysenter_eip; 534 u64 host_rip; 535 u32 host_ia32_sysenter_cs; 536 537 u32 pin_based_vm_exec_control; 538 u32 vm_exit_controls; 539 u32 secondary_vm_exec_control; 540 541 u64 io_bitmap_a; 542 u64 io_bitmap_b; 543 u64 msr_bitmap; 544 545 u16 guest_es_selector; 546 u16 guest_cs_selector; 547 u16 guest_ss_selector; 548 u16 guest_ds_selector; 549 u16 guest_fs_selector; 550 u16 guest_gs_selector; 551 u16 guest_ldtr_selector; 552 u16 guest_tr_selector; 553 554 u32 guest_es_limit; 555 u32 guest_cs_limit; 556 u32 guest_ss_limit; 557 u32 guest_ds_limit; 558 u32 guest_fs_limit; 559 u32 guest_gs_limit; 560 u32 guest_ldtr_limit; 561 u32 guest_tr_limit; 562 u32 guest_gdtr_limit; 563 u32 guest_idtr_limit; 564 565 u32 guest_es_ar_bytes; 566 u32 guest_cs_ar_bytes; 567 u32 guest_ss_ar_bytes; 568 u32 guest_ds_ar_bytes; 569 u32 guest_fs_ar_bytes; 570 u32 guest_gs_ar_bytes; 571 u32 guest_ldtr_ar_bytes; 572 u32 guest_tr_ar_bytes; 573 574 u64 guest_es_base; 575 u64 guest_cs_base; 576 u64 guest_ss_base; 577 u64 guest_ds_base; 578 u64 guest_fs_base; 579 u64 guest_gs_base; 580 u64 guest_ldtr_base; 581 u64 guest_tr_base; 582 u64 guest_gdtr_base; 583 u64 guest_idtr_base; 584 585 u64 padding64_1[3]; 586 587 u64 vm_exit_msr_store_addr; 588 u64 vm_exit_msr_load_addr; 589 u64 vm_entry_msr_load_addr; 590 591 u64 cr3_target_value0; 592 u64 cr3_target_value1; 593 u64 cr3_target_value2; 594 u64 cr3_target_value3; 595 596 u32 page_fault_error_code_mask; 597 u32 page_fault_error_code_match; 598 599 u32 cr3_target_count; 600 u32 vm_exit_msr_store_count; 601 u32 vm_exit_msr_load_count; 602 u32 vm_entry_msr_load_count; 603 604 u64 tsc_offset; 605 u64 virtual_apic_page_addr; 606 u64 vmcs_link_pointer; 607 608 u64 guest_ia32_debugctl; 609 u64 guest_ia32_pat; 610 u64 guest_ia32_efer; 611 612 u64 guest_pdptr0; 613 u64 guest_pdptr1; 614 u64 guest_pdptr2; 615 u64 guest_pdptr3; 616 617 u64 guest_pending_dbg_exceptions; 618 u64 guest_sysenter_esp; 619 u64 guest_sysenter_eip; 620 621 u32 guest_activity_state; 622 u32 guest_sysenter_cs; 623 624 u64 cr0_guest_host_mask; 625 u64 cr4_guest_host_mask; 626 u64 cr0_read_shadow; 627 u64 cr4_read_shadow; 628 u64 guest_cr0; 629 u64 guest_cr3; 630 u64 guest_cr4; 631 u64 guest_dr7; 632 633 u64 host_fs_base; 634 u64 host_gs_base; 635 u64 host_tr_base; 636 u64 host_gdtr_base; 637 u64 host_idtr_base; 638 u64 host_rsp; 639 640 u64 ept_pointer; 641 642 u16 virtual_processor_id; 643 u16 padding16[3]; 644 645 u64 padding64_2[5]; 646 u64 guest_physical_address; 647 648 u32 vm_instruction_error; 649 u32 vm_exit_reason; 650 u32 vm_exit_intr_info; 651 u32 vm_exit_intr_error_code; 652 u32 idt_vectoring_info_field; 653 u32 idt_vectoring_error_code; 654 u32 vm_exit_instruction_len; 655 u32 vmx_instruction_info; 656 657 u64 exit_qualification; 658 u64 exit_io_instruction_ecx; 659 u64 exit_io_instruction_esi; 660 u64 exit_io_instruction_edi; 661 u64 exit_io_instruction_eip; 662 663 u64 guest_linear_address; 664 u64 guest_rsp; 665 u64 guest_rflags; 666 667 u32 guest_interruptibility_info; 668 u32 cpu_based_vm_exec_control; 669 u32 exception_bitmap; 670 u32 vm_entry_controls; 671 u32 vm_entry_intr_info_field; 672 u32 vm_entry_exception_error_code; 673 u32 vm_entry_instruction_len; 674 u32 tpr_threshold; 675 676 u64 guest_rip; 677 678 u32 hv_clean_fields; 679 u32 hv_padding_32; 680 u32 hv_synthetic_controls; 681 u32 hv_enlightenments_control; 682 u32 hv_vp_id; 683 684 u64 hv_vm_id; 685 u64 partition_assist_page; 686 u64 padding64_4[4]; 687 u64 guest_bndcfgs; 688 u64 padding64_5[7]; 689 u64 xss_exit_bitmap; 690 u64 padding64_6[7]; 691 }; 692 693 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_NONE 0 694 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_IO_BITMAP BIT(0) 695 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_MSR_BITMAP BIT(1) 696 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_GRP2 BIT(2) 697 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_GRP1 BIT(3) 698 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_PROC BIT(4) 699 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_EVENT BIT(5) 700 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_ENTRY BIT(6) 701 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_EXCPN BIT(7) 702 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CRDR BIT(8) 703 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_XLAT BIT(9) 704 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_BASIC BIT(10) 705 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_GRP1 BIT(11) 706 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_GRP2 BIT(12) 707 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_HOST_POINTER BIT(13) 708 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_HOST_GRP1 BIT(14) 709 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_ENLIGHTENMENTSCONTROL BIT(15) 710 711 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL 0xFFFF 712 713 #define HV_STIMER_ENABLE (1ULL << 0) 714 #define HV_STIMER_PERIODIC (1ULL << 1) 715 #define HV_STIMER_LAZY (1ULL << 2) 716 #define HV_STIMER_AUTOENABLE (1ULL << 3) 717 #define HV_STIMER_SINT(config) (__u8)(((config) >> 16) & 0x0F) 718 719 struct ipi_arg_non_ex { 720 u32 vector; 721 u32 reserved; 722 u64 cpu_mask; 723 }; 724 725 struct hv_vpset { 726 u64 format; 727 u64 valid_bank_mask; 728 u64 bank_contents[]; 729 }; 730 731 struct ipi_arg_ex { 732 u32 vector; 733 u32 reserved; 734 struct hv_vpset vp_set; 735 }; 736 737 #endif 738