1 /* SPDX-License-Identifier: GPL-2.0 */ 2 3 /* 4 * This file contains definitions from Hyper-V Hypervisor Top-Level Functional 5 * Specification (TLFS): 6 * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs 7 */ 8 9 #ifndef _ASM_X86_HYPERV_TLFS_H 10 #define _ASM_X86_HYPERV_TLFS_H 11 12 #include <linux/types.h> 13 #include <asm/page.h> 14 /* 15 * The below CPUID leaves are present if VersionAndFeatures.HypervisorPresent 16 * is set by CPUID(HvCpuIdFunctionVersionAndFeatures). 17 */ 18 #define HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS 0x40000000 19 #define HYPERV_CPUID_INTERFACE 0x40000001 20 #define HYPERV_CPUID_VERSION 0x40000002 21 #define HYPERV_CPUID_FEATURES 0x40000003 22 #define HYPERV_CPUID_ENLIGHTMENT_INFO 0x40000004 23 #define HYPERV_CPUID_IMPLEMENT_LIMITS 0x40000005 24 #define HYPERV_CPUID_CPU_MANAGEMENT_FEATURES 0x40000007 25 #define HYPERV_CPUID_NESTED_FEATURES 0x4000000A 26 #define HYPERV_CPUID_ISOLATION_CONFIG 0x4000000C 27 28 #define HYPERV_CPUID_VIRT_STACK_INTERFACE 0x40000081 29 #define HYPERV_VS_INTERFACE_EAX_SIGNATURE 0x31235356 /* "VS#1" */ 30 31 #define HYPERV_CPUID_VIRT_STACK_PROPERTIES 0x40000082 32 /* Support for the extended IOAPIC RTE format */ 33 #define HYPERV_VS_PROPERTIES_EAX_EXTENDED_IOAPIC_RTE BIT(2) 34 35 #define HYPERV_HYPERVISOR_PRESENT_BIT 0x80000000 36 #define HYPERV_CPUID_MIN 0x40000005 37 #define HYPERV_CPUID_MAX 0x4000ffff 38 39 /* 40 * Group D Features. The bit assignments are custom to each architecture. 41 * On x86/x64 these are HYPERV_CPUID_FEATURES.EDX bits. 42 */ 43 /* The MWAIT instruction is available (per section MONITOR / MWAIT) */ 44 #define HV_X64_MWAIT_AVAILABLE BIT(0) 45 /* Guest debugging support is available */ 46 #define HV_X64_GUEST_DEBUGGING_AVAILABLE BIT(1) 47 /* Performance Monitor support is available*/ 48 #define HV_X64_PERF_MONITOR_AVAILABLE BIT(2) 49 /* Support for physical CPU dynamic partitioning events is available*/ 50 #define HV_X64_CPU_DYNAMIC_PARTITIONING_AVAILABLE BIT(3) 51 /* 52 * Support for passing hypercall input parameter block via XMM 53 * registers is available 54 */ 55 #define HV_X64_HYPERCALL_XMM_INPUT_AVAILABLE BIT(4) 56 /* Support for a virtual guest idle state is available */ 57 #define HV_X64_GUEST_IDLE_STATE_AVAILABLE BIT(5) 58 /* Frequency MSRs available */ 59 #define HV_FEATURE_FREQUENCY_MSRS_AVAILABLE BIT(8) 60 /* Crash MSR available */ 61 #define HV_FEATURE_GUEST_CRASH_MSR_AVAILABLE BIT(10) 62 /* Support for debug MSRs available */ 63 #define HV_FEATURE_DEBUG_MSRS_AVAILABLE BIT(11) 64 /* Support for extended gva ranges for flush hypercalls available */ 65 #define HV_FEATURE_EXT_GVA_RANGES_FLUSH BIT(14) 66 /* 67 * Support for returning hypercall output block via XMM 68 * registers is available 69 */ 70 #define HV_X64_HYPERCALL_XMM_OUTPUT_AVAILABLE BIT(15) 71 /* stimer Direct Mode is available */ 72 #define HV_STIMER_DIRECT_MODE_AVAILABLE BIT(19) 73 74 /* 75 * Implementation recommendations. Indicates which behaviors the hypervisor 76 * recommends the OS implement for optimal performance. 77 * These are HYPERV_CPUID_ENLIGHTMENT_INFO.EAX bits. 78 */ 79 /* 80 * Recommend using hypercall for address space switches rather 81 * than MOV to CR3 instruction 82 */ 83 #define HV_X64_AS_SWITCH_RECOMMENDED BIT(0) 84 /* Recommend using hypercall for local TLB flushes rather 85 * than INVLPG or MOV to CR3 instructions */ 86 #define HV_X64_LOCAL_TLB_FLUSH_RECOMMENDED BIT(1) 87 /* 88 * Recommend using hypercall for remote TLB flushes rather 89 * than inter-processor interrupts 90 */ 91 #define HV_X64_REMOTE_TLB_FLUSH_RECOMMENDED BIT(2) 92 /* 93 * Recommend using MSRs for accessing APIC registers 94 * EOI, ICR and TPR rather than their memory-mapped counterparts 95 */ 96 #define HV_X64_APIC_ACCESS_RECOMMENDED BIT(3) 97 /* Recommend using the hypervisor-provided MSR to initiate a system RESET */ 98 #define HV_X64_SYSTEM_RESET_RECOMMENDED BIT(4) 99 /* 100 * Recommend using relaxed timing for this partition. If used, 101 * the VM should disable any watchdog timeouts that rely on the 102 * timely delivery of external interrupts 103 */ 104 #define HV_X64_RELAXED_TIMING_RECOMMENDED BIT(5) 105 106 /* 107 * Recommend not using Auto End-Of-Interrupt feature 108 */ 109 #define HV_DEPRECATING_AEOI_RECOMMENDED BIT(9) 110 111 /* 112 * Recommend using cluster IPI hypercalls. 113 */ 114 #define HV_X64_CLUSTER_IPI_RECOMMENDED BIT(10) 115 116 /* Recommend using the newer ExProcessorMasks interface */ 117 #define HV_X64_EX_PROCESSOR_MASKS_RECOMMENDED BIT(11) 118 119 /* Recommend using enlightened VMCS */ 120 #define HV_X64_ENLIGHTENED_VMCS_RECOMMENDED BIT(14) 121 122 /* 123 * CPU management features identification. 124 * These are HYPERV_CPUID_CPU_MANAGEMENT_FEATURES.EAX bits. 125 */ 126 #define HV_X64_START_LOGICAL_PROCESSOR BIT(0) 127 #define HV_X64_CREATE_ROOT_VIRTUAL_PROCESSOR BIT(1) 128 #define HV_X64_PERFORMANCE_COUNTER_SYNC BIT(2) 129 #define HV_X64_RESERVED_IDENTITY_BIT BIT(31) 130 131 /* 132 * Virtual processor will never share a physical core with another virtual 133 * processor, except for virtual processors that are reported as sibling SMT 134 * threads. 135 */ 136 #define HV_X64_NO_NONARCH_CORESHARING BIT(18) 137 138 /* Nested features. These are HYPERV_CPUID_NESTED_FEATURES.EAX bits. */ 139 #define HV_X64_NESTED_DIRECT_FLUSH BIT(17) 140 #define HV_X64_NESTED_GUEST_MAPPING_FLUSH BIT(18) 141 #define HV_X64_NESTED_MSR_BITMAP BIT(19) 142 143 /* Nested features #2. These are HYPERV_CPUID_NESTED_FEATURES.EBX bits. */ 144 #define HV_X64_NESTED_EVMCS1_PERF_GLOBAL_CTRL BIT(0) 145 146 /* 147 * This is specific to AMD and specifies that enlightened TLB flush is 148 * supported. If guest opts in to this feature, ASID invalidations only 149 * flushes gva -> hpa mapping entries. To flush the TLB entries derived 150 * from NPT, hypercalls should be used (HvFlushGuestPhysicalAddressSpace 151 * or HvFlushGuestPhysicalAddressList). 152 */ 153 #define HV_X64_NESTED_ENLIGHTENED_TLB BIT(22) 154 155 /* HYPERV_CPUID_ISOLATION_CONFIG.EAX bits. */ 156 #define HV_PARAVISOR_PRESENT BIT(0) 157 158 /* HYPERV_CPUID_ISOLATION_CONFIG.EBX bits. */ 159 #define HV_ISOLATION_TYPE GENMASK(3, 0) 160 #define HV_SHARED_GPA_BOUNDARY_ACTIVE BIT(5) 161 #define HV_SHARED_GPA_BOUNDARY_BITS GENMASK(11, 6) 162 163 enum hv_isolation_type { 164 HV_ISOLATION_TYPE_NONE = 0, 165 HV_ISOLATION_TYPE_VBS = 1, 166 HV_ISOLATION_TYPE_SNP = 2 167 }; 168 169 /* Hyper-V specific model specific registers (MSRs) */ 170 171 /* MSR used to identify the guest OS. */ 172 #define HV_X64_MSR_GUEST_OS_ID 0x40000000 173 174 /* MSR used to setup pages used to communicate with the hypervisor. */ 175 #define HV_X64_MSR_HYPERCALL 0x40000001 176 177 /* MSR used to provide vcpu index */ 178 #define HV_REGISTER_VP_INDEX 0x40000002 179 180 /* MSR used to reset the guest OS. */ 181 #define HV_X64_MSR_RESET 0x40000003 182 183 /* MSR used to provide vcpu runtime in 100ns units */ 184 #define HV_X64_MSR_VP_RUNTIME 0x40000010 185 186 /* MSR used to read the per-partition time reference counter */ 187 #define HV_REGISTER_TIME_REF_COUNT 0x40000020 188 189 /* A partition's reference time stamp counter (TSC) page */ 190 #define HV_REGISTER_REFERENCE_TSC 0x40000021 191 192 /* MSR used to retrieve the TSC frequency */ 193 #define HV_X64_MSR_TSC_FREQUENCY 0x40000022 194 195 /* MSR used to retrieve the local APIC timer frequency */ 196 #define HV_X64_MSR_APIC_FREQUENCY 0x40000023 197 198 /* Define the virtual APIC registers */ 199 #define HV_X64_MSR_EOI 0x40000070 200 #define HV_X64_MSR_ICR 0x40000071 201 #define HV_X64_MSR_TPR 0x40000072 202 #define HV_X64_MSR_VP_ASSIST_PAGE 0x40000073 203 204 /* Define synthetic interrupt controller model specific registers. */ 205 #define HV_REGISTER_SCONTROL 0x40000080 206 #define HV_REGISTER_SVERSION 0x40000081 207 #define HV_REGISTER_SIEFP 0x40000082 208 #define HV_REGISTER_SIMP 0x40000083 209 #define HV_REGISTER_EOM 0x40000084 210 #define HV_REGISTER_SINT0 0x40000090 211 #define HV_REGISTER_SINT1 0x40000091 212 #define HV_REGISTER_SINT2 0x40000092 213 #define HV_REGISTER_SINT3 0x40000093 214 #define HV_REGISTER_SINT4 0x40000094 215 #define HV_REGISTER_SINT5 0x40000095 216 #define HV_REGISTER_SINT6 0x40000096 217 #define HV_REGISTER_SINT7 0x40000097 218 #define HV_REGISTER_SINT8 0x40000098 219 #define HV_REGISTER_SINT9 0x40000099 220 #define HV_REGISTER_SINT10 0x4000009A 221 #define HV_REGISTER_SINT11 0x4000009B 222 #define HV_REGISTER_SINT12 0x4000009C 223 #define HV_REGISTER_SINT13 0x4000009D 224 #define HV_REGISTER_SINT14 0x4000009E 225 #define HV_REGISTER_SINT15 0x4000009F 226 227 /* 228 * Synthetic Timer MSRs. Four timers per vcpu. 229 */ 230 #define HV_REGISTER_STIMER0_CONFIG 0x400000B0 231 #define HV_REGISTER_STIMER0_COUNT 0x400000B1 232 #define HV_REGISTER_STIMER1_CONFIG 0x400000B2 233 #define HV_REGISTER_STIMER1_COUNT 0x400000B3 234 #define HV_REGISTER_STIMER2_CONFIG 0x400000B4 235 #define HV_REGISTER_STIMER2_COUNT 0x400000B5 236 #define HV_REGISTER_STIMER3_CONFIG 0x400000B6 237 #define HV_REGISTER_STIMER3_COUNT 0x400000B7 238 239 /* Hyper-V guest idle MSR */ 240 #define HV_X64_MSR_GUEST_IDLE 0x400000F0 241 242 /* Hyper-V guest crash notification MSR's */ 243 #define HV_REGISTER_CRASH_P0 0x40000100 244 #define HV_REGISTER_CRASH_P1 0x40000101 245 #define HV_REGISTER_CRASH_P2 0x40000102 246 #define HV_REGISTER_CRASH_P3 0x40000103 247 #define HV_REGISTER_CRASH_P4 0x40000104 248 #define HV_REGISTER_CRASH_CTL 0x40000105 249 250 /* TSC emulation after migration */ 251 #define HV_X64_MSR_REENLIGHTENMENT_CONTROL 0x40000106 252 #define HV_X64_MSR_TSC_EMULATION_CONTROL 0x40000107 253 #define HV_X64_MSR_TSC_EMULATION_STATUS 0x40000108 254 255 /* TSC invariant control */ 256 #define HV_X64_MSR_TSC_INVARIANT_CONTROL 0x40000118 257 258 /* Register name aliases for temporary compatibility */ 259 #define HV_X64_MSR_STIMER0_COUNT HV_REGISTER_STIMER0_COUNT 260 #define HV_X64_MSR_STIMER0_CONFIG HV_REGISTER_STIMER0_CONFIG 261 #define HV_X64_MSR_STIMER1_COUNT HV_REGISTER_STIMER1_COUNT 262 #define HV_X64_MSR_STIMER1_CONFIG HV_REGISTER_STIMER1_CONFIG 263 #define HV_X64_MSR_STIMER2_COUNT HV_REGISTER_STIMER2_COUNT 264 #define HV_X64_MSR_STIMER2_CONFIG HV_REGISTER_STIMER2_CONFIG 265 #define HV_X64_MSR_STIMER3_COUNT HV_REGISTER_STIMER3_COUNT 266 #define HV_X64_MSR_STIMER3_CONFIG HV_REGISTER_STIMER3_CONFIG 267 #define HV_X64_MSR_SCONTROL HV_REGISTER_SCONTROL 268 #define HV_X64_MSR_SVERSION HV_REGISTER_SVERSION 269 #define HV_X64_MSR_SIMP HV_REGISTER_SIMP 270 #define HV_X64_MSR_SIEFP HV_REGISTER_SIEFP 271 #define HV_X64_MSR_VP_INDEX HV_REGISTER_VP_INDEX 272 #define HV_X64_MSR_EOM HV_REGISTER_EOM 273 #define HV_X64_MSR_SINT0 HV_REGISTER_SINT0 274 #define HV_X64_MSR_SINT15 HV_REGISTER_SINT15 275 #define HV_X64_MSR_CRASH_P0 HV_REGISTER_CRASH_P0 276 #define HV_X64_MSR_CRASH_P1 HV_REGISTER_CRASH_P1 277 #define HV_X64_MSR_CRASH_P2 HV_REGISTER_CRASH_P2 278 #define HV_X64_MSR_CRASH_P3 HV_REGISTER_CRASH_P3 279 #define HV_X64_MSR_CRASH_P4 HV_REGISTER_CRASH_P4 280 #define HV_X64_MSR_CRASH_CTL HV_REGISTER_CRASH_CTL 281 #define HV_X64_MSR_TIME_REF_COUNT HV_REGISTER_TIME_REF_COUNT 282 #define HV_X64_MSR_REFERENCE_TSC HV_REGISTER_REFERENCE_TSC 283 284 /* Hyper-V memory host visibility */ 285 enum hv_mem_host_visibility { 286 VMBUS_PAGE_NOT_VISIBLE = 0, 287 VMBUS_PAGE_VISIBLE_READ_ONLY = 1, 288 VMBUS_PAGE_VISIBLE_READ_WRITE = 3 289 }; 290 291 /* HvCallModifySparseGpaPageHostVisibility hypercall */ 292 #define HV_MAX_MODIFY_GPA_REP_COUNT ((PAGE_SIZE / sizeof(u64)) - 2) 293 struct hv_gpa_range_for_visibility { 294 u64 partition_id; 295 u32 host_visibility:2; 296 u32 reserved0:30; 297 u32 reserved1; 298 u64 gpa_page_list[HV_MAX_MODIFY_GPA_REP_COUNT]; 299 } __packed; 300 301 /* 302 * Declare the MSR used to setup pages used to communicate with the hypervisor. 303 */ 304 union hv_x64_msr_hypercall_contents { 305 u64 as_uint64; 306 struct { 307 u64 enable:1; 308 u64 reserved:11; 309 u64 guest_physical_address:52; 310 } __packed; 311 }; 312 313 union hv_vp_assist_msr_contents { 314 u64 as_uint64; 315 struct { 316 u64 enable:1; 317 u64 reserved:11; 318 u64 pfn:52; 319 } __packed; 320 }; 321 322 struct hv_reenlightenment_control { 323 __u64 vector:8; 324 __u64 reserved1:8; 325 __u64 enabled:1; 326 __u64 reserved2:15; 327 __u64 target_vp:32; 328 } __packed; 329 330 struct hv_tsc_emulation_control { 331 __u64 enabled:1; 332 __u64 reserved:63; 333 } __packed; 334 335 struct hv_tsc_emulation_status { 336 __u64 inprogress:1; 337 __u64 reserved:63; 338 } __packed; 339 340 #define HV_X64_MSR_HYPERCALL_ENABLE 0x00000001 341 #define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT 12 342 #define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_MASK \ 343 (~((1ull << HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT) - 1)) 344 345 #define HV_X64_MSR_CRASH_PARAMS \ 346 (1 + (HV_X64_MSR_CRASH_P4 - HV_X64_MSR_CRASH_P0)) 347 348 #define HV_IPI_LOW_VECTOR 0x10 349 #define HV_IPI_HIGH_VECTOR 0xff 350 351 #define HV_X64_MSR_VP_ASSIST_PAGE_ENABLE 0x00000001 352 #define HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_SHIFT 12 353 #define HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_MASK \ 354 (~((1ull << HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_SHIFT) - 1)) 355 356 /* Hyper-V Enlightened VMCS version mask in nested features CPUID */ 357 #define HV_X64_ENLIGHTENED_VMCS_VERSION 0xff 358 359 #define HV_X64_MSR_TSC_REFERENCE_ENABLE 0x00000001 360 #define HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT 12 361 362 /* Number of XMM registers used in hypercall input/output */ 363 #define HV_HYPERCALL_MAX_XMM_REGISTERS 6 364 365 struct hv_nested_enlightenments_control { 366 struct { 367 __u32 directhypercall:1; 368 __u32 reserved:31; 369 } features; 370 struct { 371 __u32 reserved; 372 } hypercallControls; 373 } __packed; 374 375 /* Define virtual processor assist page structure. */ 376 struct hv_vp_assist_page { 377 __u32 apic_assist; 378 __u32 reserved1; 379 __u32 vtl_entry_reason; 380 __u32 vtl_reserved; 381 __u64 vtl_ret_x64rax; 382 __u64 vtl_ret_x64rcx; 383 struct hv_nested_enlightenments_control nested_control; 384 __u8 enlighten_vmentry; 385 __u8 reserved2[7]; 386 __u64 current_nested_vmcs; 387 __u8 synthetic_time_unhalted_timer_expired; 388 __u8 reserved3[7]; 389 __u8 virtualization_fault_information[40]; 390 __u8 reserved4[8]; 391 __u8 intercept_message[256]; 392 __u8 vtl_ret_actions[256]; 393 } __packed; 394 395 struct hv_enlightened_vmcs { 396 u32 revision_id; 397 u32 abort; 398 399 u16 host_es_selector; 400 u16 host_cs_selector; 401 u16 host_ss_selector; 402 u16 host_ds_selector; 403 u16 host_fs_selector; 404 u16 host_gs_selector; 405 u16 host_tr_selector; 406 407 u16 padding16_1; 408 409 u64 host_ia32_pat; 410 u64 host_ia32_efer; 411 412 u64 host_cr0; 413 u64 host_cr3; 414 u64 host_cr4; 415 416 u64 host_ia32_sysenter_esp; 417 u64 host_ia32_sysenter_eip; 418 u64 host_rip; 419 u32 host_ia32_sysenter_cs; 420 421 u32 pin_based_vm_exec_control; 422 u32 vm_exit_controls; 423 u32 secondary_vm_exec_control; 424 425 u64 io_bitmap_a; 426 u64 io_bitmap_b; 427 u64 msr_bitmap; 428 429 u16 guest_es_selector; 430 u16 guest_cs_selector; 431 u16 guest_ss_selector; 432 u16 guest_ds_selector; 433 u16 guest_fs_selector; 434 u16 guest_gs_selector; 435 u16 guest_ldtr_selector; 436 u16 guest_tr_selector; 437 438 u32 guest_es_limit; 439 u32 guest_cs_limit; 440 u32 guest_ss_limit; 441 u32 guest_ds_limit; 442 u32 guest_fs_limit; 443 u32 guest_gs_limit; 444 u32 guest_ldtr_limit; 445 u32 guest_tr_limit; 446 u32 guest_gdtr_limit; 447 u32 guest_idtr_limit; 448 449 u32 guest_es_ar_bytes; 450 u32 guest_cs_ar_bytes; 451 u32 guest_ss_ar_bytes; 452 u32 guest_ds_ar_bytes; 453 u32 guest_fs_ar_bytes; 454 u32 guest_gs_ar_bytes; 455 u32 guest_ldtr_ar_bytes; 456 u32 guest_tr_ar_bytes; 457 458 u64 guest_es_base; 459 u64 guest_cs_base; 460 u64 guest_ss_base; 461 u64 guest_ds_base; 462 u64 guest_fs_base; 463 u64 guest_gs_base; 464 u64 guest_ldtr_base; 465 u64 guest_tr_base; 466 u64 guest_gdtr_base; 467 u64 guest_idtr_base; 468 469 u64 padding64_1[3]; 470 471 u64 vm_exit_msr_store_addr; 472 u64 vm_exit_msr_load_addr; 473 u64 vm_entry_msr_load_addr; 474 475 u64 cr3_target_value0; 476 u64 cr3_target_value1; 477 u64 cr3_target_value2; 478 u64 cr3_target_value3; 479 480 u32 page_fault_error_code_mask; 481 u32 page_fault_error_code_match; 482 483 u32 cr3_target_count; 484 u32 vm_exit_msr_store_count; 485 u32 vm_exit_msr_load_count; 486 u32 vm_entry_msr_load_count; 487 488 u64 tsc_offset; 489 u64 virtual_apic_page_addr; 490 u64 vmcs_link_pointer; 491 492 u64 guest_ia32_debugctl; 493 u64 guest_ia32_pat; 494 u64 guest_ia32_efer; 495 496 u64 guest_pdptr0; 497 u64 guest_pdptr1; 498 u64 guest_pdptr2; 499 u64 guest_pdptr3; 500 501 u64 guest_pending_dbg_exceptions; 502 u64 guest_sysenter_esp; 503 u64 guest_sysenter_eip; 504 505 u32 guest_activity_state; 506 u32 guest_sysenter_cs; 507 508 u64 cr0_guest_host_mask; 509 u64 cr4_guest_host_mask; 510 u64 cr0_read_shadow; 511 u64 cr4_read_shadow; 512 u64 guest_cr0; 513 u64 guest_cr3; 514 u64 guest_cr4; 515 u64 guest_dr7; 516 517 u64 host_fs_base; 518 u64 host_gs_base; 519 u64 host_tr_base; 520 u64 host_gdtr_base; 521 u64 host_idtr_base; 522 u64 host_rsp; 523 524 u64 ept_pointer; 525 526 u16 virtual_processor_id; 527 u16 padding16_2[3]; 528 529 u64 padding64_2[5]; 530 u64 guest_physical_address; 531 532 u32 vm_instruction_error; 533 u32 vm_exit_reason; 534 u32 vm_exit_intr_info; 535 u32 vm_exit_intr_error_code; 536 u32 idt_vectoring_info_field; 537 u32 idt_vectoring_error_code; 538 u32 vm_exit_instruction_len; 539 u32 vmx_instruction_info; 540 541 u64 exit_qualification; 542 u64 exit_io_instruction_ecx; 543 u64 exit_io_instruction_esi; 544 u64 exit_io_instruction_edi; 545 u64 exit_io_instruction_eip; 546 547 u64 guest_linear_address; 548 u64 guest_rsp; 549 u64 guest_rflags; 550 551 u32 guest_interruptibility_info; 552 u32 cpu_based_vm_exec_control; 553 u32 exception_bitmap; 554 u32 vm_entry_controls; 555 u32 vm_entry_intr_info_field; 556 u32 vm_entry_exception_error_code; 557 u32 vm_entry_instruction_len; 558 u32 tpr_threshold; 559 560 u64 guest_rip; 561 562 u32 hv_clean_fields; 563 u32 padding32_1; 564 u32 hv_synthetic_controls; 565 struct { 566 u32 nested_flush_hypercall:1; 567 u32 msr_bitmap:1; 568 u32 reserved:30; 569 } __packed hv_enlightenments_control; 570 u32 hv_vp_id; 571 u32 padding32_2; 572 u64 hv_vm_id; 573 u64 partition_assist_page; 574 u64 padding64_4[4]; 575 u64 guest_bndcfgs; 576 u64 guest_ia32_perf_global_ctrl; 577 u64 guest_ia32_s_cet; 578 u64 guest_ssp; 579 u64 guest_ia32_int_ssp_table_addr; 580 u64 guest_ia32_lbr_ctl; 581 u64 padding64_5[2]; 582 u64 xss_exit_bitmap; 583 u64 encls_exiting_bitmap; 584 u64 host_ia32_perf_global_ctrl; 585 u64 tsc_multiplier; 586 u64 host_ia32_s_cet; 587 u64 host_ssp; 588 u64 host_ia32_int_ssp_table_addr; 589 u64 padding64_6; 590 } __packed; 591 592 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_NONE 0 593 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_IO_BITMAP BIT(0) 594 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_MSR_BITMAP BIT(1) 595 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_GRP2 BIT(2) 596 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_GRP1 BIT(3) 597 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_PROC BIT(4) 598 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_EVENT BIT(5) 599 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_ENTRY BIT(6) 600 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_EXCPN BIT(7) 601 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CRDR BIT(8) 602 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_XLAT BIT(9) 603 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_BASIC BIT(10) 604 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_GRP1 BIT(11) 605 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_GRP2 BIT(12) 606 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_HOST_POINTER BIT(13) 607 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_HOST_GRP1 BIT(14) 608 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_ENLIGHTENMENTSCONTROL BIT(15) 609 610 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL 0xFFFF 611 612 /* 613 * Note, Hyper-V isn't actually stealing bit 28 from Intel, just abusing it by 614 * pairing it with architecturally impossible exit reasons. Bit 28 is set only 615 * on SMI exits to a SMI transfer monitor (STM) and if and only if a MTF VM-Exit 616 * is pending. I.e. it will never be set by hardware for non-SMI exits (there 617 * are only three), nor will it ever be set unless the VMM is an STM. 618 */ 619 #define HV_VMX_SYNTHETIC_EXIT_REASON_TRAP_AFTER_FLUSH 0x10000031 620 621 /* 622 * Hyper-V uses the software reserved 32 bytes in VMCB control area to expose 623 * SVM enlightenments to guests. 624 */ 625 struct hv_vmcb_enlightenments { 626 struct __packed hv_enlightenments_control { 627 u32 nested_flush_hypercall:1; 628 u32 msr_bitmap:1; 629 u32 enlightened_npt_tlb: 1; 630 u32 reserved:29; 631 } __packed hv_enlightenments_control; 632 u32 hv_vp_id; 633 u64 hv_vm_id; 634 u64 partition_assist_page; 635 u64 reserved; 636 } __packed; 637 638 /* 639 * Hyper-V uses the software reserved clean bit in VMCB. 640 */ 641 #define HV_VMCB_NESTED_ENLIGHTENMENTS 31 642 643 /* Synthetic VM-Exit */ 644 #define HV_SVM_EXITCODE_ENL 0xf0000000 645 #define HV_SVM_ENL_EXITCODE_TRAP_AFTER_FLUSH (1) 646 647 struct hv_partition_assist_pg { 648 u32 tlb_lock_count; 649 }; 650 651 enum hv_interrupt_type { 652 HV_X64_INTERRUPT_TYPE_FIXED = 0x0000, 653 HV_X64_INTERRUPT_TYPE_LOWESTPRIORITY = 0x0001, 654 HV_X64_INTERRUPT_TYPE_SMI = 0x0002, 655 HV_X64_INTERRUPT_TYPE_REMOTEREAD = 0x0003, 656 HV_X64_INTERRUPT_TYPE_NMI = 0x0004, 657 HV_X64_INTERRUPT_TYPE_INIT = 0x0005, 658 HV_X64_INTERRUPT_TYPE_SIPI = 0x0006, 659 HV_X64_INTERRUPT_TYPE_EXTINT = 0x0007, 660 HV_X64_INTERRUPT_TYPE_LOCALINT0 = 0x0008, 661 HV_X64_INTERRUPT_TYPE_LOCALINT1 = 0x0009, 662 HV_X64_INTERRUPT_TYPE_MAXIMUM = 0x000A, 663 }; 664 665 union hv_msi_address_register { 666 u32 as_uint32; 667 struct { 668 u32 reserved1:2; 669 u32 destination_mode:1; 670 u32 redirection_hint:1; 671 u32 reserved2:8; 672 u32 destination_id:8; 673 u32 msi_base:12; 674 }; 675 } __packed; 676 677 union hv_msi_data_register { 678 u32 as_uint32; 679 struct { 680 u32 vector:8; 681 u32 delivery_mode:3; 682 u32 reserved1:3; 683 u32 level_assert:1; 684 u32 trigger_mode:1; 685 u32 reserved2:16; 686 }; 687 } __packed; 688 689 /* HvRetargetDeviceInterrupt hypercall */ 690 union hv_msi_entry { 691 u64 as_uint64; 692 struct { 693 union hv_msi_address_register address; 694 union hv_msi_data_register data; 695 } __packed; 696 }; 697 698 #include <asm-generic/hyperv-tlfs.h> 699 700 #endif 701