1 /* SPDX-License-Identifier: GPL-2.0 */ 2 3 /* 4 * This file contains definitions from Hyper-V Hypervisor Top-Level Functional 5 * Specification (TLFS): 6 * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs 7 */ 8 9 #ifndef _ASM_X86_HYPERV_TLFS_H 10 #define _ASM_X86_HYPERV_TLFS_H 11 12 #include <linux/types.h> 13 #include <asm/page.h> 14 15 /* 16 * While not explicitly listed in the TLFS, Hyper-V always runs with a page size 17 * of 4096. These definitions are used when communicating with Hyper-V using 18 * guest physical pages and guest physical page addresses, since the guest page 19 * size may not be 4096 on all architectures. 20 */ 21 #define HV_HYP_PAGE_SHIFT 12 22 #define HV_HYP_PAGE_SIZE BIT(HV_HYP_PAGE_SHIFT) 23 #define HV_HYP_PAGE_MASK (~(HV_HYP_PAGE_SIZE - 1)) 24 25 /* 26 * The below CPUID leaves are present if VersionAndFeatures.HypervisorPresent 27 * is set by CPUID(HvCpuIdFunctionVersionAndFeatures). 28 */ 29 #define HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS 0x40000000 30 #define HYPERV_CPUID_INTERFACE 0x40000001 31 #define HYPERV_CPUID_VERSION 0x40000002 32 #define HYPERV_CPUID_FEATURES 0x40000003 33 #define HYPERV_CPUID_ENLIGHTMENT_INFO 0x40000004 34 #define HYPERV_CPUID_IMPLEMENT_LIMITS 0x40000005 35 #define HYPERV_CPUID_NESTED_FEATURES 0x4000000A 36 37 #define HYPERV_HYPERVISOR_PRESENT_BIT 0x80000000 38 #define HYPERV_CPUID_MIN 0x40000005 39 #define HYPERV_CPUID_MAX 0x4000ffff 40 41 /* 42 * Feature identification. EAX indicates which features are available 43 * to the partition based upon the current partition privileges. 44 * These are HYPERV_CPUID_FEATURES.EAX bits. 45 */ 46 47 /* VP Runtime (HV_X64_MSR_VP_RUNTIME) available */ 48 #define HV_X64_MSR_VP_RUNTIME_AVAILABLE BIT(0) 49 /* Partition Reference Counter (HV_X64_MSR_TIME_REF_COUNT) available*/ 50 #define HV_MSR_TIME_REF_COUNT_AVAILABLE BIT(1) 51 /* 52 * Basic SynIC MSRs (HV_X64_MSR_SCONTROL through HV_X64_MSR_EOM 53 * and HV_X64_MSR_SINT0 through HV_X64_MSR_SINT15) available 54 */ 55 #define HV_X64_MSR_SYNIC_AVAILABLE BIT(2) 56 /* 57 * Synthetic Timer MSRs (HV_X64_MSR_STIMER0_CONFIG through 58 * HV_X64_MSR_STIMER3_COUNT) available 59 */ 60 #define HV_MSR_SYNTIMER_AVAILABLE BIT(3) 61 /* 62 * APIC access MSRs (HV_X64_MSR_EOI, HV_X64_MSR_ICR and HV_X64_MSR_TPR) 63 * are available 64 */ 65 #define HV_X64_MSR_APIC_ACCESS_AVAILABLE BIT(4) 66 /* Hypercall MSRs (HV_X64_MSR_GUEST_OS_ID and HV_X64_MSR_HYPERCALL) available*/ 67 #define HV_X64_MSR_HYPERCALL_AVAILABLE BIT(5) 68 /* Access virtual processor index MSR (HV_X64_MSR_VP_INDEX) available*/ 69 #define HV_X64_MSR_VP_INDEX_AVAILABLE BIT(6) 70 /* Virtual system reset MSR (HV_X64_MSR_RESET) is available*/ 71 #define HV_X64_MSR_RESET_AVAILABLE BIT(7) 72 /* 73 * Access statistics pages MSRs (HV_X64_MSR_STATS_PARTITION_RETAIL_PAGE, 74 * HV_X64_MSR_STATS_PARTITION_INTERNAL_PAGE, HV_X64_MSR_STATS_VP_RETAIL_PAGE, 75 * HV_X64_MSR_STATS_VP_INTERNAL_PAGE) available 76 */ 77 #define HV_X64_MSR_STAT_PAGES_AVAILABLE BIT(8) 78 /* Partition reference TSC MSR is available */ 79 #define HV_MSR_REFERENCE_TSC_AVAILABLE BIT(9) 80 /* Partition Guest IDLE MSR is available */ 81 #define HV_X64_MSR_GUEST_IDLE_AVAILABLE BIT(10) 82 /* 83 * There is a single feature flag that signifies if the partition has access 84 * to MSRs with local APIC and TSC frequencies. 85 */ 86 #define HV_X64_ACCESS_FREQUENCY_MSRS BIT(11) 87 /* AccessReenlightenmentControls privilege */ 88 #define HV_X64_ACCESS_REENLIGHTENMENT BIT(13) 89 90 /* 91 * Feature identification: indicates which flags were specified at partition 92 * creation. The format is the same as the partition creation flag structure 93 * defined in section Partition Creation Flags. 94 * These are HYPERV_CPUID_FEATURES.EBX bits. 95 */ 96 #define HV_X64_CREATE_PARTITIONS BIT(0) 97 #define HV_X64_ACCESS_PARTITION_ID BIT(1) 98 #define HV_X64_ACCESS_MEMORY_POOL BIT(2) 99 #define HV_X64_ADJUST_MESSAGE_BUFFERS BIT(3) 100 #define HV_X64_POST_MESSAGES BIT(4) 101 #define HV_X64_SIGNAL_EVENTS BIT(5) 102 #define HV_X64_CREATE_PORT BIT(6) 103 #define HV_X64_CONNECT_PORT BIT(7) 104 #define HV_X64_ACCESS_STATS BIT(8) 105 #define HV_X64_DEBUGGING BIT(11) 106 #define HV_X64_CPU_POWER_MANAGEMENT BIT(12) 107 108 /* 109 * Feature identification. EDX indicates which miscellaneous features 110 * are available to the partition. 111 * These are HYPERV_CPUID_FEATURES.EDX bits. 112 */ 113 /* The MWAIT instruction is available (per section MONITOR / MWAIT) */ 114 #define HV_X64_MWAIT_AVAILABLE BIT(0) 115 /* Guest debugging support is available */ 116 #define HV_X64_GUEST_DEBUGGING_AVAILABLE BIT(1) 117 /* Performance Monitor support is available*/ 118 #define HV_X64_PERF_MONITOR_AVAILABLE BIT(2) 119 /* Support for physical CPU dynamic partitioning events is available*/ 120 #define HV_X64_CPU_DYNAMIC_PARTITIONING_AVAILABLE BIT(3) 121 /* 122 * Support for passing hypercall input parameter block via XMM 123 * registers is available 124 */ 125 #define HV_X64_HYPERCALL_PARAMS_XMM_AVAILABLE BIT(4) 126 /* Support for a virtual guest idle state is available */ 127 #define HV_X64_GUEST_IDLE_STATE_AVAILABLE BIT(5) 128 /* Frequency MSRs available */ 129 #define HV_FEATURE_FREQUENCY_MSRS_AVAILABLE BIT(8) 130 /* Crash MSR available */ 131 #define HV_FEATURE_GUEST_CRASH_MSR_AVAILABLE BIT(10) 132 /* stimer Direct Mode is available */ 133 #define HV_STIMER_DIRECT_MODE_AVAILABLE BIT(19) 134 135 /* 136 * Implementation recommendations. Indicates which behaviors the hypervisor 137 * recommends the OS implement for optimal performance. 138 * These are HYPERV_CPUID_ENLIGHTMENT_INFO.EAX bits. 139 */ 140 /* 141 * Recommend using hypercall for address space switches rather 142 * than MOV to CR3 instruction 143 */ 144 #define HV_X64_AS_SWITCH_RECOMMENDED BIT(0) 145 /* Recommend using hypercall for local TLB flushes rather 146 * than INVLPG or MOV to CR3 instructions */ 147 #define HV_X64_LOCAL_TLB_FLUSH_RECOMMENDED BIT(1) 148 /* 149 * Recommend using hypercall for remote TLB flushes rather 150 * than inter-processor interrupts 151 */ 152 #define HV_X64_REMOTE_TLB_FLUSH_RECOMMENDED BIT(2) 153 /* 154 * Recommend using MSRs for accessing APIC registers 155 * EOI, ICR and TPR rather than their memory-mapped counterparts 156 */ 157 #define HV_X64_APIC_ACCESS_RECOMMENDED BIT(3) 158 /* Recommend using the hypervisor-provided MSR to initiate a system RESET */ 159 #define HV_X64_SYSTEM_RESET_RECOMMENDED BIT(4) 160 /* 161 * Recommend using relaxed timing for this partition. If used, 162 * the VM should disable any watchdog timeouts that rely on the 163 * timely delivery of external interrupts 164 */ 165 #define HV_X64_RELAXED_TIMING_RECOMMENDED BIT(5) 166 167 /* 168 * Recommend not using Auto End-Of-Interrupt feature 169 */ 170 #define HV_DEPRECATING_AEOI_RECOMMENDED BIT(9) 171 172 /* 173 * Recommend using cluster IPI hypercalls. 174 */ 175 #define HV_X64_CLUSTER_IPI_RECOMMENDED BIT(10) 176 177 /* Recommend using the newer ExProcessorMasks interface */ 178 #define HV_X64_EX_PROCESSOR_MASKS_RECOMMENDED BIT(11) 179 180 /* Recommend using enlightened VMCS */ 181 #define HV_X64_ENLIGHTENED_VMCS_RECOMMENDED BIT(14) 182 183 /* Nested features. These are HYPERV_CPUID_NESTED_FEATURES.EAX bits. */ 184 #define HV_X64_NESTED_GUEST_MAPPING_FLUSH BIT(18) 185 #define HV_X64_NESTED_MSR_BITMAP BIT(19) 186 187 /* Hyper-V specific model specific registers (MSRs) */ 188 189 /* MSR used to identify the guest OS. */ 190 #define HV_X64_MSR_GUEST_OS_ID 0x40000000 191 192 /* MSR used to setup pages used to communicate with the hypervisor. */ 193 #define HV_X64_MSR_HYPERCALL 0x40000001 194 195 /* MSR used to provide vcpu index */ 196 #define HV_X64_MSR_VP_INDEX 0x40000002 197 198 /* MSR used to reset the guest OS. */ 199 #define HV_X64_MSR_RESET 0x40000003 200 201 /* MSR used to provide vcpu runtime in 100ns units */ 202 #define HV_X64_MSR_VP_RUNTIME 0x40000010 203 204 /* MSR used to read the per-partition time reference counter */ 205 #define HV_X64_MSR_TIME_REF_COUNT 0x40000020 206 207 /* A partition's reference time stamp counter (TSC) page */ 208 #define HV_X64_MSR_REFERENCE_TSC 0x40000021 209 210 /* MSR used to retrieve the TSC frequency */ 211 #define HV_X64_MSR_TSC_FREQUENCY 0x40000022 212 213 /* MSR used to retrieve the local APIC timer frequency */ 214 #define HV_X64_MSR_APIC_FREQUENCY 0x40000023 215 216 /* Define the virtual APIC registers */ 217 #define HV_X64_MSR_EOI 0x40000070 218 #define HV_X64_MSR_ICR 0x40000071 219 #define HV_X64_MSR_TPR 0x40000072 220 #define HV_X64_MSR_VP_ASSIST_PAGE 0x40000073 221 222 /* Define synthetic interrupt controller model specific registers. */ 223 #define HV_X64_MSR_SCONTROL 0x40000080 224 #define HV_X64_MSR_SVERSION 0x40000081 225 #define HV_X64_MSR_SIEFP 0x40000082 226 #define HV_X64_MSR_SIMP 0x40000083 227 #define HV_X64_MSR_EOM 0x40000084 228 #define HV_X64_MSR_SINT0 0x40000090 229 #define HV_X64_MSR_SINT1 0x40000091 230 #define HV_X64_MSR_SINT2 0x40000092 231 #define HV_X64_MSR_SINT3 0x40000093 232 #define HV_X64_MSR_SINT4 0x40000094 233 #define HV_X64_MSR_SINT5 0x40000095 234 #define HV_X64_MSR_SINT6 0x40000096 235 #define HV_X64_MSR_SINT7 0x40000097 236 #define HV_X64_MSR_SINT8 0x40000098 237 #define HV_X64_MSR_SINT9 0x40000099 238 #define HV_X64_MSR_SINT10 0x4000009A 239 #define HV_X64_MSR_SINT11 0x4000009B 240 #define HV_X64_MSR_SINT12 0x4000009C 241 #define HV_X64_MSR_SINT13 0x4000009D 242 #define HV_X64_MSR_SINT14 0x4000009E 243 #define HV_X64_MSR_SINT15 0x4000009F 244 245 /* 246 * Synthetic Timer MSRs. Four timers per vcpu. 247 */ 248 #define HV_X64_MSR_STIMER0_CONFIG 0x400000B0 249 #define HV_X64_MSR_STIMER0_COUNT 0x400000B1 250 #define HV_X64_MSR_STIMER1_CONFIG 0x400000B2 251 #define HV_X64_MSR_STIMER1_COUNT 0x400000B3 252 #define HV_X64_MSR_STIMER2_CONFIG 0x400000B4 253 #define HV_X64_MSR_STIMER2_COUNT 0x400000B5 254 #define HV_X64_MSR_STIMER3_CONFIG 0x400000B6 255 #define HV_X64_MSR_STIMER3_COUNT 0x400000B7 256 257 /* Hyper-V guest idle MSR */ 258 #define HV_X64_MSR_GUEST_IDLE 0x400000F0 259 260 /* Hyper-V guest crash notification MSR's */ 261 #define HV_X64_MSR_CRASH_P0 0x40000100 262 #define HV_X64_MSR_CRASH_P1 0x40000101 263 #define HV_X64_MSR_CRASH_P2 0x40000102 264 #define HV_X64_MSR_CRASH_P3 0x40000103 265 #define HV_X64_MSR_CRASH_P4 0x40000104 266 #define HV_X64_MSR_CRASH_CTL 0x40000105 267 268 /* TSC emulation after migration */ 269 #define HV_X64_MSR_REENLIGHTENMENT_CONTROL 0x40000106 270 #define HV_X64_MSR_TSC_EMULATION_CONTROL 0x40000107 271 #define HV_X64_MSR_TSC_EMULATION_STATUS 0x40000108 272 273 /* 274 * Declare the MSR used to setup pages used to communicate with the hypervisor. 275 */ 276 union hv_x64_msr_hypercall_contents { 277 u64 as_uint64; 278 struct { 279 u64 enable:1; 280 u64 reserved:11; 281 u64 guest_physical_address:52; 282 } __packed; 283 }; 284 285 /* 286 * TSC page layout. 287 */ 288 struct ms_hyperv_tsc_page { 289 volatile u32 tsc_sequence; 290 u32 reserved1; 291 volatile u64 tsc_scale; 292 volatile s64 tsc_offset; 293 u64 reserved2[509]; 294 } __packed; 295 296 /* 297 * The guest OS needs to register the guest ID with the hypervisor. 298 * The guest ID is a 64 bit entity and the structure of this ID is 299 * specified in the Hyper-V specification: 300 * 301 * msdn.microsoft.com/en-us/library/windows/hardware/ff542653%28v=vs.85%29.aspx 302 * 303 * While the current guideline does not specify how Linux guest ID(s) 304 * need to be generated, our plan is to publish the guidelines for 305 * Linux and other guest operating systems that currently are hosted 306 * on Hyper-V. The implementation here conforms to this yet 307 * unpublished guidelines. 308 * 309 * 310 * Bit(s) 311 * 63 - Indicates if the OS is Open Source or not; 1 is Open Source 312 * 62:56 - Os Type; Linux is 0x100 313 * 55:48 - Distro specific identification 314 * 47:16 - Linux kernel version number 315 * 15:0 - Distro specific identification 316 * 317 * 318 */ 319 320 #define HV_LINUX_VENDOR_ID 0x8100 321 322 struct hv_reenlightenment_control { 323 __u64 vector:8; 324 __u64 reserved1:8; 325 __u64 enabled:1; 326 __u64 reserved2:15; 327 __u64 target_vp:32; 328 } __packed; 329 330 struct hv_tsc_emulation_control { 331 __u64 enabled:1; 332 __u64 reserved:63; 333 } __packed; 334 335 struct hv_tsc_emulation_status { 336 __u64 inprogress:1; 337 __u64 reserved:63; 338 } __packed; 339 340 #define HV_X64_MSR_HYPERCALL_ENABLE 0x00000001 341 #define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT 12 342 #define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_MASK \ 343 (~((1ull << HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT) - 1)) 344 345 /* 346 * Crash notification (HV_X64_MSR_CRASH_CTL) flags. 347 */ 348 #define HV_CRASH_CTL_CRASH_NOTIFY_MSG BIT_ULL(62) 349 #define HV_CRASH_CTL_CRASH_NOTIFY BIT_ULL(63) 350 #define HV_X64_MSR_CRASH_PARAMS \ 351 (1 + (HV_X64_MSR_CRASH_P4 - HV_X64_MSR_CRASH_P0)) 352 353 #define HV_IPI_LOW_VECTOR 0x10 354 #define HV_IPI_HIGH_VECTOR 0xff 355 356 /* Declare the various hypercall operations. */ 357 #define HVCALL_FLUSH_VIRTUAL_ADDRESS_SPACE 0x0002 358 #define HVCALL_FLUSH_VIRTUAL_ADDRESS_LIST 0x0003 359 #define HVCALL_NOTIFY_LONG_SPIN_WAIT 0x0008 360 #define HVCALL_SEND_IPI 0x000b 361 #define HVCALL_FLUSH_VIRTUAL_ADDRESS_SPACE_EX 0x0013 362 #define HVCALL_FLUSH_VIRTUAL_ADDRESS_LIST_EX 0x0014 363 #define HVCALL_SEND_IPI_EX 0x0015 364 #define HVCALL_POST_MESSAGE 0x005c 365 #define HVCALL_SIGNAL_EVENT 0x005d 366 #define HVCALL_FLUSH_GUEST_PHYSICAL_ADDRESS_SPACE 0x00af 367 #define HVCALL_FLUSH_GUEST_PHYSICAL_ADDRESS_LIST 0x00b0 368 369 #define HV_X64_MSR_VP_ASSIST_PAGE_ENABLE 0x00000001 370 #define HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_SHIFT 12 371 #define HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_MASK \ 372 (~((1ull << HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_SHIFT) - 1)) 373 374 /* Hyper-V Enlightened VMCS version mask in nested features CPUID */ 375 #define HV_X64_ENLIGHTENED_VMCS_VERSION 0xff 376 377 #define HV_X64_MSR_TSC_REFERENCE_ENABLE 0x00000001 378 #define HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT 12 379 380 #define HV_PROCESSOR_POWER_STATE_C0 0 381 #define HV_PROCESSOR_POWER_STATE_C1 1 382 #define HV_PROCESSOR_POWER_STATE_C2 2 383 #define HV_PROCESSOR_POWER_STATE_C3 3 384 385 #define HV_FLUSH_ALL_PROCESSORS BIT(0) 386 #define HV_FLUSH_ALL_VIRTUAL_ADDRESS_SPACES BIT(1) 387 #define HV_FLUSH_NON_GLOBAL_MAPPINGS_ONLY BIT(2) 388 #define HV_FLUSH_USE_EXTENDED_RANGE_FORMAT BIT(3) 389 390 enum HV_GENERIC_SET_FORMAT { 391 HV_GENERIC_SET_SPARSE_4K, 392 HV_GENERIC_SET_ALL, 393 }; 394 395 #define HV_HYPERCALL_RESULT_MASK GENMASK_ULL(15, 0) 396 #define HV_HYPERCALL_FAST_BIT BIT(16) 397 #define HV_HYPERCALL_VARHEAD_OFFSET 17 398 #define HV_HYPERCALL_REP_COMP_OFFSET 32 399 #define HV_HYPERCALL_REP_COMP_MASK GENMASK_ULL(43, 32) 400 #define HV_HYPERCALL_REP_START_OFFSET 48 401 #define HV_HYPERCALL_REP_START_MASK GENMASK_ULL(59, 48) 402 403 /* hypercall status code */ 404 #define HV_STATUS_SUCCESS 0 405 #define HV_STATUS_INVALID_HYPERCALL_CODE 2 406 #define HV_STATUS_INVALID_HYPERCALL_INPUT 3 407 #define HV_STATUS_INVALID_ALIGNMENT 4 408 #define HV_STATUS_INVALID_PARAMETER 5 409 #define HV_STATUS_INSUFFICIENT_MEMORY 11 410 #define HV_STATUS_INVALID_PORT_ID 17 411 #define HV_STATUS_INVALID_CONNECTION_ID 18 412 #define HV_STATUS_INSUFFICIENT_BUFFERS 19 413 414 /* 415 * The Hyper-V TimeRefCount register and the TSC 416 * page provide a guest VM clock with 100ns tick rate 417 */ 418 #define HV_CLOCK_HZ (NSEC_PER_SEC/100) 419 420 typedef struct _HV_REFERENCE_TSC_PAGE { 421 __u32 tsc_sequence; 422 __u32 res1; 423 __u64 tsc_scale; 424 __s64 tsc_offset; 425 } __packed HV_REFERENCE_TSC_PAGE, *PHV_REFERENCE_TSC_PAGE; 426 427 /* Define the number of synthetic interrupt sources. */ 428 #define HV_SYNIC_SINT_COUNT (16) 429 /* Define the expected SynIC version. */ 430 #define HV_SYNIC_VERSION_1 (0x1) 431 /* Valid SynIC vectors are 16-255. */ 432 #define HV_SYNIC_FIRST_VALID_VECTOR (16) 433 434 #define HV_SYNIC_CONTROL_ENABLE (1ULL << 0) 435 #define HV_SYNIC_SIMP_ENABLE (1ULL << 0) 436 #define HV_SYNIC_SIEFP_ENABLE (1ULL << 0) 437 #define HV_SYNIC_SINT_MASKED (1ULL << 16) 438 #define HV_SYNIC_SINT_AUTO_EOI (1ULL << 17) 439 #define HV_SYNIC_SINT_VECTOR_MASK (0xFF) 440 441 #define HV_SYNIC_STIMER_COUNT (4) 442 443 /* Define synthetic interrupt controller message constants. */ 444 #define HV_MESSAGE_SIZE (256) 445 #define HV_MESSAGE_PAYLOAD_BYTE_COUNT (240) 446 #define HV_MESSAGE_PAYLOAD_QWORD_COUNT (30) 447 448 /* Define hypervisor message types. */ 449 enum hv_message_type { 450 HVMSG_NONE = 0x00000000, 451 452 /* Memory access messages. */ 453 HVMSG_UNMAPPED_GPA = 0x80000000, 454 HVMSG_GPA_INTERCEPT = 0x80000001, 455 456 /* Timer notification messages. */ 457 HVMSG_TIMER_EXPIRED = 0x80000010, 458 459 /* Error messages. */ 460 HVMSG_INVALID_VP_REGISTER_VALUE = 0x80000020, 461 HVMSG_UNRECOVERABLE_EXCEPTION = 0x80000021, 462 HVMSG_UNSUPPORTED_FEATURE = 0x80000022, 463 464 /* Trace buffer complete messages. */ 465 HVMSG_EVENTLOG_BUFFERCOMPLETE = 0x80000040, 466 467 /* Platform-specific processor intercept messages. */ 468 HVMSG_X64_IOPORT_INTERCEPT = 0x80010000, 469 HVMSG_X64_MSR_INTERCEPT = 0x80010001, 470 HVMSG_X64_CPUID_INTERCEPT = 0x80010002, 471 HVMSG_X64_EXCEPTION_INTERCEPT = 0x80010003, 472 HVMSG_X64_APIC_EOI = 0x80010004, 473 HVMSG_X64_LEGACY_FP_ERROR = 0x80010005 474 }; 475 476 /* Define synthetic interrupt controller message flags. */ 477 union hv_message_flags { 478 __u8 asu8; 479 struct { 480 __u8 msg_pending:1; 481 __u8 reserved:7; 482 } __packed; 483 }; 484 485 /* Define port identifier type. */ 486 union hv_port_id { 487 __u32 asu32; 488 struct { 489 __u32 id:24; 490 __u32 reserved:8; 491 } __packed u; 492 }; 493 494 /* Define synthetic interrupt controller message header. */ 495 struct hv_message_header { 496 __u32 message_type; 497 __u8 payload_size; 498 union hv_message_flags message_flags; 499 __u8 reserved[2]; 500 union { 501 __u64 sender; 502 union hv_port_id port; 503 }; 504 } __packed; 505 506 /* Define synthetic interrupt controller message format. */ 507 struct hv_message { 508 struct hv_message_header header; 509 union { 510 __u64 payload[HV_MESSAGE_PAYLOAD_QWORD_COUNT]; 511 } u; 512 } __packed; 513 514 /* Define the synthetic interrupt message page layout. */ 515 struct hv_message_page { 516 struct hv_message sint_message[HV_SYNIC_SINT_COUNT]; 517 } __packed; 518 519 /* Define timer message payload structure. */ 520 struct hv_timer_message_payload { 521 __u32 timer_index; 522 __u32 reserved; 523 __u64 expiration_time; /* When the timer expired */ 524 __u64 delivery_time; /* When the message was delivered */ 525 } __packed; 526 527 /* Define virtual processor assist page structure. */ 528 struct hv_vp_assist_page { 529 __u32 apic_assist; 530 __u32 reserved; 531 __u64 vtl_control[2]; 532 __u64 nested_enlightenments_control[2]; 533 __u32 enlighten_vmentry; 534 __u32 padding; 535 __u64 current_nested_vmcs; 536 } __packed; 537 538 struct hv_enlightened_vmcs { 539 u32 revision_id; 540 u32 abort; 541 542 u16 host_es_selector; 543 u16 host_cs_selector; 544 u16 host_ss_selector; 545 u16 host_ds_selector; 546 u16 host_fs_selector; 547 u16 host_gs_selector; 548 u16 host_tr_selector; 549 550 u16 padding16_1; 551 552 u64 host_ia32_pat; 553 u64 host_ia32_efer; 554 555 u64 host_cr0; 556 u64 host_cr3; 557 u64 host_cr4; 558 559 u64 host_ia32_sysenter_esp; 560 u64 host_ia32_sysenter_eip; 561 u64 host_rip; 562 u32 host_ia32_sysenter_cs; 563 564 u32 pin_based_vm_exec_control; 565 u32 vm_exit_controls; 566 u32 secondary_vm_exec_control; 567 568 u64 io_bitmap_a; 569 u64 io_bitmap_b; 570 u64 msr_bitmap; 571 572 u16 guest_es_selector; 573 u16 guest_cs_selector; 574 u16 guest_ss_selector; 575 u16 guest_ds_selector; 576 u16 guest_fs_selector; 577 u16 guest_gs_selector; 578 u16 guest_ldtr_selector; 579 u16 guest_tr_selector; 580 581 u32 guest_es_limit; 582 u32 guest_cs_limit; 583 u32 guest_ss_limit; 584 u32 guest_ds_limit; 585 u32 guest_fs_limit; 586 u32 guest_gs_limit; 587 u32 guest_ldtr_limit; 588 u32 guest_tr_limit; 589 u32 guest_gdtr_limit; 590 u32 guest_idtr_limit; 591 592 u32 guest_es_ar_bytes; 593 u32 guest_cs_ar_bytes; 594 u32 guest_ss_ar_bytes; 595 u32 guest_ds_ar_bytes; 596 u32 guest_fs_ar_bytes; 597 u32 guest_gs_ar_bytes; 598 u32 guest_ldtr_ar_bytes; 599 u32 guest_tr_ar_bytes; 600 601 u64 guest_es_base; 602 u64 guest_cs_base; 603 u64 guest_ss_base; 604 u64 guest_ds_base; 605 u64 guest_fs_base; 606 u64 guest_gs_base; 607 u64 guest_ldtr_base; 608 u64 guest_tr_base; 609 u64 guest_gdtr_base; 610 u64 guest_idtr_base; 611 612 u64 padding64_1[3]; 613 614 u64 vm_exit_msr_store_addr; 615 u64 vm_exit_msr_load_addr; 616 u64 vm_entry_msr_load_addr; 617 618 u64 cr3_target_value0; 619 u64 cr3_target_value1; 620 u64 cr3_target_value2; 621 u64 cr3_target_value3; 622 623 u32 page_fault_error_code_mask; 624 u32 page_fault_error_code_match; 625 626 u32 cr3_target_count; 627 u32 vm_exit_msr_store_count; 628 u32 vm_exit_msr_load_count; 629 u32 vm_entry_msr_load_count; 630 631 u64 tsc_offset; 632 u64 virtual_apic_page_addr; 633 u64 vmcs_link_pointer; 634 635 u64 guest_ia32_debugctl; 636 u64 guest_ia32_pat; 637 u64 guest_ia32_efer; 638 639 u64 guest_pdptr0; 640 u64 guest_pdptr1; 641 u64 guest_pdptr2; 642 u64 guest_pdptr3; 643 644 u64 guest_pending_dbg_exceptions; 645 u64 guest_sysenter_esp; 646 u64 guest_sysenter_eip; 647 648 u32 guest_activity_state; 649 u32 guest_sysenter_cs; 650 651 u64 cr0_guest_host_mask; 652 u64 cr4_guest_host_mask; 653 u64 cr0_read_shadow; 654 u64 cr4_read_shadow; 655 u64 guest_cr0; 656 u64 guest_cr3; 657 u64 guest_cr4; 658 u64 guest_dr7; 659 660 u64 host_fs_base; 661 u64 host_gs_base; 662 u64 host_tr_base; 663 u64 host_gdtr_base; 664 u64 host_idtr_base; 665 u64 host_rsp; 666 667 u64 ept_pointer; 668 669 u16 virtual_processor_id; 670 u16 padding16_2[3]; 671 672 u64 padding64_2[5]; 673 u64 guest_physical_address; 674 675 u32 vm_instruction_error; 676 u32 vm_exit_reason; 677 u32 vm_exit_intr_info; 678 u32 vm_exit_intr_error_code; 679 u32 idt_vectoring_info_field; 680 u32 idt_vectoring_error_code; 681 u32 vm_exit_instruction_len; 682 u32 vmx_instruction_info; 683 684 u64 exit_qualification; 685 u64 exit_io_instruction_ecx; 686 u64 exit_io_instruction_esi; 687 u64 exit_io_instruction_edi; 688 u64 exit_io_instruction_eip; 689 690 u64 guest_linear_address; 691 u64 guest_rsp; 692 u64 guest_rflags; 693 694 u32 guest_interruptibility_info; 695 u32 cpu_based_vm_exec_control; 696 u32 exception_bitmap; 697 u32 vm_entry_controls; 698 u32 vm_entry_intr_info_field; 699 u32 vm_entry_exception_error_code; 700 u32 vm_entry_instruction_len; 701 u32 tpr_threshold; 702 703 u64 guest_rip; 704 705 u32 hv_clean_fields; 706 u32 hv_padding_32; 707 u32 hv_synthetic_controls; 708 struct { 709 u32 nested_flush_hypercall:1; 710 u32 msr_bitmap:1; 711 u32 reserved:30; 712 } __packed hv_enlightenments_control; 713 u32 hv_vp_id; 714 715 u64 hv_vm_id; 716 u64 partition_assist_page; 717 u64 padding64_4[4]; 718 u64 guest_bndcfgs; 719 u64 padding64_5[7]; 720 u64 xss_exit_bitmap; 721 u64 padding64_6[7]; 722 } __packed; 723 724 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_NONE 0 725 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_IO_BITMAP BIT(0) 726 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_MSR_BITMAP BIT(1) 727 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_GRP2 BIT(2) 728 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_GRP1 BIT(3) 729 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_PROC BIT(4) 730 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_EVENT BIT(5) 731 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_ENTRY BIT(6) 732 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_EXCPN BIT(7) 733 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CRDR BIT(8) 734 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_XLAT BIT(9) 735 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_BASIC BIT(10) 736 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_GRP1 BIT(11) 737 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_GRP2 BIT(12) 738 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_HOST_POINTER BIT(13) 739 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_HOST_GRP1 BIT(14) 740 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_ENLIGHTENMENTSCONTROL BIT(15) 741 742 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL 0xFFFF 743 744 /* Define synthetic interrupt controller flag constants. */ 745 #define HV_EVENT_FLAGS_COUNT (256 * 8) 746 #define HV_EVENT_FLAGS_LONG_COUNT (256 / sizeof(unsigned long)) 747 748 /* 749 * Synthetic timer configuration. 750 */ 751 union hv_stimer_config { 752 u64 as_uint64; 753 struct { 754 u64 enable:1; 755 u64 periodic:1; 756 u64 lazy:1; 757 u64 auto_enable:1; 758 u64 apic_vector:8; 759 u64 direct_mode:1; 760 u64 reserved_z0:3; 761 u64 sintx:4; 762 u64 reserved_z1:44; 763 } __packed; 764 }; 765 766 767 /* Define the synthetic interrupt controller event flags format. */ 768 union hv_synic_event_flags { 769 unsigned long flags[HV_EVENT_FLAGS_LONG_COUNT]; 770 }; 771 772 /* Define SynIC control register. */ 773 union hv_synic_scontrol { 774 u64 as_uint64; 775 struct { 776 u64 enable:1; 777 u64 reserved:63; 778 } __packed; 779 }; 780 781 /* Define synthetic interrupt source. */ 782 union hv_synic_sint { 783 u64 as_uint64; 784 struct { 785 u64 vector:8; 786 u64 reserved1:8; 787 u64 masked:1; 788 u64 auto_eoi:1; 789 u64 reserved2:46; 790 } __packed; 791 }; 792 793 /* Define the format of the SIMP register */ 794 union hv_synic_simp { 795 u64 as_uint64; 796 struct { 797 u64 simp_enabled:1; 798 u64 preserved:11; 799 u64 base_simp_gpa:52; 800 } __packed; 801 }; 802 803 /* Define the format of the SIEFP register */ 804 union hv_synic_siefp { 805 u64 as_uint64; 806 struct { 807 u64 siefp_enabled:1; 808 u64 preserved:11; 809 u64 base_siefp_gpa:52; 810 } __packed; 811 }; 812 813 struct hv_vpset { 814 u64 format; 815 u64 valid_bank_mask; 816 u64 bank_contents[]; 817 } __packed; 818 819 /* HvCallSendSyntheticClusterIpi hypercall */ 820 struct hv_send_ipi { 821 u32 vector; 822 u32 reserved; 823 u64 cpu_mask; 824 } __packed; 825 826 /* HvCallSendSyntheticClusterIpiEx hypercall */ 827 struct hv_send_ipi_ex { 828 u32 vector; 829 u32 reserved; 830 struct hv_vpset vp_set; 831 } __packed; 832 833 /* HvFlushGuestPhysicalAddressSpace hypercalls */ 834 struct hv_guest_mapping_flush { 835 u64 address_space; 836 u64 flags; 837 } __packed; 838 839 /* 840 * HV_MAX_FLUSH_PAGES = "additional_pages" + 1. It's limited 841 * by the bitwidth of "additional_pages" in union hv_gpa_page_range. 842 */ 843 #define HV_MAX_FLUSH_PAGES (2048) 844 845 /* HvFlushGuestPhysicalAddressList hypercall */ 846 union hv_gpa_page_range { 847 u64 address_space; 848 struct { 849 u64 additional_pages:11; 850 u64 largepage:1; 851 u64 basepfn:52; 852 } page; 853 }; 854 855 /* 856 * All input flush parameters should be in single page. The max flush 857 * count is equal with how many entries of union hv_gpa_page_range can 858 * be populated into the input parameter page. 859 */ 860 #define HV_MAX_FLUSH_REP_COUNT ((HV_HYP_PAGE_SIZE - 2 * sizeof(u64)) / \ 861 sizeof(union hv_gpa_page_range)) 862 863 struct hv_guest_mapping_flush_list { 864 u64 address_space; 865 u64 flags; 866 union hv_gpa_page_range gpa_list[HV_MAX_FLUSH_REP_COUNT]; 867 }; 868 869 /* HvFlushVirtualAddressSpace, HvFlushVirtualAddressList hypercalls */ 870 struct hv_tlb_flush { 871 u64 address_space; 872 u64 flags; 873 u64 processor_mask; 874 u64 gva_list[]; 875 } __packed; 876 877 /* HvFlushVirtualAddressSpaceEx, HvFlushVirtualAddressListEx hypercalls */ 878 struct hv_tlb_flush_ex { 879 u64 address_space; 880 u64 flags; 881 struct hv_vpset hv_vp_set; 882 u64 gva_list[]; 883 } __packed; 884 885 #endif 886