xref: /openbmc/linux/arch/x86/include/asm/gsseg.h (revision ae53fa18)
1*ae53fa18SH. Peter Anvin (Intel) /* SPDX-License-Identifier: GPL-2.0-only */
2*ae53fa18SH. Peter Anvin (Intel) #ifndef _ASM_X86_GSSEG_H
3*ae53fa18SH. Peter Anvin (Intel) #define _ASM_X86_GSSEG_H
4*ae53fa18SH. Peter Anvin (Intel) 
5*ae53fa18SH. Peter Anvin (Intel) #include <linux/types.h>
6*ae53fa18SH. Peter Anvin (Intel) 
7*ae53fa18SH. Peter Anvin (Intel) #include <asm/asm.h>
8*ae53fa18SH. Peter Anvin (Intel) #include <asm/cpufeature.h>
9*ae53fa18SH. Peter Anvin (Intel) #include <asm/alternative.h>
10*ae53fa18SH. Peter Anvin (Intel) #include <asm/processor.h>
11*ae53fa18SH. Peter Anvin (Intel) #include <asm/nops.h>
12*ae53fa18SH. Peter Anvin (Intel) 
13*ae53fa18SH. Peter Anvin (Intel) #ifdef CONFIG_X86_64
14*ae53fa18SH. Peter Anvin (Intel) 
15*ae53fa18SH. Peter Anvin (Intel) extern asmlinkage void asm_load_gs_index(u16 selector);
16*ae53fa18SH. Peter Anvin (Intel) 
17*ae53fa18SH. Peter Anvin (Intel) static inline void native_load_gs_index(unsigned int selector)
18*ae53fa18SH. Peter Anvin (Intel) {
19*ae53fa18SH. Peter Anvin (Intel) 	unsigned long flags;
20*ae53fa18SH. Peter Anvin (Intel) 
21*ae53fa18SH. Peter Anvin (Intel) 	local_irq_save(flags);
22*ae53fa18SH. Peter Anvin (Intel) 	asm_load_gs_index(selector);
23*ae53fa18SH. Peter Anvin (Intel) 	local_irq_restore(flags);
24*ae53fa18SH. Peter Anvin (Intel) }
25*ae53fa18SH. Peter Anvin (Intel) 
26*ae53fa18SH. Peter Anvin (Intel) #endif /* CONFIG_X86_64 */
27*ae53fa18SH. Peter Anvin (Intel) 
28*ae53fa18SH. Peter Anvin (Intel) #ifndef CONFIG_PARAVIRT_XXL
29*ae53fa18SH. Peter Anvin (Intel) 
30*ae53fa18SH. Peter Anvin (Intel) static inline void load_gs_index(unsigned int selector)
31*ae53fa18SH. Peter Anvin (Intel) {
32*ae53fa18SH. Peter Anvin (Intel) #ifdef CONFIG_X86_64
33*ae53fa18SH. Peter Anvin (Intel) 	native_load_gs_index(selector);
34*ae53fa18SH. Peter Anvin (Intel) #else
35*ae53fa18SH. Peter Anvin (Intel) 	loadsegment(gs, selector);
36*ae53fa18SH. Peter Anvin (Intel) #endif
37*ae53fa18SH. Peter Anvin (Intel) }
38*ae53fa18SH. Peter Anvin (Intel) 
39*ae53fa18SH. Peter Anvin (Intel) #endif /* CONFIG_PARAVIRT_XXL */
40*ae53fa18SH. Peter Anvin (Intel) 
41*ae53fa18SH. Peter Anvin (Intel) #endif /* _ASM_X86_GSSEG_H */
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