1 #ifndef _ASM_X86_GART_H 2 #define _ASM_X86_GART_H 3 4 #include <asm/e820.h> 5 6 extern void set_up_gart_resume(u32, u32); 7 8 extern int fallback_aper_order; 9 extern int fallback_aper_force; 10 extern int fix_aperture; 11 12 /* PTE bits. */ 13 #define GPTE_VALID 1 14 #define GPTE_COHERENT 2 15 16 /* Aperture control register bits. */ 17 #define GARTEN (1<<0) 18 #define DISGARTCPU (1<<4) 19 #define DISGARTIO (1<<5) 20 21 /* GART cache control register bits. */ 22 #define INVGART (1<<0) 23 #define GARTPTEERR (1<<1) 24 25 /* K8 On-cpu GART registers */ 26 #define AMD64_GARTAPERTURECTL 0x90 27 #define AMD64_GARTAPERTUREBASE 0x94 28 #define AMD64_GARTTABLEBASE 0x98 29 #define AMD64_GARTCACHECTL 0x9c 30 #define AMD64_GARTEN (1<<0) 31 32 extern int agp_amd64_init(void); 33 34 static inline void enable_gart_translation(struct pci_dev *dev, u64 addr) 35 { 36 u32 tmp, ctl; 37 38 /* address of the mappings table */ 39 addr >>= 12; 40 tmp = (u32) addr<<4; 41 tmp &= ~0xf; 42 pci_write_config_dword(dev, AMD64_GARTTABLEBASE, tmp); 43 44 /* Enable GART translation for this hammer. */ 45 pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &ctl); 46 ctl |= GARTEN; 47 ctl &= ~(DISGARTCPU | DISGARTIO); 48 pci_write_config_dword(dev, AMD64_GARTAPERTURECTL, ctl); 49 } 50 51 static inline int aperture_valid(u64 aper_base, u32 aper_size, u32 min_size) 52 { 53 if (!aper_base) 54 return 0; 55 56 if (aper_base + aper_size > 0x100000000ULL) { 57 printk(KERN_INFO "Aperture beyond 4GB. Ignoring.\n"); 58 return 0; 59 } 60 if (e820_any_mapped(aper_base, aper_base + aper_size, E820_RAM)) { 61 printk(KERN_INFO "Aperture pointing to e820 RAM. Ignoring.\n"); 62 return 0; 63 } 64 if (aper_size < min_size) { 65 printk(KERN_INFO "Aperture too small (%d MB) than (%d MB)\n", 66 aper_size>>20, min_size>>20); 67 return 0; 68 } 69 70 return 1; 71 } 72 73 #endif /* _ASM_X86_GART_H */ 74