1b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */
2bb898558SAl Viro /*
3bb898558SAl Viro * linux/include/asm/dma.h: Defines for using and allocating dma channels.
4bb898558SAl Viro * Written by Hennus Bergman, 1992.
5bb898558SAl Viro * High DMA channel support & info by Hannu Savolainen
6bb898558SAl Viro * and John Boyd, Nov. 1992.
7bb898558SAl Viro */
8bb898558SAl Viro
91965aae3SH. Peter Anvin #ifndef _ASM_X86_DMA_H
101965aae3SH. Peter Anvin #define _ASM_X86_DMA_H
11bb898558SAl Viro
12bb898558SAl Viro #include <linux/spinlock.h> /* And spinlocks */
13bb898558SAl Viro #include <asm/io.h> /* need byte IO */
14bb898558SAl Viro
15bb898558SAl Viro #ifdef HAVE_REALLY_SLOW_DMA_CONTROLLER
16bb898558SAl Viro #define dma_outb outb_p
17bb898558SAl Viro #else
18bb898558SAl Viro #define dma_outb outb
19bb898558SAl Viro #endif
20bb898558SAl Viro
21bb898558SAl Viro #define dma_inb inb
22bb898558SAl Viro
23bb898558SAl Viro /*
24bb898558SAl Viro * NOTES about DMA transfers:
25bb898558SAl Viro *
26bb898558SAl Viro * controller 1: channels 0-3, byte operations, ports 00-1F
27bb898558SAl Viro * controller 2: channels 4-7, word operations, ports C0-DF
28bb898558SAl Viro *
29bb898558SAl Viro * - ALL registers are 8 bits only, regardless of transfer size
30bb898558SAl Viro * - channel 4 is not used - cascades 1 into 2.
31bb898558SAl Viro * - channels 0-3 are byte - addresses/counts are for physical bytes
32bb898558SAl Viro * - channels 5-7 are word - addresses/counts are for physical words
33bb898558SAl Viro * - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries
34bb898558SAl Viro * - transfer count loaded to registers is 1 less than actual count
35bb898558SAl Viro * - controller 2 offsets are all even (2x offsets for controller 1)
36bb898558SAl Viro * - page registers for 5-7 don't use data bit 0, represent 128K pages
37bb898558SAl Viro * - page registers for 0-3 use bit 0, represent 64K pages
38bb898558SAl Viro *
39bb898558SAl Viro * DMA transfers are limited to the lower 16MB of _physical_ memory.
40bb898558SAl Viro * Note that addresses loaded into registers must be _physical_ addresses,
41bb898558SAl Viro * not logical addresses (which may differ if paging is active).
42bb898558SAl Viro *
43bb898558SAl Viro * Address mapping for channels 0-3:
44bb898558SAl Viro *
45bb898558SAl Viro * A23 ... A16 A15 ... A8 A7 ... A0 (Physical addresses)
46bb898558SAl Viro * | ... | | ... | | ... |
47bb898558SAl Viro * | ... | | ... | | ... |
48bb898558SAl Viro * | ... | | ... | | ... |
49bb898558SAl Viro * P7 ... P0 A7 ... A0 A7 ... A0
50bb898558SAl Viro * | Page | Addr MSB | Addr LSB | (DMA registers)
51bb898558SAl Viro *
52bb898558SAl Viro * Address mapping for channels 5-7:
53bb898558SAl Viro *
54bb898558SAl Viro * A23 ... A17 A16 A15 ... A9 A8 A7 ... A1 A0 (Physical addresses)
55bb898558SAl Viro * | ... | \ \ ... \ \ \ ... \ \
56bb898558SAl Viro * | ... | \ \ ... \ \ \ ... \ (not used)
57bb898558SAl Viro * | ... | \ \ ... \ \ \ ... \
58bb898558SAl Viro * P7 ... P1 (0) A7 A6 ... A0 A7 A6 ... A0
59bb898558SAl Viro * | Page | Addr MSB | Addr LSB | (DMA registers)
60bb898558SAl Viro *
61bb898558SAl Viro * Again, channels 5-7 transfer _physical_ words (16 bits), so addresses
62bb898558SAl Viro * and counts _must_ be word-aligned (the lowest address bit is _ignored_ at
63bb898558SAl Viro * the hardware level, so odd-byte transfers aren't possible).
64bb898558SAl Viro *
65bb898558SAl Viro * Transfer count (_not # bytes_) is limited to 64K, represented as actual
66bb898558SAl Viro * count - 1 : 64K => 0xFFFF, 1 => 0x0000. Thus, count is always 1 or more,
67bb898558SAl Viro * and up to 128K bytes may be transferred on channels 5-7 in one operation.
68bb898558SAl Viro *
69bb898558SAl Viro */
70bb898558SAl Viro
71bb898558SAl Viro #define MAX_DMA_CHANNELS 8
72bb898558SAl Viro
73744baba0STejun Heo /* 16MB ISA DMA zone */
74c072b90cSXishi Qiu #define MAX_DMA_PFN ((16UL * 1024 * 1024) >> PAGE_SHIFT)
75744baba0STejun Heo
76bb898558SAl Viro /* 4GB broken PCI/AGP hardware bus master zone */
7788743470SAlexander Dahl #define MAX_DMA32_PFN (1UL << (32 - PAGE_SHIFT))
78bb898558SAl Viro
791b7e03efSTejun Heo #ifdef CONFIG_X86_32
801b7e03efSTejun Heo /* The maximum address that we can perform a DMA transfer to on this platform */
811b7e03efSTejun Heo #define MAX_DMA_ADDRESS (PAGE_OFFSET + 0x1000000)
821b7e03efSTejun Heo #else
83bb898558SAl Viro /* Compat define for old dma zone */
84bb898558SAl Viro #define MAX_DMA_ADDRESS ((unsigned long)__va(MAX_DMA_PFN << PAGE_SHIFT))
85bb898558SAl Viro #endif
86bb898558SAl Viro
87bb898558SAl Viro /* 8237 DMA controllers */
88bb898558SAl Viro #define IO_DMA1_BASE 0x00 /* 8 bit slave DMA, channels 0..3 */
89bb898558SAl Viro #define IO_DMA2_BASE 0xC0 /* 16 bit master DMA, ch 4(=slave input)..7 */
90bb898558SAl Viro
91bb898558SAl Viro /* DMA controller registers */
92bb898558SAl Viro #define DMA1_CMD_REG 0x08 /* command register (w) */
93bb898558SAl Viro #define DMA1_STAT_REG 0x08 /* status register (r) */
94bb898558SAl Viro #define DMA1_REQ_REG 0x09 /* request register (w) */
95bb898558SAl Viro #define DMA1_MASK_REG 0x0A /* single-channel mask (w) */
96bb898558SAl Viro #define DMA1_MODE_REG 0x0B /* mode register (w) */
97bb898558SAl Viro #define DMA1_CLEAR_FF_REG 0x0C /* clear pointer flip-flop (w) */
98bb898558SAl Viro #define DMA1_TEMP_REG 0x0D /* Temporary Register (r) */
99bb898558SAl Viro #define DMA1_RESET_REG 0x0D /* Master Clear (w) */
100bb898558SAl Viro #define DMA1_CLR_MASK_REG 0x0E /* Clear Mask */
101bb898558SAl Viro #define DMA1_MASK_ALL_REG 0x0F /* all-channels mask (w) */
102bb898558SAl Viro
103bb898558SAl Viro #define DMA2_CMD_REG 0xD0 /* command register (w) */
104bb898558SAl Viro #define DMA2_STAT_REG 0xD0 /* status register (r) */
105bb898558SAl Viro #define DMA2_REQ_REG 0xD2 /* request register (w) */
106bb898558SAl Viro #define DMA2_MASK_REG 0xD4 /* single-channel mask (w) */
107bb898558SAl Viro #define DMA2_MODE_REG 0xD6 /* mode register (w) */
108bb898558SAl Viro #define DMA2_CLEAR_FF_REG 0xD8 /* clear pointer flip-flop (w) */
109bb898558SAl Viro #define DMA2_TEMP_REG 0xDA /* Temporary Register (r) */
110bb898558SAl Viro #define DMA2_RESET_REG 0xDA /* Master Clear (w) */
111bb898558SAl Viro #define DMA2_CLR_MASK_REG 0xDC /* Clear Mask */
112bb898558SAl Viro #define DMA2_MASK_ALL_REG 0xDE /* all-channels mask (w) */
113bb898558SAl Viro
114bb898558SAl Viro #define DMA_ADDR_0 0x00 /* DMA address registers */
115bb898558SAl Viro #define DMA_ADDR_1 0x02
116bb898558SAl Viro #define DMA_ADDR_2 0x04
117bb898558SAl Viro #define DMA_ADDR_3 0x06
118bb898558SAl Viro #define DMA_ADDR_4 0xC0
119bb898558SAl Viro #define DMA_ADDR_5 0xC4
120bb898558SAl Viro #define DMA_ADDR_6 0xC8
121bb898558SAl Viro #define DMA_ADDR_7 0xCC
122bb898558SAl Viro
123bb898558SAl Viro #define DMA_CNT_0 0x01 /* DMA count registers */
124bb898558SAl Viro #define DMA_CNT_1 0x03
125bb898558SAl Viro #define DMA_CNT_2 0x05
126bb898558SAl Viro #define DMA_CNT_3 0x07
127bb898558SAl Viro #define DMA_CNT_4 0xC2
128bb898558SAl Viro #define DMA_CNT_5 0xC6
129bb898558SAl Viro #define DMA_CNT_6 0xCA
130bb898558SAl Viro #define DMA_CNT_7 0xCE
131bb898558SAl Viro
132bb898558SAl Viro #define DMA_PAGE_0 0x87 /* DMA page registers */
133bb898558SAl Viro #define DMA_PAGE_1 0x83
134bb898558SAl Viro #define DMA_PAGE_2 0x81
135bb898558SAl Viro #define DMA_PAGE_3 0x82
136bb898558SAl Viro #define DMA_PAGE_5 0x8B
137bb898558SAl Viro #define DMA_PAGE_6 0x89
138bb898558SAl Viro #define DMA_PAGE_7 0x8A
139bb898558SAl Viro
140bb898558SAl Viro /* I/O to memory, no autoinit, increment, single mode */
141bb898558SAl Viro #define DMA_MODE_READ 0x44
142bb898558SAl Viro /* memory to I/O, no autoinit, increment, single mode */
143bb898558SAl Viro #define DMA_MODE_WRITE 0x48
144bb898558SAl Viro /* pass thru DREQ->HRQ, DACK<-HLDA only */
145bb898558SAl Viro #define DMA_MODE_CASCADE 0xC0
146bb898558SAl Viro
147bb898558SAl Viro #define DMA_AUTOINIT 0x10
148bb898558SAl Viro
149bb898558SAl Viro
1501c00f016SDavid Rientjes #ifdef CONFIG_ISA_DMA_API
151bb898558SAl Viro extern spinlock_t dma_spin_lock;
152bb898558SAl Viro
claim_dma_lock(void)153bb898558SAl Viro static inline unsigned long claim_dma_lock(void)
154bb898558SAl Viro {
155bb898558SAl Viro unsigned long flags;
156bb898558SAl Viro spin_lock_irqsave(&dma_spin_lock, flags);
157bb898558SAl Viro return flags;
158bb898558SAl Viro }
159bb898558SAl Viro
release_dma_lock(unsigned long flags)160bb898558SAl Viro static inline void release_dma_lock(unsigned long flags)
161bb898558SAl Viro {
162bb898558SAl Viro spin_unlock_irqrestore(&dma_spin_lock, flags);
163bb898558SAl Viro }
1641c00f016SDavid Rientjes #endif /* CONFIG_ISA_DMA_API */
165bb898558SAl Viro
166bb898558SAl Viro /* enable/disable a specific DMA channel */
enable_dma(unsigned int dmanr)167bb898558SAl Viro static inline void enable_dma(unsigned int dmanr)
168bb898558SAl Viro {
169bb898558SAl Viro if (dmanr <= 3)
170bb898558SAl Viro dma_outb(dmanr, DMA1_MASK_REG);
171bb898558SAl Viro else
172bb898558SAl Viro dma_outb(dmanr & 3, DMA2_MASK_REG);
173bb898558SAl Viro }
174bb898558SAl Viro
disable_dma(unsigned int dmanr)175bb898558SAl Viro static inline void disable_dma(unsigned int dmanr)
176bb898558SAl Viro {
177bb898558SAl Viro if (dmanr <= 3)
178bb898558SAl Viro dma_outb(dmanr | 4, DMA1_MASK_REG);
179bb898558SAl Viro else
180bb898558SAl Viro dma_outb((dmanr & 3) | 4, DMA2_MASK_REG);
181bb898558SAl Viro }
182bb898558SAl Viro
183bb898558SAl Viro /* Clear the 'DMA Pointer Flip Flop'.
184bb898558SAl Viro * Write 0 for LSB/MSB, 1 for MSB/LSB access.
185bb898558SAl Viro * Use this once to initialize the FF to a known state.
186bb898558SAl Viro * After that, keep track of it. :-)
187bb898558SAl Viro * --- In order to do that, the DMA routines below should ---
188bb898558SAl Viro * --- only be used while holding the DMA lock ! ---
189bb898558SAl Viro */
clear_dma_ff(unsigned int dmanr)190bb898558SAl Viro static inline void clear_dma_ff(unsigned int dmanr)
191bb898558SAl Viro {
192bb898558SAl Viro if (dmanr <= 3)
193bb898558SAl Viro dma_outb(0, DMA1_CLEAR_FF_REG);
194bb898558SAl Viro else
195bb898558SAl Viro dma_outb(0, DMA2_CLEAR_FF_REG);
196bb898558SAl Viro }
197bb898558SAl Viro
198bb898558SAl Viro /* set mode (above) for a specific DMA channel */
set_dma_mode(unsigned int dmanr,char mode)199bb898558SAl Viro static inline void set_dma_mode(unsigned int dmanr, char mode)
200bb898558SAl Viro {
201bb898558SAl Viro if (dmanr <= 3)
202bb898558SAl Viro dma_outb(mode | dmanr, DMA1_MODE_REG);
203bb898558SAl Viro else
204bb898558SAl Viro dma_outb(mode | (dmanr & 3), DMA2_MODE_REG);
205bb898558SAl Viro }
206bb898558SAl Viro
207bb898558SAl Viro /* Set only the page register bits of the transfer address.
208bb898558SAl Viro * This is used for successive transfers when we know the contents of
209bb898558SAl Viro * the lower 16 bits of the DMA current address register, but a 64k boundary
210bb898558SAl Viro * may have been crossed.
211bb898558SAl Viro */
set_dma_page(unsigned int dmanr,char pagenr)212bb898558SAl Viro static inline void set_dma_page(unsigned int dmanr, char pagenr)
213bb898558SAl Viro {
214bb898558SAl Viro switch (dmanr) {
215bb898558SAl Viro case 0:
216bb898558SAl Viro dma_outb(pagenr, DMA_PAGE_0);
217bb898558SAl Viro break;
218bb898558SAl Viro case 1:
219bb898558SAl Viro dma_outb(pagenr, DMA_PAGE_1);
220bb898558SAl Viro break;
221bb898558SAl Viro case 2:
222bb898558SAl Viro dma_outb(pagenr, DMA_PAGE_2);
223bb898558SAl Viro break;
224bb898558SAl Viro case 3:
225bb898558SAl Viro dma_outb(pagenr, DMA_PAGE_3);
226bb898558SAl Viro break;
227bb898558SAl Viro case 5:
228bb898558SAl Viro dma_outb(pagenr & 0xfe, DMA_PAGE_5);
229bb898558SAl Viro break;
230bb898558SAl Viro case 6:
231bb898558SAl Viro dma_outb(pagenr & 0xfe, DMA_PAGE_6);
232bb898558SAl Viro break;
233bb898558SAl Viro case 7:
234bb898558SAl Viro dma_outb(pagenr & 0xfe, DMA_PAGE_7);
235bb898558SAl Viro break;
236bb898558SAl Viro }
237bb898558SAl Viro }
238bb898558SAl Viro
239bb898558SAl Viro
240bb898558SAl Viro /* Set transfer address & page bits for specific DMA channel.
241bb898558SAl Viro * Assumes dma flipflop is clear.
242bb898558SAl Viro */
set_dma_addr(unsigned int dmanr,unsigned int a)243bb898558SAl Viro static inline void set_dma_addr(unsigned int dmanr, unsigned int a)
244bb898558SAl Viro {
245bb898558SAl Viro set_dma_page(dmanr, a>>16);
246bb898558SAl Viro if (dmanr <= 3) {
247bb898558SAl Viro dma_outb(a & 0xff, ((dmanr & 3) << 1) + IO_DMA1_BASE);
248bb898558SAl Viro dma_outb((a >> 8) & 0xff, ((dmanr & 3) << 1) + IO_DMA1_BASE);
249bb898558SAl Viro } else {
250bb898558SAl Viro dma_outb((a >> 1) & 0xff, ((dmanr & 3) << 2) + IO_DMA2_BASE);
251bb898558SAl Viro dma_outb((a >> 9) & 0xff, ((dmanr & 3) << 2) + IO_DMA2_BASE);
252bb898558SAl Viro }
253bb898558SAl Viro }
254bb898558SAl Viro
255bb898558SAl Viro
256bb898558SAl Viro /* Set transfer size (max 64k for DMA0..3, 128k for DMA5..7) for
257bb898558SAl Viro * a specific DMA channel.
258bb898558SAl Viro * You must ensure the parameters are valid.
259bb898558SAl Viro * NOTE: from a manual: "the number of transfers is one more
260bb898558SAl Viro * than the initial word count"! This is taken into account.
261bb898558SAl Viro * Assumes dma flip-flop is clear.
262bb898558SAl Viro * NOTE 2: "count" represents _bytes_ and must be even for channels 5-7.
263bb898558SAl Viro */
set_dma_count(unsigned int dmanr,unsigned int count)264bb898558SAl Viro static inline void set_dma_count(unsigned int dmanr, unsigned int count)
265bb898558SAl Viro {
266bb898558SAl Viro count--;
267bb898558SAl Viro if (dmanr <= 3) {
268bb898558SAl Viro dma_outb(count & 0xff, ((dmanr & 3) << 1) + 1 + IO_DMA1_BASE);
269bb898558SAl Viro dma_outb((count >> 8) & 0xff,
270bb898558SAl Viro ((dmanr & 3) << 1) + 1 + IO_DMA1_BASE);
271bb898558SAl Viro } else {
272bb898558SAl Viro dma_outb((count >> 1) & 0xff,
273bb898558SAl Viro ((dmanr & 3) << 2) + 2 + IO_DMA2_BASE);
274bb898558SAl Viro dma_outb((count >> 9) & 0xff,
275bb898558SAl Viro ((dmanr & 3) << 2) + 2 + IO_DMA2_BASE);
276bb898558SAl Viro }
277bb898558SAl Viro }
278bb898558SAl Viro
279bb898558SAl Viro
280bb898558SAl Viro /* Get DMA residue count. After a DMA transfer, this
281bb898558SAl Viro * should return zero. Reading this while a DMA transfer is
282bb898558SAl Viro * still in progress will return unpredictable results.
283bb898558SAl Viro * If called before the channel has been used, it may return 1.
284bb898558SAl Viro * Otherwise, it returns the number of _bytes_ left to transfer.
285bb898558SAl Viro *
286bb898558SAl Viro * Assumes DMA flip-flop is clear.
287bb898558SAl Viro */
get_dma_residue(unsigned int dmanr)288bb898558SAl Viro static inline int get_dma_residue(unsigned int dmanr)
289bb898558SAl Viro {
290bb898558SAl Viro unsigned int io_port;
291bb898558SAl Viro /* using short to get 16-bit wrap around */
292bb898558SAl Viro unsigned short count;
293bb898558SAl Viro
294bb898558SAl Viro io_port = (dmanr <= 3) ? ((dmanr & 3) << 1) + 1 + IO_DMA1_BASE
295bb898558SAl Viro : ((dmanr & 3) << 2) + 2 + IO_DMA2_BASE;
296bb898558SAl Viro
297bb898558SAl Viro count = 1 + dma_inb(io_port);
298bb898558SAl Viro count += dma_inb(io_port) << 8;
299bb898558SAl Viro
300bb898558SAl Viro return (dmanr <= 3) ? count : (count << 1);
301bb898558SAl Viro }
302bb898558SAl Viro
303bb898558SAl Viro
3041c00f016SDavid Rientjes /* These are in kernel/dma.c because x86 uses CONFIG_GENERIC_ISA_DMA */
3051c00f016SDavid Rientjes #ifdef CONFIG_ISA_DMA_API
306bb898558SAl Viro extern int request_dma(unsigned int dmanr, const char *device_id);
307bb898558SAl Viro extern void free_dma(unsigned int dmanr);
3081c00f016SDavid Rientjes #endif
309bb898558SAl Viro
3101965aae3SH. Peter Anvin #endif /* _ASM_X86_DMA_H */
311