1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _ASM_X86_DESC_H 3 #define _ASM_X86_DESC_H 4 5 #include <asm/desc_defs.h> 6 #include <asm/ldt.h> 7 #include <asm/mmu.h> 8 #include <asm/fixmap.h> 9 #include <asm/irq_vectors.h> 10 #include <asm/cpu_entry_area.h> 11 12 #include <linux/smp.h> 13 #include <linux/percpu.h> 14 15 static inline void fill_ldt(struct desc_struct *desc, const struct user_desc *info) 16 { 17 desc->limit0 = info->limit & 0x0ffff; 18 19 desc->base0 = (info->base_addr & 0x0000ffff); 20 desc->base1 = (info->base_addr & 0x00ff0000) >> 16; 21 22 desc->type = (info->read_exec_only ^ 1) << 1; 23 desc->type |= info->contents << 2; 24 25 desc->s = 1; 26 desc->dpl = 0x3; 27 desc->p = info->seg_not_present ^ 1; 28 desc->limit1 = (info->limit & 0xf0000) >> 16; 29 desc->avl = info->useable; 30 desc->d = info->seg_32bit; 31 desc->g = info->limit_in_pages; 32 33 desc->base2 = (info->base_addr & 0xff000000) >> 24; 34 /* 35 * Don't allow setting of the lm bit. It would confuse 36 * user_64bit_mode and would get overridden by sysret anyway. 37 */ 38 desc->l = 0; 39 } 40 41 extern struct desc_ptr idt_descr; 42 extern gate_desc idt_table[]; 43 extern const struct desc_ptr debug_idt_descr; 44 extern gate_desc debug_idt_table[]; 45 46 struct gdt_page { 47 struct desc_struct gdt[GDT_ENTRIES]; 48 } __attribute__((aligned(PAGE_SIZE))); 49 50 DECLARE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page); 51 52 /* Provide the original GDT */ 53 static inline struct desc_struct *get_cpu_gdt_rw(unsigned int cpu) 54 { 55 return per_cpu(gdt_page, cpu).gdt; 56 } 57 58 /* Provide the current original GDT */ 59 static inline struct desc_struct *get_current_gdt_rw(void) 60 { 61 return this_cpu_ptr(&gdt_page)->gdt; 62 } 63 64 /* Provide the fixmap address of the remapped GDT */ 65 static inline struct desc_struct *get_cpu_gdt_ro(int cpu) 66 { 67 return (struct desc_struct *)&get_cpu_entry_area(cpu)->gdt; 68 } 69 70 /* Provide the current read-only GDT */ 71 static inline struct desc_struct *get_current_gdt_ro(void) 72 { 73 return get_cpu_gdt_ro(smp_processor_id()); 74 } 75 76 /* Provide the physical address of the GDT page. */ 77 static inline phys_addr_t get_cpu_gdt_paddr(unsigned int cpu) 78 { 79 return per_cpu_ptr_to_phys(get_cpu_gdt_rw(cpu)); 80 } 81 82 static inline void pack_gate(gate_desc *gate, unsigned type, unsigned long func, 83 unsigned dpl, unsigned ist, unsigned seg) 84 { 85 gate->offset_low = (u16) func; 86 gate->bits.p = 1; 87 gate->bits.dpl = dpl; 88 gate->bits.zero = 0; 89 gate->bits.type = type; 90 gate->offset_middle = (u16) (func >> 16); 91 #ifdef CONFIG_X86_64 92 gate->segment = __KERNEL_CS; 93 gate->bits.ist = ist; 94 gate->reserved = 0; 95 gate->offset_high = (u32) (func >> 32); 96 #else 97 gate->segment = seg; 98 gate->bits.ist = 0; 99 #endif 100 } 101 102 static inline int desc_empty(const void *ptr) 103 { 104 const u32 *desc = ptr; 105 106 return !(desc[0] | desc[1]); 107 } 108 109 #ifdef CONFIG_PARAVIRT 110 #include <asm/paravirt.h> 111 #else 112 #define load_TR_desc() native_load_tr_desc() 113 #define load_gdt(dtr) native_load_gdt(dtr) 114 #define load_idt(dtr) native_load_idt(dtr) 115 #define load_tr(tr) asm volatile("ltr %0"::"m" (tr)) 116 #define load_ldt(ldt) asm volatile("lldt %0"::"m" (ldt)) 117 118 #define store_gdt(dtr) native_store_gdt(dtr) 119 #define store_tr(tr) (tr = native_store_tr()) 120 121 #define load_TLS(t, cpu) native_load_tls(t, cpu) 122 #define set_ldt native_set_ldt 123 124 #define write_ldt_entry(dt, entry, desc) native_write_ldt_entry(dt, entry, desc) 125 #define write_gdt_entry(dt, entry, desc, type) native_write_gdt_entry(dt, entry, desc, type) 126 #define write_idt_entry(dt, entry, g) native_write_idt_entry(dt, entry, g) 127 128 static inline void paravirt_alloc_ldt(struct desc_struct *ldt, unsigned entries) 129 { 130 } 131 132 static inline void paravirt_free_ldt(struct desc_struct *ldt, unsigned entries) 133 { 134 } 135 #endif /* CONFIG_PARAVIRT */ 136 137 #define store_ldt(ldt) asm("sldt %0" : "=m"(ldt)) 138 139 static inline void native_write_idt_entry(gate_desc *idt, int entry, const gate_desc *gate) 140 { 141 memcpy(&idt[entry], gate, sizeof(*gate)); 142 } 143 144 static inline void native_write_ldt_entry(struct desc_struct *ldt, int entry, const void *desc) 145 { 146 memcpy(&ldt[entry], desc, 8); 147 } 148 149 static inline void 150 native_write_gdt_entry(struct desc_struct *gdt, int entry, const void *desc, int type) 151 { 152 unsigned int size; 153 154 switch (type) { 155 case DESC_TSS: size = sizeof(tss_desc); break; 156 case DESC_LDT: size = sizeof(ldt_desc); break; 157 default: size = sizeof(*gdt); break; 158 } 159 160 memcpy(&gdt[entry], desc, size); 161 } 162 163 static inline void set_tssldt_descriptor(void *d, unsigned long addr, 164 unsigned type, unsigned size) 165 { 166 struct ldttss_desc *desc = d; 167 168 memset(desc, 0, sizeof(*desc)); 169 170 desc->limit0 = (u16) size; 171 desc->base0 = (u16) addr; 172 desc->base1 = (addr >> 16) & 0xFF; 173 desc->type = type; 174 desc->p = 1; 175 desc->limit1 = (size >> 16) & 0xF; 176 desc->base2 = (addr >> 24) & 0xFF; 177 #ifdef CONFIG_X86_64 178 desc->base3 = (u32) (addr >> 32); 179 #endif 180 } 181 182 static inline void __set_tss_desc(unsigned cpu, unsigned int entry, struct x86_hw_tss *addr) 183 { 184 struct desc_struct *d = get_cpu_gdt_rw(cpu); 185 tss_desc tss; 186 187 set_tssldt_descriptor(&tss, (unsigned long)addr, DESC_TSS, 188 __KERNEL_TSS_LIMIT); 189 write_gdt_entry(d, entry, &tss, DESC_TSS); 190 } 191 192 #define set_tss_desc(cpu, addr) __set_tss_desc(cpu, GDT_ENTRY_TSS, addr) 193 194 static inline void native_set_ldt(const void *addr, unsigned int entries) 195 { 196 if (likely(entries == 0)) 197 asm volatile("lldt %w0"::"q" (0)); 198 else { 199 unsigned cpu = smp_processor_id(); 200 ldt_desc ldt; 201 202 set_tssldt_descriptor(&ldt, (unsigned long)addr, DESC_LDT, 203 entries * LDT_ENTRY_SIZE - 1); 204 write_gdt_entry(get_cpu_gdt_rw(cpu), GDT_ENTRY_LDT, 205 &ldt, DESC_LDT); 206 asm volatile("lldt %w0"::"q" (GDT_ENTRY_LDT*8)); 207 } 208 } 209 210 static inline void native_load_gdt(const struct desc_ptr *dtr) 211 { 212 asm volatile("lgdt %0"::"m" (*dtr)); 213 } 214 215 static inline void native_load_idt(const struct desc_ptr *dtr) 216 { 217 asm volatile("lidt %0"::"m" (*dtr)); 218 } 219 220 static inline void native_store_gdt(struct desc_ptr *dtr) 221 { 222 asm volatile("sgdt %0":"=m" (*dtr)); 223 } 224 225 static inline void store_idt(struct desc_ptr *dtr) 226 { 227 asm volatile("sidt %0":"=m" (*dtr)); 228 } 229 230 /* 231 * The LTR instruction marks the TSS GDT entry as busy. On 64-bit, the GDT is 232 * a read-only remapping. To prevent a page fault, the GDT is switched to the 233 * original writeable version when needed. 234 */ 235 #ifdef CONFIG_X86_64 236 static inline void native_load_tr_desc(void) 237 { 238 struct desc_ptr gdt; 239 int cpu = raw_smp_processor_id(); 240 bool restore = 0; 241 struct desc_struct *fixmap_gdt; 242 243 native_store_gdt(&gdt); 244 fixmap_gdt = get_cpu_gdt_ro(cpu); 245 246 /* 247 * If the current GDT is the read-only fixmap, swap to the original 248 * writeable version. Swap back at the end. 249 */ 250 if (gdt.address == (unsigned long)fixmap_gdt) { 251 load_direct_gdt(cpu); 252 restore = 1; 253 } 254 asm volatile("ltr %w0"::"q" (GDT_ENTRY_TSS*8)); 255 if (restore) 256 load_fixmap_gdt(cpu); 257 } 258 #else 259 static inline void native_load_tr_desc(void) 260 { 261 asm volatile("ltr %w0"::"q" (GDT_ENTRY_TSS*8)); 262 } 263 #endif 264 265 static inline unsigned long native_store_tr(void) 266 { 267 unsigned long tr; 268 269 asm volatile("str %0":"=r" (tr)); 270 271 return tr; 272 } 273 274 static inline void native_load_tls(struct thread_struct *t, unsigned int cpu) 275 { 276 struct desc_struct *gdt = get_cpu_gdt_rw(cpu); 277 unsigned int i; 278 279 for (i = 0; i < GDT_ENTRY_TLS_ENTRIES; i++) 280 gdt[GDT_ENTRY_TLS_MIN + i] = t->tls_array[i]; 281 } 282 283 DECLARE_PER_CPU(bool, __tss_limit_invalid); 284 285 static inline void force_reload_TR(void) 286 { 287 struct desc_struct *d = get_current_gdt_rw(); 288 tss_desc tss; 289 290 memcpy(&tss, &d[GDT_ENTRY_TSS], sizeof(tss_desc)); 291 292 /* 293 * LTR requires an available TSS, and the TSS is currently 294 * busy. Make it be available so that LTR will work. 295 */ 296 tss.type = DESC_TSS; 297 write_gdt_entry(d, GDT_ENTRY_TSS, &tss, DESC_TSS); 298 299 load_TR_desc(); 300 this_cpu_write(__tss_limit_invalid, false); 301 } 302 303 /* 304 * Call this if you need the TSS limit to be correct, which should be the case 305 * if and only if you have TIF_IO_BITMAP set or you're switching to a task 306 * with TIF_IO_BITMAP set. 307 */ 308 static inline void refresh_tss_limit(void) 309 { 310 DEBUG_LOCKS_WARN_ON(preemptible()); 311 312 if (unlikely(this_cpu_read(__tss_limit_invalid))) 313 force_reload_TR(); 314 } 315 316 /* 317 * If you do something evil that corrupts the cached TSS limit (I'm looking 318 * at you, VMX exits), call this function. 319 * 320 * The optimization here is that the TSS limit only matters for Linux if the 321 * IO bitmap is in use. If the TSS limit gets forced to its minimum value, 322 * everything works except that IO bitmap will be ignored and all CPL 3 IO 323 * instructions will #GP, which is exactly what we want for normal tasks. 324 */ 325 static inline void invalidate_tss_limit(void) 326 { 327 DEBUG_LOCKS_WARN_ON(preemptible()); 328 329 if (unlikely(test_thread_flag(TIF_IO_BITMAP))) 330 force_reload_TR(); 331 else 332 this_cpu_write(__tss_limit_invalid, true); 333 } 334 335 /* This intentionally ignores lm, since 32-bit apps don't have that field. */ 336 #define LDT_empty(info) \ 337 ((info)->base_addr == 0 && \ 338 (info)->limit == 0 && \ 339 (info)->contents == 0 && \ 340 (info)->read_exec_only == 1 && \ 341 (info)->seg_32bit == 0 && \ 342 (info)->limit_in_pages == 0 && \ 343 (info)->seg_not_present == 1 && \ 344 (info)->useable == 0) 345 346 /* Lots of programs expect an all-zero user_desc to mean "no segment at all". */ 347 static inline bool LDT_zero(const struct user_desc *info) 348 { 349 return (info->base_addr == 0 && 350 info->limit == 0 && 351 info->contents == 0 && 352 info->read_exec_only == 0 && 353 info->seg_32bit == 0 && 354 info->limit_in_pages == 0 && 355 info->seg_not_present == 0 && 356 info->useable == 0); 357 } 358 359 static inline void clear_LDT(void) 360 { 361 set_ldt(NULL, 0); 362 } 363 364 static inline unsigned long get_desc_base(const struct desc_struct *desc) 365 { 366 return (unsigned)(desc->base0 | ((desc->base1) << 16) | ((desc->base2) << 24)); 367 } 368 369 static inline void set_desc_base(struct desc_struct *desc, unsigned long base) 370 { 371 desc->base0 = base & 0xffff; 372 desc->base1 = (base >> 16) & 0xff; 373 desc->base2 = (base >> 24) & 0xff; 374 } 375 376 static inline unsigned long get_desc_limit(const struct desc_struct *desc) 377 { 378 return desc->limit0 | (desc->limit1 << 16); 379 } 380 381 static inline void set_desc_limit(struct desc_struct *desc, unsigned long limit) 382 { 383 desc->limit0 = limit & 0xffff; 384 desc->limit1 = (limit >> 16) & 0xf; 385 } 386 387 void update_intr_gate(unsigned int n, const void *addr); 388 void alloc_intr_gate(unsigned int n, const void *addr); 389 390 extern unsigned long system_vectors[]; 391 392 #ifdef CONFIG_X86_64 393 DECLARE_PER_CPU(u32, debug_idt_ctr); 394 static inline bool is_debug_idt_enabled(void) 395 { 396 if (this_cpu_read(debug_idt_ctr)) 397 return true; 398 399 return false; 400 } 401 402 static inline void load_debug_idt(void) 403 { 404 load_idt((const struct desc_ptr *)&debug_idt_descr); 405 } 406 #else 407 static inline bool is_debug_idt_enabled(void) 408 { 409 return false; 410 } 411 412 static inline void load_debug_idt(void) 413 { 414 } 415 #endif 416 417 /* 418 * The load_current_idt() must be called with interrupts disabled 419 * to avoid races. That way the IDT will always be set back to the expected 420 * descriptor. It's also called when a CPU is being initialized, and 421 * that doesn't need to disable interrupts, as nothing should be 422 * bothering the CPU then. 423 */ 424 static inline void load_current_idt(void) 425 { 426 if (is_debug_idt_enabled()) 427 load_debug_idt(); 428 else 429 load_idt((const struct desc_ptr *)&idt_descr); 430 } 431 432 extern void idt_setup_early_handler(void); 433 extern void idt_setup_early_traps(void); 434 extern void idt_setup_traps(void); 435 extern void idt_setup_apic_and_irq_gates(void); 436 437 #ifdef CONFIG_X86_64 438 extern void idt_setup_early_pf(void); 439 extern void idt_setup_ist_traps(void); 440 extern void idt_setup_debugidt_traps(void); 441 #else 442 static inline void idt_setup_early_pf(void) { } 443 static inline void idt_setup_ist_traps(void) { } 444 static inline void idt_setup_debugidt_traps(void) { } 445 #endif 446 447 extern void idt_invalidate(void *addr); 448 449 #endif /* _ASM_X86_DESC_H */ 450