1 #ifndef _ASM_X86_DESC_H 2 #define _ASM_X86_DESC_H 3 4 #ifndef __ASSEMBLY__ 5 #include <asm/desc_defs.h> 6 #include <asm/ldt.h> 7 #include <asm/mmu.h> 8 #include <linux/smp.h> 9 10 static inline void fill_ldt(struct desc_struct *desc, 11 const struct user_desc *info) 12 { 13 desc->limit0 = info->limit & 0x0ffff; 14 desc->base0 = info->base_addr & 0x0000ffff; 15 16 desc->base1 = (info->base_addr & 0x00ff0000) >> 16; 17 desc->type = (info->read_exec_only ^ 1) << 1; 18 desc->type |= info->contents << 2; 19 desc->s = 1; 20 desc->dpl = 0x3; 21 desc->p = info->seg_not_present ^ 1; 22 desc->limit = (info->limit & 0xf0000) >> 16; 23 desc->avl = info->useable; 24 desc->d = info->seg_32bit; 25 desc->g = info->limit_in_pages; 26 desc->base2 = (info->base_addr & 0xff000000) >> 24; 27 /* 28 * Don't allow setting of the lm bit. It is useless anyway 29 * because 64bit system calls require __USER_CS: 30 */ 31 desc->l = 0; 32 } 33 34 extern struct desc_ptr idt_descr; 35 extern gate_desc idt_table[]; 36 37 struct gdt_page { 38 struct desc_struct gdt[GDT_ENTRIES]; 39 } __attribute__((aligned(PAGE_SIZE))); 40 DECLARE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page); 41 42 static inline struct desc_struct *get_cpu_gdt_table(unsigned int cpu) 43 { 44 return per_cpu(gdt_page, cpu).gdt; 45 } 46 47 #ifdef CONFIG_X86_64 48 49 static inline void pack_gate(gate_desc *gate, unsigned type, unsigned long func, 50 unsigned dpl, unsigned ist, unsigned seg) 51 { 52 gate->offset_low = PTR_LOW(func); 53 gate->segment = __KERNEL_CS; 54 gate->ist = ist; 55 gate->p = 1; 56 gate->dpl = dpl; 57 gate->zero0 = 0; 58 gate->zero1 = 0; 59 gate->type = type; 60 gate->offset_middle = PTR_MIDDLE(func); 61 gate->offset_high = PTR_HIGH(func); 62 } 63 64 #else 65 static inline void pack_gate(gate_desc *gate, unsigned char type, 66 unsigned long base, unsigned dpl, unsigned flags, 67 unsigned short seg) 68 { 69 gate->a = (seg << 16) | (base & 0xffff); 70 gate->b = (base & 0xffff0000) | 71 (((0x80 | type | (dpl << 5)) & 0xff) << 8); 72 } 73 74 #endif 75 76 static inline int desc_empty(const void *ptr) 77 { 78 const u32 *desc = ptr; 79 return !(desc[0] | desc[1]); 80 } 81 82 #ifdef CONFIG_PARAVIRT 83 #include <asm/paravirt.h> 84 #else 85 #define load_TR_desc() native_load_tr_desc() 86 #define load_gdt(dtr) native_load_gdt(dtr) 87 #define load_idt(dtr) native_load_idt(dtr) 88 #define load_tr(tr) asm volatile("ltr %0"::"m" (tr)) 89 #define load_ldt(ldt) asm volatile("lldt %0"::"m" (ldt)) 90 91 #define store_gdt(dtr) native_store_gdt(dtr) 92 #define store_idt(dtr) native_store_idt(dtr) 93 #define store_tr(tr) (tr = native_store_tr()) 94 95 #define load_TLS(t, cpu) native_load_tls(t, cpu) 96 #define set_ldt native_set_ldt 97 98 #define write_ldt_entry(dt, entry, desc) \ 99 native_write_ldt_entry(dt, entry, desc) 100 #define write_gdt_entry(dt, entry, desc, type) \ 101 native_write_gdt_entry(dt, entry, desc, type) 102 #define write_idt_entry(dt, entry, g) \ 103 native_write_idt_entry(dt, entry, g) 104 105 static inline void paravirt_alloc_ldt(struct desc_struct *ldt, unsigned entries) 106 { 107 } 108 109 static inline void paravirt_free_ldt(struct desc_struct *ldt, unsigned entries) 110 { 111 } 112 #endif /* CONFIG_PARAVIRT */ 113 114 #define store_ldt(ldt) asm("sldt %0" : "=m"(ldt)) 115 116 static inline void native_write_idt_entry(gate_desc *idt, int entry, 117 const gate_desc *gate) 118 { 119 memcpy(&idt[entry], gate, sizeof(*gate)); 120 } 121 122 static inline void native_write_ldt_entry(struct desc_struct *ldt, int entry, 123 const void *desc) 124 { 125 memcpy(&ldt[entry], desc, 8); 126 } 127 128 static inline void native_write_gdt_entry(struct desc_struct *gdt, int entry, 129 const void *desc, int type) 130 { 131 unsigned int size; 132 switch (type) { 133 case DESC_TSS: 134 size = sizeof(tss_desc); 135 break; 136 case DESC_LDT: 137 size = sizeof(ldt_desc); 138 break; 139 default: 140 size = sizeof(struct desc_struct); 141 break; 142 } 143 memcpy(&gdt[entry], desc, size); 144 } 145 146 static inline void pack_descriptor(struct desc_struct *desc, unsigned long base, 147 unsigned long limit, unsigned char type, 148 unsigned char flags) 149 { 150 desc->a = ((base & 0xffff) << 16) | (limit & 0xffff); 151 desc->b = (base & 0xff000000) | ((base & 0xff0000) >> 16) | 152 (limit & 0x000f0000) | ((type & 0xff) << 8) | 153 ((flags & 0xf) << 20); 154 desc->p = 1; 155 } 156 157 158 static inline void set_tssldt_descriptor(void *d, unsigned long addr, 159 unsigned type, unsigned size) 160 { 161 #ifdef CONFIG_X86_64 162 struct ldttss_desc64 *desc = d; 163 memset(desc, 0, sizeof(*desc)); 164 desc->limit0 = size & 0xFFFF; 165 desc->base0 = PTR_LOW(addr); 166 desc->base1 = PTR_MIDDLE(addr) & 0xFF; 167 desc->type = type; 168 desc->p = 1; 169 desc->limit1 = (size >> 16) & 0xF; 170 desc->base2 = (PTR_MIDDLE(addr) >> 8) & 0xFF; 171 desc->base3 = PTR_HIGH(addr); 172 #else 173 pack_descriptor((struct desc_struct *)d, addr, size, 0x80 | type, 0); 174 #endif 175 } 176 177 static inline void __set_tss_desc(unsigned cpu, unsigned int entry, void *addr) 178 { 179 struct desc_struct *d = get_cpu_gdt_table(cpu); 180 tss_desc tss; 181 182 /* 183 * sizeof(unsigned long) coming from an extra "long" at the end 184 * of the iobitmap. See tss_struct definition in processor.h 185 * 186 * -1? seg base+limit should be pointing to the address of the 187 * last valid byte 188 */ 189 set_tssldt_descriptor(&tss, (unsigned long)addr, DESC_TSS, 190 IO_BITMAP_OFFSET + IO_BITMAP_BYTES + 191 sizeof(unsigned long) - 1); 192 write_gdt_entry(d, entry, &tss, DESC_TSS); 193 } 194 195 #define set_tss_desc(cpu, addr) __set_tss_desc(cpu, GDT_ENTRY_TSS, addr) 196 197 static inline void native_set_ldt(const void *addr, unsigned int entries) 198 { 199 if (likely(entries == 0)) 200 asm volatile("lldt %w0"::"q" (0)); 201 else { 202 unsigned cpu = smp_processor_id(); 203 ldt_desc ldt; 204 205 set_tssldt_descriptor(&ldt, (unsigned long)addr, DESC_LDT, 206 entries * LDT_ENTRY_SIZE - 1); 207 write_gdt_entry(get_cpu_gdt_table(cpu), GDT_ENTRY_LDT, 208 &ldt, DESC_LDT); 209 asm volatile("lldt %w0"::"q" (GDT_ENTRY_LDT*8)); 210 } 211 } 212 213 static inline void native_load_tr_desc(void) 214 { 215 asm volatile("ltr %w0"::"q" (GDT_ENTRY_TSS*8)); 216 } 217 218 static inline void native_load_gdt(const struct desc_ptr *dtr) 219 { 220 asm volatile("lgdt %0"::"m" (*dtr)); 221 } 222 223 static inline void native_load_idt(const struct desc_ptr *dtr) 224 { 225 asm volatile("lidt %0"::"m" (*dtr)); 226 } 227 228 static inline void native_store_gdt(struct desc_ptr *dtr) 229 { 230 asm volatile("sgdt %0":"=m" (*dtr)); 231 } 232 233 static inline void native_store_idt(struct desc_ptr *dtr) 234 { 235 asm volatile("sidt %0":"=m" (*dtr)); 236 } 237 238 static inline unsigned long native_store_tr(void) 239 { 240 unsigned long tr; 241 asm volatile("str %0":"=r" (tr)); 242 return tr; 243 } 244 245 static inline void native_load_tls(struct thread_struct *t, unsigned int cpu) 246 { 247 unsigned int i; 248 struct desc_struct *gdt = get_cpu_gdt_table(cpu); 249 250 for (i = 0; i < GDT_ENTRY_TLS_ENTRIES; i++) 251 gdt[GDT_ENTRY_TLS_MIN + i] = t->tls_array[i]; 252 } 253 254 #define _LDT_empty(info) \ 255 ((info)->base_addr == 0 && \ 256 (info)->limit == 0 && \ 257 (info)->contents == 0 && \ 258 (info)->read_exec_only == 1 && \ 259 (info)->seg_32bit == 0 && \ 260 (info)->limit_in_pages == 0 && \ 261 (info)->seg_not_present == 1 && \ 262 (info)->useable == 0) 263 264 #ifdef CONFIG_X86_64 265 #define LDT_empty(info) (_LDT_empty(info) && ((info)->lm == 0)) 266 #else 267 #define LDT_empty(info) (_LDT_empty(info)) 268 #endif 269 270 static inline void clear_LDT(void) 271 { 272 set_ldt(NULL, 0); 273 } 274 275 /* 276 * load one particular LDT into the current CPU 277 */ 278 static inline void load_LDT_nolock(mm_context_t *pc) 279 { 280 set_ldt(pc->ldt, pc->size); 281 } 282 283 static inline void load_LDT(mm_context_t *pc) 284 { 285 preempt_disable(); 286 load_LDT_nolock(pc); 287 preempt_enable(); 288 } 289 290 static inline unsigned long get_desc_base(const struct desc_struct *desc) 291 { 292 return desc->base0 | ((desc->base1) << 16) | ((desc->base2) << 24); 293 } 294 295 static inline unsigned long get_desc_limit(const struct desc_struct *desc) 296 { 297 return desc->limit0 | (desc->limit << 16); 298 } 299 300 static inline void _set_gate(int gate, unsigned type, void *addr, 301 unsigned dpl, unsigned ist, unsigned seg) 302 { 303 gate_desc s; 304 pack_gate(&s, type, (unsigned long)addr, dpl, ist, seg); 305 /* 306 * does not need to be atomic because it is only done once at 307 * setup time 308 */ 309 write_idt_entry(idt_table, gate, &s); 310 } 311 312 /* 313 * This needs to use 'idt_table' rather than 'idt', and 314 * thus use the _nonmapped_ version of the IDT, as the 315 * Pentium F0 0F bugfix can have resulted in the mapped 316 * IDT being write-protected. 317 */ 318 static inline void set_intr_gate(unsigned int n, void *addr) 319 { 320 BUG_ON((unsigned)n > 0xFF); 321 _set_gate(n, GATE_INTERRUPT, addr, 0, 0, __KERNEL_CS); 322 } 323 324 extern int first_system_vector; 325 /* used_vectors is BITMAP for irq is not managed by percpu vector_irq */ 326 extern unsigned long used_vectors[]; 327 328 static inline void alloc_system_vector(int vector) 329 { 330 if (!test_bit(vector, used_vectors)) { 331 set_bit(vector, used_vectors); 332 if (first_system_vector > vector) 333 first_system_vector = vector; 334 } else 335 BUG(); 336 } 337 338 static inline void alloc_intr_gate(unsigned int n, void *addr) 339 { 340 alloc_system_vector(n); 341 set_intr_gate(n, addr); 342 } 343 344 /* 345 * This routine sets up an interrupt gate at directory privilege level 3. 346 */ 347 static inline void set_system_intr_gate(unsigned int n, void *addr) 348 { 349 BUG_ON((unsigned)n > 0xFF); 350 _set_gate(n, GATE_INTERRUPT, addr, 0x3, 0, __KERNEL_CS); 351 } 352 353 static inline void set_system_trap_gate(unsigned int n, void *addr) 354 { 355 BUG_ON((unsigned)n > 0xFF); 356 _set_gate(n, GATE_TRAP, addr, 0x3, 0, __KERNEL_CS); 357 } 358 359 static inline void set_trap_gate(unsigned int n, void *addr) 360 { 361 BUG_ON((unsigned)n > 0xFF); 362 _set_gate(n, GATE_TRAP, addr, 0, 0, __KERNEL_CS); 363 } 364 365 static inline void set_task_gate(unsigned int n, unsigned int gdt_entry) 366 { 367 BUG_ON((unsigned)n > 0xFF); 368 _set_gate(n, GATE_TASK, (void *)0, 0, 0, (gdt_entry<<3)); 369 } 370 371 static inline void set_intr_gate_ist(int n, void *addr, unsigned ist) 372 { 373 BUG_ON((unsigned)n > 0xFF); 374 _set_gate(n, GATE_INTERRUPT, addr, 0, ist, __KERNEL_CS); 375 } 376 377 static inline void set_system_intr_gate_ist(int n, void *addr, unsigned ist) 378 { 379 BUG_ON((unsigned)n > 0xFF); 380 _set_gate(n, GATE_INTERRUPT, addr, 0x3, ist, __KERNEL_CS); 381 } 382 383 #else 384 /* 385 * GET_DESC_BASE reads the descriptor base of the specified segment. 386 * 387 * Args: 388 * idx - descriptor index 389 * gdt - GDT pointer 390 * base - 32bit register to which the base will be written 391 * lo_w - lo word of the "base" register 392 * lo_b - lo byte of the "base" register 393 * hi_b - hi byte of the low word of the "base" register 394 * 395 * Example: 396 * GET_DESC_BASE(GDT_ENTRY_ESPFIX_SS, %ebx, %eax, %ax, %al, %ah) 397 * Will read the base address of GDT_ENTRY_ESPFIX_SS and put it into %eax. 398 */ 399 #define GET_DESC_BASE(idx, gdt, base, lo_w, lo_b, hi_b) \ 400 movb idx * 8 + 4(gdt), lo_b; \ 401 movb idx * 8 + 7(gdt), hi_b; \ 402 shll $16, base; \ 403 movw idx * 8 + 2(gdt), lo_w; 404 405 406 #endif /* __ASSEMBLY__ */ 407 408 #endif /* _ASM_X86_DESC_H */ 409