1 #ifndef _ASM_X86_DESC_H 2 #define _ASM_X86_DESC_H 3 4 #include <asm/desc_defs.h> 5 #include <asm/ldt.h> 6 #include <asm/mmu.h> 7 #include <linux/smp.h> 8 9 static inline void fill_ldt(struct desc_struct *desc, 10 const struct user_desc *info) 11 { 12 desc->limit0 = info->limit & 0x0ffff; 13 desc->base0 = info->base_addr & 0x0000ffff; 14 15 desc->base1 = (info->base_addr & 0x00ff0000) >> 16; 16 desc->type = (info->read_exec_only ^ 1) << 1; 17 desc->type |= info->contents << 2; 18 desc->s = 1; 19 desc->dpl = 0x3; 20 desc->p = info->seg_not_present ^ 1; 21 desc->limit = (info->limit & 0xf0000) >> 16; 22 desc->avl = info->useable; 23 desc->d = info->seg_32bit; 24 desc->g = info->limit_in_pages; 25 desc->base2 = (info->base_addr & 0xff000000) >> 24; 26 /* 27 * Don't allow setting of the lm bit. It is useless anyway 28 * because 64bit system calls require __USER_CS: 29 */ 30 desc->l = 0; 31 } 32 33 extern struct desc_ptr idt_descr; 34 extern gate_desc idt_table[]; 35 36 struct gdt_page { 37 struct desc_struct gdt[GDT_ENTRIES]; 38 } __attribute__((aligned(PAGE_SIZE))); 39 DECLARE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page); 40 41 static inline struct desc_struct *get_cpu_gdt_table(unsigned int cpu) 42 { 43 return per_cpu(gdt_page, cpu).gdt; 44 } 45 46 #ifdef CONFIG_X86_64 47 48 static inline void pack_gate(gate_desc *gate, unsigned type, unsigned long func, 49 unsigned dpl, unsigned ist, unsigned seg) 50 { 51 gate->offset_low = PTR_LOW(func); 52 gate->segment = __KERNEL_CS; 53 gate->ist = ist; 54 gate->p = 1; 55 gate->dpl = dpl; 56 gate->zero0 = 0; 57 gate->zero1 = 0; 58 gate->type = type; 59 gate->offset_middle = PTR_MIDDLE(func); 60 gate->offset_high = PTR_HIGH(func); 61 } 62 63 #else 64 static inline void pack_gate(gate_desc *gate, unsigned char type, 65 unsigned long base, unsigned dpl, unsigned flags, 66 unsigned short seg) 67 { 68 gate->a = (seg << 16) | (base & 0xffff); 69 gate->b = (base & 0xffff0000) | 70 (((0x80 | type | (dpl << 5)) & 0xff) << 8); 71 } 72 73 #endif 74 75 static inline int desc_empty(const void *ptr) 76 { 77 const u32 *desc = ptr; 78 return !(desc[0] | desc[1]); 79 } 80 81 #ifdef CONFIG_PARAVIRT 82 #include <asm/paravirt.h> 83 #else 84 #define load_TR_desc() native_load_tr_desc() 85 #define load_gdt(dtr) native_load_gdt(dtr) 86 #define load_idt(dtr) native_load_idt(dtr) 87 #define load_tr(tr) asm volatile("ltr %0"::"m" (tr)) 88 #define load_ldt(ldt) asm volatile("lldt %0"::"m" (ldt)) 89 90 #define store_gdt(dtr) native_store_gdt(dtr) 91 #define store_idt(dtr) native_store_idt(dtr) 92 #define store_tr(tr) (tr = native_store_tr()) 93 94 #define load_TLS(t, cpu) native_load_tls(t, cpu) 95 #define set_ldt native_set_ldt 96 97 #define write_ldt_entry(dt, entry, desc) \ 98 native_write_ldt_entry(dt, entry, desc) 99 #define write_gdt_entry(dt, entry, desc, type) \ 100 native_write_gdt_entry(dt, entry, desc, type) 101 #define write_idt_entry(dt, entry, g) \ 102 native_write_idt_entry(dt, entry, g) 103 104 static inline void paravirt_alloc_ldt(struct desc_struct *ldt, unsigned entries) 105 { 106 } 107 108 static inline void paravirt_free_ldt(struct desc_struct *ldt, unsigned entries) 109 { 110 } 111 #endif /* CONFIG_PARAVIRT */ 112 113 #define store_ldt(ldt) asm("sldt %0" : "=m"(ldt)) 114 115 static inline void native_write_idt_entry(gate_desc *idt, int entry, 116 const gate_desc *gate) 117 { 118 memcpy(&idt[entry], gate, sizeof(*gate)); 119 } 120 121 static inline void native_write_ldt_entry(struct desc_struct *ldt, int entry, 122 const void *desc) 123 { 124 memcpy(&ldt[entry], desc, 8); 125 } 126 127 static inline void native_write_gdt_entry(struct desc_struct *gdt, int entry, 128 const void *desc, int type) 129 { 130 unsigned int size; 131 switch (type) { 132 case DESC_TSS: 133 size = sizeof(tss_desc); 134 break; 135 case DESC_LDT: 136 size = sizeof(ldt_desc); 137 break; 138 default: 139 size = sizeof(struct desc_struct); 140 break; 141 } 142 memcpy(&gdt[entry], desc, size); 143 } 144 145 static inline void pack_descriptor(struct desc_struct *desc, unsigned long base, 146 unsigned long limit, unsigned char type, 147 unsigned char flags) 148 { 149 desc->a = ((base & 0xffff) << 16) | (limit & 0xffff); 150 desc->b = (base & 0xff000000) | ((base & 0xff0000) >> 16) | 151 (limit & 0x000f0000) | ((type & 0xff) << 8) | 152 ((flags & 0xf) << 20); 153 desc->p = 1; 154 } 155 156 157 static inline void set_tssldt_descriptor(void *d, unsigned long addr, 158 unsigned type, unsigned size) 159 { 160 #ifdef CONFIG_X86_64 161 struct ldttss_desc64 *desc = d; 162 memset(desc, 0, sizeof(*desc)); 163 desc->limit0 = size & 0xFFFF; 164 desc->base0 = PTR_LOW(addr); 165 desc->base1 = PTR_MIDDLE(addr) & 0xFF; 166 desc->type = type; 167 desc->p = 1; 168 desc->limit1 = (size >> 16) & 0xF; 169 desc->base2 = (PTR_MIDDLE(addr) >> 8) & 0xFF; 170 desc->base3 = PTR_HIGH(addr); 171 #else 172 pack_descriptor((struct desc_struct *)d, addr, size, 0x80 | type, 0); 173 #endif 174 } 175 176 static inline void __set_tss_desc(unsigned cpu, unsigned int entry, void *addr) 177 { 178 struct desc_struct *d = get_cpu_gdt_table(cpu); 179 tss_desc tss; 180 181 /* 182 * sizeof(unsigned long) coming from an extra "long" at the end 183 * of the iobitmap. See tss_struct definition in processor.h 184 * 185 * -1? seg base+limit should be pointing to the address of the 186 * last valid byte 187 */ 188 set_tssldt_descriptor(&tss, (unsigned long)addr, DESC_TSS, 189 IO_BITMAP_OFFSET + IO_BITMAP_BYTES + 190 sizeof(unsigned long) - 1); 191 write_gdt_entry(d, entry, &tss, DESC_TSS); 192 } 193 194 #define set_tss_desc(cpu, addr) __set_tss_desc(cpu, GDT_ENTRY_TSS, addr) 195 196 static inline void native_set_ldt(const void *addr, unsigned int entries) 197 { 198 if (likely(entries == 0)) 199 asm volatile("lldt %w0"::"q" (0)); 200 else { 201 unsigned cpu = smp_processor_id(); 202 ldt_desc ldt; 203 204 set_tssldt_descriptor(&ldt, (unsigned long)addr, DESC_LDT, 205 entries * LDT_ENTRY_SIZE - 1); 206 write_gdt_entry(get_cpu_gdt_table(cpu), GDT_ENTRY_LDT, 207 &ldt, DESC_LDT); 208 asm volatile("lldt %w0"::"q" (GDT_ENTRY_LDT*8)); 209 } 210 } 211 212 static inline void native_load_tr_desc(void) 213 { 214 asm volatile("ltr %w0"::"q" (GDT_ENTRY_TSS*8)); 215 } 216 217 static inline void native_load_gdt(const struct desc_ptr *dtr) 218 { 219 asm volatile("lgdt %0"::"m" (*dtr)); 220 } 221 222 static inline void native_load_idt(const struct desc_ptr *dtr) 223 { 224 asm volatile("lidt %0"::"m" (*dtr)); 225 } 226 227 static inline void native_store_gdt(struct desc_ptr *dtr) 228 { 229 asm volatile("sgdt %0":"=m" (*dtr)); 230 } 231 232 static inline void native_store_idt(struct desc_ptr *dtr) 233 { 234 asm volatile("sidt %0":"=m" (*dtr)); 235 } 236 237 static inline unsigned long native_store_tr(void) 238 { 239 unsigned long tr; 240 asm volatile("str %0":"=r" (tr)); 241 return tr; 242 } 243 244 static inline void native_load_tls(struct thread_struct *t, unsigned int cpu) 245 { 246 unsigned int i; 247 struct desc_struct *gdt = get_cpu_gdt_table(cpu); 248 249 for (i = 0; i < GDT_ENTRY_TLS_ENTRIES; i++) 250 gdt[GDT_ENTRY_TLS_MIN + i] = t->tls_array[i]; 251 } 252 253 #define _LDT_empty(info) \ 254 ((info)->base_addr == 0 && \ 255 (info)->limit == 0 && \ 256 (info)->contents == 0 && \ 257 (info)->read_exec_only == 1 && \ 258 (info)->seg_32bit == 0 && \ 259 (info)->limit_in_pages == 0 && \ 260 (info)->seg_not_present == 1 && \ 261 (info)->useable == 0) 262 263 #ifdef CONFIG_X86_64 264 #define LDT_empty(info) (_LDT_empty(info) && ((info)->lm == 0)) 265 #else 266 #define LDT_empty(info) (_LDT_empty(info)) 267 #endif 268 269 static inline void clear_LDT(void) 270 { 271 set_ldt(NULL, 0); 272 } 273 274 /* 275 * load one particular LDT into the current CPU 276 */ 277 static inline void load_LDT_nolock(mm_context_t *pc) 278 { 279 set_ldt(pc->ldt, pc->size); 280 } 281 282 static inline void load_LDT(mm_context_t *pc) 283 { 284 preempt_disable(); 285 load_LDT_nolock(pc); 286 preempt_enable(); 287 } 288 289 static inline unsigned long get_desc_base(const struct desc_struct *desc) 290 { 291 return (unsigned)(desc->base0 | ((desc->base1) << 16) | ((desc->base2) << 24)); 292 } 293 294 static inline void set_desc_base(struct desc_struct *desc, unsigned long base) 295 { 296 desc->base0 = base & 0xffff; 297 desc->base1 = (base >> 16) & 0xff; 298 desc->base2 = (base >> 24) & 0xff; 299 } 300 301 static inline unsigned long get_desc_limit(const struct desc_struct *desc) 302 { 303 return desc->limit0 | (desc->limit << 16); 304 } 305 306 static inline void set_desc_limit(struct desc_struct *desc, unsigned long limit) 307 { 308 desc->limit0 = limit & 0xffff; 309 desc->limit = (limit >> 16) & 0xf; 310 } 311 312 static inline void _set_gate(int gate, unsigned type, void *addr, 313 unsigned dpl, unsigned ist, unsigned seg) 314 { 315 gate_desc s; 316 pack_gate(&s, type, (unsigned long)addr, dpl, ist, seg); 317 /* 318 * does not need to be atomic because it is only done once at 319 * setup time 320 */ 321 write_idt_entry(idt_table, gate, &s); 322 } 323 324 /* 325 * This needs to use 'idt_table' rather than 'idt', and 326 * thus use the _nonmapped_ version of the IDT, as the 327 * Pentium F0 0F bugfix can have resulted in the mapped 328 * IDT being write-protected. 329 */ 330 static inline void set_intr_gate(unsigned int n, void *addr) 331 { 332 BUG_ON((unsigned)n > 0xFF); 333 _set_gate(n, GATE_INTERRUPT, addr, 0, 0, __KERNEL_CS); 334 } 335 336 extern int first_system_vector; 337 /* used_vectors is BITMAP for irq is not managed by percpu vector_irq */ 338 extern unsigned long used_vectors[]; 339 340 static inline void alloc_system_vector(int vector) 341 { 342 if (!test_bit(vector, used_vectors)) { 343 set_bit(vector, used_vectors); 344 if (first_system_vector > vector) 345 first_system_vector = vector; 346 } else 347 BUG(); 348 } 349 350 static inline void alloc_intr_gate(unsigned int n, void *addr) 351 { 352 alloc_system_vector(n); 353 set_intr_gate(n, addr); 354 } 355 356 /* 357 * This routine sets up an interrupt gate at directory privilege level 3. 358 */ 359 static inline void set_system_intr_gate(unsigned int n, void *addr) 360 { 361 BUG_ON((unsigned)n > 0xFF); 362 _set_gate(n, GATE_INTERRUPT, addr, 0x3, 0, __KERNEL_CS); 363 } 364 365 static inline void set_system_trap_gate(unsigned int n, void *addr) 366 { 367 BUG_ON((unsigned)n > 0xFF); 368 _set_gate(n, GATE_TRAP, addr, 0x3, 0, __KERNEL_CS); 369 } 370 371 static inline void set_trap_gate(unsigned int n, void *addr) 372 { 373 BUG_ON((unsigned)n > 0xFF); 374 _set_gate(n, GATE_TRAP, addr, 0, 0, __KERNEL_CS); 375 } 376 377 static inline void set_task_gate(unsigned int n, unsigned int gdt_entry) 378 { 379 BUG_ON((unsigned)n > 0xFF); 380 _set_gate(n, GATE_TASK, (void *)0, 0, 0, (gdt_entry<<3)); 381 } 382 383 static inline void set_intr_gate_ist(int n, void *addr, unsigned ist) 384 { 385 BUG_ON((unsigned)n > 0xFF); 386 _set_gate(n, GATE_INTERRUPT, addr, 0, ist, __KERNEL_CS); 387 } 388 389 static inline void set_system_intr_gate_ist(int n, void *addr, unsigned ist) 390 { 391 BUG_ON((unsigned)n > 0xFF); 392 _set_gate(n, GATE_INTERRUPT, addr, 0x3, ist, __KERNEL_CS); 393 } 394 395 #endif /* _ASM_X86_DESC_H */ 396