1 /* 2 * Defines x86 CPU feature bits 3 */ 4 #ifndef _ASM_X86_CPUFEATURE_H 5 #define _ASM_X86_CPUFEATURE_H 6 7 #ifndef _ASM_X86_REQUIRED_FEATURES_H 8 #include <asm/required-features.h> 9 #endif 10 11 #define NCAPINTS 10 /* N 32-bit words worth of info */ 12 #define NBUGINTS 1 /* N 32-bit bug flags */ 13 14 /* 15 * Note: If the comment begins with a quoted string, that string is used 16 * in /proc/cpuinfo instead of the macro name. If the string is "", 17 * this feature bit is not displayed in /proc/cpuinfo at all. 18 */ 19 20 /* Intel-defined CPU features, CPUID level 0x00000001 (edx), word 0 */ 21 #define X86_FEATURE_FPU (0*32+ 0) /* Onboard FPU */ 22 #define X86_FEATURE_VME (0*32+ 1) /* Virtual Mode Extensions */ 23 #define X86_FEATURE_DE (0*32+ 2) /* Debugging Extensions */ 24 #define X86_FEATURE_PSE (0*32+ 3) /* Page Size Extensions */ 25 #define X86_FEATURE_TSC (0*32+ 4) /* Time Stamp Counter */ 26 #define X86_FEATURE_MSR (0*32+ 5) /* Model-Specific Registers */ 27 #define X86_FEATURE_PAE (0*32+ 6) /* Physical Address Extensions */ 28 #define X86_FEATURE_MCE (0*32+ 7) /* Machine Check Exception */ 29 #define X86_FEATURE_CX8 (0*32+ 8) /* CMPXCHG8 instruction */ 30 #define X86_FEATURE_APIC (0*32+ 9) /* Onboard APIC */ 31 #define X86_FEATURE_SEP (0*32+11) /* SYSENTER/SYSEXIT */ 32 #define X86_FEATURE_MTRR (0*32+12) /* Memory Type Range Registers */ 33 #define X86_FEATURE_PGE (0*32+13) /* Page Global Enable */ 34 #define X86_FEATURE_MCA (0*32+14) /* Machine Check Architecture */ 35 #define X86_FEATURE_CMOV (0*32+15) /* CMOV instructions */ 36 /* (plus FCMOVcc, FCOMI with FPU) */ 37 #define X86_FEATURE_PAT (0*32+16) /* Page Attribute Table */ 38 #define X86_FEATURE_PSE36 (0*32+17) /* 36-bit PSEs */ 39 #define X86_FEATURE_PN (0*32+18) /* Processor serial number */ 40 #define X86_FEATURE_CLFLUSH (0*32+19) /* CLFLUSH instruction */ 41 #define X86_FEATURE_DS (0*32+21) /* "dts" Debug Store */ 42 #define X86_FEATURE_ACPI (0*32+22) /* ACPI via MSR */ 43 #define X86_FEATURE_MMX (0*32+23) /* Multimedia Extensions */ 44 #define X86_FEATURE_FXSR (0*32+24) /* FXSAVE/FXRSTOR, CR4.OSFXSR */ 45 #define X86_FEATURE_XMM (0*32+25) /* "sse" */ 46 #define X86_FEATURE_XMM2 (0*32+26) /* "sse2" */ 47 #define X86_FEATURE_SELFSNOOP (0*32+27) /* "ss" CPU self snoop */ 48 #define X86_FEATURE_HT (0*32+28) /* Hyper-Threading */ 49 #define X86_FEATURE_ACC (0*32+29) /* "tm" Automatic clock control */ 50 #define X86_FEATURE_IA64 (0*32+30) /* IA-64 processor */ 51 #define X86_FEATURE_PBE (0*32+31) /* Pending Break Enable */ 52 53 /* AMD-defined CPU features, CPUID level 0x80000001, word 1 */ 54 /* Don't duplicate feature flags which are redundant with Intel! */ 55 #define X86_FEATURE_SYSCALL (1*32+11) /* SYSCALL/SYSRET */ 56 #define X86_FEATURE_MP (1*32+19) /* MP Capable. */ 57 #define X86_FEATURE_NX (1*32+20) /* Execute Disable */ 58 #define X86_FEATURE_MMXEXT (1*32+22) /* AMD MMX extensions */ 59 #define X86_FEATURE_FXSR_OPT (1*32+25) /* FXSAVE/FXRSTOR optimizations */ 60 #define X86_FEATURE_GBPAGES (1*32+26) /* "pdpe1gb" GB pages */ 61 #define X86_FEATURE_RDTSCP (1*32+27) /* RDTSCP */ 62 #define X86_FEATURE_LM (1*32+29) /* Long Mode (x86-64) */ 63 #define X86_FEATURE_3DNOWEXT (1*32+30) /* AMD 3DNow! extensions */ 64 #define X86_FEATURE_3DNOW (1*32+31) /* 3DNow! */ 65 66 /* Transmeta-defined CPU features, CPUID level 0x80860001, word 2 */ 67 #define X86_FEATURE_RECOVERY (2*32+ 0) /* CPU in recovery mode */ 68 #define X86_FEATURE_LONGRUN (2*32+ 1) /* Longrun power control */ 69 #define X86_FEATURE_LRTI (2*32+ 3) /* LongRun table interface */ 70 71 /* Other features, Linux-defined mapping, word 3 */ 72 /* This range is used for feature bits which conflict or are synthesized */ 73 #define X86_FEATURE_CXMMX (3*32+ 0) /* Cyrix MMX extensions */ 74 #define X86_FEATURE_K6_MTRR (3*32+ 1) /* AMD K6 nonstandard MTRRs */ 75 #define X86_FEATURE_CYRIX_ARR (3*32+ 2) /* Cyrix ARRs (= MTRRs) */ 76 #define X86_FEATURE_CENTAUR_MCR (3*32+ 3) /* Centaur MCRs (= MTRRs) */ 77 /* cpu types for specific tunings: */ 78 #define X86_FEATURE_K8 (3*32+ 4) /* "" Opteron, Athlon64 */ 79 #define X86_FEATURE_K7 (3*32+ 5) /* "" Athlon */ 80 #define X86_FEATURE_P3 (3*32+ 6) /* "" P3 */ 81 #define X86_FEATURE_P4 (3*32+ 7) /* "" P4 */ 82 #define X86_FEATURE_CONSTANT_TSC (3*32+ 8) /* TSC ticks at a constant rate */ 83 #define X86_FEATURE_UP (3*32+ 9) /* smp kernel running on up */ 84 #define X86_FEATURE_FXSAVE_LEAK (3*32+10) /* "" FXSAVE leaks FOP/FIP/FOP */ 85 #define X86_FEATURE_ARCH_PERFMON (3*32+11) /* Intel Architectural PerfMon */ 86 #define X86_FEATURE_PEBS (3*32+12) /* Precise-Event Based Sampling */ 87 #define X86_FEATURE_BTS (3*32+13) /* Branch Trace Store */ 88 #define X86_FEATURE_SYSCALL32 (3*32+14) /* "" syscall in ia32 userspace */ 89 #define X86_FEATURE_SYSENTER32 (3*32+15) /* "" sysenter in ia32 userspace */ 90 #define X86_FEATURE_REP_GOOD (3*32+16) /* rep microcode works well */ 91 #define X86_FEATURE_MFENCE_RDTSC (3*32+17) /* "" Mfence synchronizes RDTSC */ 92 #define X86_FEATURE_LFENCE_RDTSC (3*32+18) /* "" Lfence synchronizes RDTSC */ 93 #define X86_FEATURE_11AP (3*32+19) /* "" Bad local APIC aka 11AP */ 94 #define X86_FEATURE_NOPL (3*32+20) /* The NOPL (0F 1F) instructions */ 95 #define X86_FEATURE_ALWAYS (3*32+21) /* "" Always-present feature */ 96 #define X86_FEATURE_XTOPOLOGY (3*32+22) /* cpu topology enum extensions */ 97 #define X86_FEATURE_TSC_RELIABLE (3*32+23) /* TSC is known to be reliable */ 98 #define X86_FEATURE_NONSTOP_TSC (3*32+24) /* TSC does not stop in C states */ 99 #define X86_FEATURE_CLFLUSH_MONITOR (3*32+25) /* "" clflush reqd with monitor */ 100 #define X86_FEATURE_EXTD_APICID (3*32+26) /* has extended APICID (8 bits) */ 101 #define X86_FEATURE_AMD_DCM (3*32+27) /* multi-node processor */ 102 #define X86_FEATURE_APERFMPERF (3*32+28) /* APERFMPERF */ 103 #define X86_FEATURE_EAGER_FPU (3*32+29) /* "eagerfpu" Non lazy FPU restore */ 104 #define X86_FEATURE_NONSTOP_TSC_S3 (3*32+30) /* TSC doesn't stop in S3 state */ 105 106 /* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */ 107 #define X86_FEATURE_XMM3 (4*32+ 0) /* "pni" SSE-3 */ 108 #define X86_FEATURE_PCLMULQDQ (4*32+ 1) /* PCLMULQDQ instruction */ 109 #define X86_FEATURE_DTES64 (4*32+ 2) /* 64-bit Debug Store */ 110 #define X86_FEATURE_MWAIT (4*32+ 3) /* "monitor" Monitor/Mwait support */ 111 #define X86_FEATURE_DSCPL (4*32+ 4) /* "ds_cpl" CPL Qual. Debug Store */ 112 #define X86_FEATURE_VMX (4*32+ 5) /* Hardware virtualization */ 113 #define X86_FEATURE_SMX (4*32+ 6) /* Safer mode */ 114 #define X86_FEATURE_EST (4*32+ 7) /* Enhanced SpeedStep */ 115 #define X86_FEATURE_TM2 (4*32+ 8) /* Thermal Monitor 2 */ 116 #define X86_FEATURE_SSSE3 (4*32+ 9) /* Supplemental SSE-3 */ 117 #define X86_FEATURE_CID (4*32+10) /* Context ID */ 118 #define X86_FEATURE_FMA (4*32+12) /* Fused multiply-add */ 119 #define X86_FEATURE_CX16 (4*32+13) /* CMPXCHG16B */ 120 #define X86_FEATURE_XTPR (4*32+14) /* Send Task Priority Messages */ 121 #define X86_FEATURE_PDCM (4*32+15) /* Performance Capabilities */ 122 #define X86_FEATURE_PCID (4*32+17) /* Process Context Identifiers */ 123 #define X86_FEATURE_DCA (4*32+18) /* Direct Cache Access */ 124 #define X86_FEATURE_XMM4_1 (4*32+19) /* "sse4_1" SSE-4.1 */ 125 #define X86_FEATURE_XMM4_2 (4*32+20) /* "sse4_2" SSE-4.2 */ 126 #define X86_FEATURE_X2APIC (4*32+21) /* x2APIC */ 127 #define X86_FEATURE_MOVBE (4*32+22) /* MOVBE instruction */ 128 #define X86_FEATURE_POPCNT (4*32+23) /* POPCNT instruction */ 129 #define X86_FEATURE_TSC_DEADLINE_TIMER (4*32+24) /* Tsc deadline timer */ 130 #define X86_FEATURE_AES (4*32+25) /* AES instructions */ 131 #define X86_FEATURE_XSAVE (4*32+26) /* XSAVE/XRSTOR/XSETBV/XGETBV */ 132 #define X86_FEATURE_OSXSAVE (4*32+27) /* "" XSAVE enabled in the OS */ 133 #define X86_FEATURE_AVX (4*32+28) /* Advanced Vector Extensions */ 134 #define X86_FEATURE_F16C (4*32+29) /* 16-bit fp conversions */ 135 #define X86_FEATURE_RDRAND (4*32+30) /* The RDRAND instruction */ 136 #define X86_FEATURE_HYPERVISOR (4*32+31) /* Running on a hypervisor */ 137 138 /* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */ 139 #define X86_FEATURE_XSTORE (5*32+ 2) /* "rng" RNG present (xstore) */ 140 #define X86_FEATURE_XSTORE_EN (5*32+ 3) /* "rng_en" RNG enabled */ 141 #define X86_FEATURE_XCRYPT (5*32+ 6) /* "ace" on-CPU crypto (xcrypt) */ 142 #define X86_FEATURE_XCRYPT_EN (5*32+ 7) /* "ace_en" on-CPU crypto enabled */ 143 #define X86_FEATURE_ACE2 (5*32+ 8) /* Advanced Cryptography Engine v2 */ 144 #define X86_FEATURE_ACE2_EN (5*32+ 9) /* ACE v2 enabled */ 145 #define X86_FEATURE_PHE (5*32+10) /* PadLock Hash Engine */ 146 #define X86_FEATURE_PHE_EN (5*32+11) /* PHE enabled */ 147 #define X86_FEATURE_PMM (5*32+12) /* PadLock Montgomery Multiplier */ 148 #define X86_FEATURE_PMM_EN (5*32+13) /* PMM enabled */ 149 150 /* More extended AMD flags: CPUID level 0x80000001, ecx, word 6 */ 151 #define X86_FEATURE_LAHF_LM (6*32+ 0) /* LAHF/SAHF in long mode */ 152 #define X86_FEATURE_CMP_LEGACY (6*32+ 1) /* If yes HyperThreading not valid */ 153 #define X86_FEATURE_SVM (6*32+ 2) /* Secure virtual machine */ 154 #define X86_FEATURE_EXTAPIC (6*32+ 3) /* Extended APIC space */ 155 #define X86_FEATURE_CR8_LEGACY (6*32+ 4) /* CR8 in 32-bit mode */ 156 #define X86_FEATURE_ABM (6*32+ 5) /* Advanced bit manipulation */ 157 #define X86_FEATURE_SSE4A (6*32+ 6) /* SSE-4A */ 158 #define X86_FEATURE_MISALIGNSSE (6*32+ 7) /* Misaligned SSE mode */ 159 #define X86_FEATURE_3DNOWPREFETCH (6*32+ 8) /* 3DNow prefetch instructions */ 160 #define X86_FEATURE_OSVW (6*32+ 9) /* OS Visible Workaround */ 161 #define X86_FEATURE_IBS (6*32+10) /* Instruction Based Sampling */ 162 #define X86_FEATURE_XOP (6*32+11) /* extended AVX instructions */ 163 #define X86_FEATURE_SKINIT (6*32+12) /* SKINIT/STGI instructions */ 164 #define X86_FEATURE_WDT (6*32+13) /* Watchdog timer */ 165 #define X86_FEATURE_LWP (6*32+15) /* Light Weight Profiling */ 166 #define X86_FEATURE_FMA4 (6*32+16) /* 4 operands MAC instructions */ 167 #define X86_FEATURE_TCE (6*32+17) /* translation cache extension */ 168 #define X86_FEATURE_NODEID_MSR (6*32+19) /* NodeId MSR */ 169 #define X86_FEATURE_TBM (6*32+21) /* trailing bit manipulations */ 170 #define X86_FEATURE_TOPOEXT (6*32+22) /* topology extensions CPUID leafs */ 171 #define X86_FEATURE_PERFCTR_CORE (6*32+23) /* core performance counter extensions */ 172 #define X86_FEATURE_PERFCTR_NB (6*32+24) /* NB performance counter extensions */ 173 #define X86_FEATURE_PERFCTR_L2 (6*32+28) /* L2 performance counter extensions */ 174 175 /* 176 * Auxiliary flags: Linux defined - For features scattered in various 177 * CPUID levels like 0x6, 0xA etc, word 7 178 */ 179 #define X86_FEATURE_IDA (7*32+ 0) /* Intel Dynamic Acceleration */ 180 #define X86_FEATURE_ARAT (7*32+ 1) /* Always Running APIC Timer */ 181 #define X86_FEATURE_CPB (7*32+ 2) /* AMD Core Performance Boost */ 182 #define X86_FEATURE_EPB (7*32+ 3) /* IA32_ENERGY_PERF_BIAS support */ 183 #define X86_FEATURE_XSAVEOPT (7*32+ 4) /* Optimized Xsave */ 184 #define X86_FEATURE_PLN (7*32+ 5) /* Intel Power Limit Notification */ 185 #define X86_FEATURE_PTS (7*32+ 6) /* Intel Package Thermal Status */ 186 #define X86_FEATURE_DTHERM (7*32+ 7) /* Digital Thermal Sensor */ 187 #define X86_FEATURE_HW_PSTATE (7*32+ 8) /* AMD HW-PState */ 188 #define X86_FEATURE_PROC_FEEDBACK (7*32+ 9) /* AMD ProcFeedbackInterface */ 189 190 /* Virtualization flags: Linux defined, word 8 */ 191 #define X86_FEATURE_TPR_SHADOW (8*32+ 0) /* Intel TPR Shadow */ 192 #define X86_FEATURE_VNMI (8*32+ 1) /* Intel Virtual NMI */ 193 #define X86_FEATURE_FLEXPRIORITY (8*32+ 2) /* Intel FlexPriority */ 194 #define X86_FEATURE_EPT (8*32+ 3) /* Intel Extended Page Table */ 195 #define X86_FEATURE_VPID (8*32+ 4) /* Intel Virtual Processor ID */ 196 #define X86_FEATURE_NPT (8*32+ 5) /* AMD Nested Page Table support */ 197 #define X86_FEATURE_LBRV (8*32+ 6) /* AMD LBR Virtualization support */ 198 #define X86_FEATURE_SVML (8*32+ 7) /* "svm_lock" AMD SVM locking MSR */ 199 #define X86_FEATURE_NRIPS (8*32+ 8) /* "nrip_save" AMD SVM next_rip save */ 200 #define X86_FEATURE_TSCRATEMSR (8*32+ 9) /* "tsc_scale" AMD TSC scaling support */ 201 #define X86_FEATURE_VMCBCLEAN (8*32+10) /* "vmcb_clean" AMD VMCB clean bits support */ 202 #define X86_FEATURE_FLUSHBYASID (8*32+11) /* AMD flush-by-ASID support */ 203 #define X86_FEATURE_DECODEASSISTS (8*32+12) /* AMD Decode Assists support */ 204 #define X86_FEATURE_PAUSEFILTER (8*32+13) /* AMD filtered pause intercept */ 205 #define X86_FEATURE_PFTHRESHOLD (8*32+14) /* AMD pause filter threshold */ 206 207 208 /* Intel-defined CPU features, CPUID level 0x00000007:0 (ebx), word 9 */ 209 #define X86_FEATURE_FSGSBASE (9*32+ 0) /* {RD/WR}{FS/GS}BASE instructions*/ 210 #define X86_FEATURE_TSC_ADJUST (9*32+ 1) /* TSC adjustment MSR 0x3b */ 211 #define X86_FEATURE_BMI1 (9*32+ 3) /* 1st group bit manipulation extensions */ 212 #define X86_FEATURE_HLE (9*32+ 4) /* Hardware Lock Elision */ 213 #define X86_FEATURE_AVX2 (9*32+ 5) /* AVX2 instructions */ 214 #define X86_FEATURE_SMEP (9*32+ 7) /* Supervisor Mode Execution Protection */ 215 #define X86_FEATURE_BMI2 (9*32+ 8) /* 2nd group bit manipulation extensions */ 216 #define X86_FEATURE_ERMS (9*32+ 9) /* Enhanced REP MOVSB/STOSB */ 217 #define X86_FEATURE_INVPCID (9*32+10) /* Invalidate Processor Context ID */ 218 #define X86_FEATURE_RTM (9*32+11) /* Restricted Transactional Memory */ 219 #define X86_FEATURE_MPX (9*32+14) /* Memory Protection Extension */ 220 #define X86_FEATURE_AVX512F (9*32+16) /* AVX-512 Foundation */ 221 #define X86_FEATURE_RDSEED (9*32+18) /* The RDSEED instruction */ 222 #define X86_FEATURE_ADX (9*32+19) /* The ADCX and ADOX instructions */ 223 #define X86_FEATURE_SMAP (9*32+20) /* Supervisor Mode Access Prevention */ 224 #define X86_FEATURE_CLFLUSHOPT (9*32+23) /* CLFLUSHOPT instruction */ 225 #define X86_FEATURE_AVX512PF (9*32+26) /* AVX-512 Prefetch */ 226 #define X86_FEATURE_AVX512ER (9*32+27) /* AVX-512 Exponential and Reciprocal */ 227 #define X86_FEATURE_AVX512CD (9*32+28) /* AVX-512 Conflict Detection */ 228 229 /* 230 * BUG word(s) 231 */ 232 #define X86_BUG(x) (NCAPINTS*32 + (x)) 233 234 #define X86_BUG_F00F X86_BUG(0) /* Intel F00F */ 235 #define X86_BUG_FDIV X86_BUG(1) /* FPU FDIV */ 236 #define X86_BUG_COMA X86_BUG(2) /* Cyrix 6x86 coma */ 237 #define X86_BUG_AMD_TLB_MMATCH X86_BUG(3) /* AMD Erratum 383 */ 238 #define X86_BUG_AMD_APIC_C1E X86_BUG(4) /* AMD Erratum 400 */ 239 240 #if defined(__KERNEL__) && !defined(__ASSEMBLY__) 241 242 #include <asm/asm.h> 243 #include <linux/bitops.h> 244 245 extern const char * const x86_cap_flags[NCAPINTS*32]; 246 extern const char * const x86_power_flags[32]; 247 248 #define test_cpu_cap(c, bit) \ 249 test_bit(bit, (unsigned long *)((c)->x86_capability)) 250 251 #define REQUIRED_MASK_BIT_SET(bit) \ 252 ( (((bit)>>5)==0 && (1UL<<((bit)&31) & REQUIRED_MASK0)) || \ 253 (((bit)>>5)==1 && (1UL<<((bit)&31) & REQUIRED_MASK1)) || \ 254 (((bit)>>5)==2 && (1UL<<((bit)&31) & REQUIRED_MASK2)) || \ 255 (((bit)>>5)==3 && (1UL<<((bit)&31) & REQUIRED_MASK3)) || \ 256 (((bit)>>5)==4 && (1UL<<((bit)&31) & REQUIRED_MASK4)) || \ 257 (((bit)>>5)==5 && (1UL<<((bit)&31) & REQUIRED_MASK5)) || \ 258 (((bit)>>5)==6 && (1UL<<((bit)&31) & REQUIRED_MASK6)) || \ 259 (((bit)>>5)==7 && (1UL<<((bit)&31) & REQUIRED_MASK7)) || \ 260 (((bit)>>5)==8 && (1UL<<((bit)&31) & REQUIRED_MASK8)) || \ 261 (((bit)>>5)==9 && (1UL<<((bit)&31) & REQUIRED_MASK9)) ) 262 263 #define cpu_has(c, bit) \ 264 (__builtin_constant_p(bit) && REQUIRED_MASK_BIT_SET(bit) ? 1 : \ 265 test_cpu_cap(c, bit)) 266 267 #define this_cpu_has(bit) \ 268 (__builtin_constant_p(bit) && REQUIRED_MASK_BIT_SET(bit) ? 1 : \ 269 x86_this_cpu_test_bit(bit, (unsigned long *)&cpu_info.x86_capability)) 270 271 #define boot_cpu_has(bit) cpu_has(&boot_cpu_data, bit) 272 273 #define set_cpu_cap(c, bit) set_bit(bit, (unsigned long *)((c)->x86_capability)) 274 #define clear_cpu_cap(c, bit) clear_bit(bit, (unsigned long *)((c)->x86_capability)) 275 #define setup_clear_cpu_cap(bit) do { \ 276 clear_cpu_cap(&boot_cpu_data, bit); \ 277 set_bit(bit, (unsigned long *)cpu_caps_cleared); \ 278 } while (0) 279 #define setup_force_cpu_cap(bit) do { \ 280 set_cpu_cap(&boot_cpu_data, bit); \ 281 set_bit(bit, (unsigned long *)cpu_caps_set); \ 282 } while (0) 283 284 #define cpu_has_fpu boot_cpu_has(X86_FEATURE_FPU) 285 #define cpu_has_vme boot_cpu_has(X86_FEATURE_VME) 286 #define cpu_has_de boot_cpu_has(X86_FEATURE_DE) 287 #define cpu_has_pse boot_cpu_has(X86_FEATURE_PSE) 288 #define cpu_has_tsc boot_cpu_has(X86_FEATURE_TSC) 289 #define cpu_has_pae boot_cpu_has(X86_FEATURE_PAE) 290 #define cpu_has_pge boot_cpu_has(X86_FEATURE_PGE) 291 #define cpu_has_apic boot_cpu_has(X86_FEATURE_APIC) 292 #define cpu_has_sep boot_cpu_has(X86_FEATURE_SEP) 293 #define cpu_has_mtrr boot_cpu_has(X86_FEATURE_MTRR) 294 #define cpu_has_mmx boot_cpu_has(X86_FEATURE_MMX) 295 #define cpu_has_fxsr boot_cpu_has(X86_FEATURE_FXSR) 296 #define cpu_has_xmm boot_cpu_has(X86_FEATURE_XMM) 297 #define cpu_has_xmm2 boot_cpu_has(X86_FEATURE_XMM2) 298 #define cpu_has_xmm3 boot_cpu_has(X86_FEATURE_XMM3) 299 #define cpu_has_ssse3 boot_cpu_has(X86_FEATURE_SSSE3) 300 #define cpu_has_aes boot_cpu_has(X86_FEATURE_AES) 301 #define cpu_has_avx boot_cpu_has(X86_FEATURE_AVX) 302 #define cpu_has_avx2 boot_cpu_has(X86_FEATURE_AVX2) 303 #define cpu_has_ht boot_cpu_has(X86_FEATURE_HT) 304 #define cpu_has_mp boot_cpu_has(X86_FEATURE_MP) 305 #define cpu_has_nx boot_cpu_has(X86_FEATURE_NX) 306 #define cpu_has_k6_mtrr boot_cpu_has(X86_FEATURE_K6_MTRR) 307 #define cpu_has_cyrix_arr boot_cpu_has(X86_FEATURE_CYRIX_ARR) 308 #define cpu_has_centaur_mcr boot_cpu_has(X86_FEATURE_CENTAUR_MCR) 309 #define cpu_has_xstore boot_cpu_has(X86_FEATURE_XSTORE) 310 #define cpu_has_xstore_enabled boot_cpu_has(X86_FEATURE_XSTORE_EN) 311 #define cpu_has_xcrypt boot_cpu_has(X86_FEATURE_XCRYPT) 312 #define cpu_has_xcrypt_enabled boot_cpu_has(X86_FEATURE_XCRYPT_EN) 313 #define cpu_has_ace2 boot_cpu_has(X86_FEATURE_ACE2) 314 #define cpu_has_ace2_enabled boot_cpu_has(X86_FEATURE_ACE2_EN) 315 #define cpu_has_phe boot_cpu_has(X86_FEATURE_PHE) 316 #define cpu_has_phe_enabled boot_cpu_has(X86_FEATURE_PHE_EN) 317 #define cpu_has_pmm boot_cpu_has(X86_FEATURE_PMM) 318 #define cpu_has_pmm_enabled boot_cpu_has(X86_FEATURE_PMM_EN) 319 #define cpu_has_ds boot_cpu_has(X86_FEATURE_DS) 320 #define cpu_has_pebs boot_cpu_has(X86_FEATURE_PEBS) 321 #define cpu_has_clflush boot_cpu_has(X86_FEATURE_CLFLUSH) 322 #define cpu_has_bts boot_cpu_has(X86_FEATURE_BTS) 323 #define cpu_has_gbpages boot_cpu_has(X86_FEATURE_GBPAGES) 324 #define cpu_has_arch_perfmon boot_cpu_has(X86_FEATURE_ARCH_PERFMON) 325 #define cpu_has_pat boot_cpu_has(X86_FEATURE_PAT) 326 #define cpu_has_xmm4_1 boot_cpu_has(X86_FEATURE_XMM4_1) 327 #define cpu_has_xmm4_2 boot_cpu_has(X86_FEATURE_XMM4_2) 328 #define cpu_has_x2apic boot_cpu_has(X86_FEATURE_X2APIC) 329 #define cpu_has_xsave boot_cpu_has(X86_FEATURE_XSAVE) 330 #define cpu_has_xsaveopt boot_cpu_has(X86_FEATURE_XSAVEOPT) 331 #define cpu_has_osxsave boot_cpu_has(X86_FEATURE_OSXSAVE) 332 #define cpu_has_hypervisor boot_cpu_has(X86_FEATURE_HYPERVISOR) 333 #define cpu_has_pclmulqdq boot_cpu_has(X86_FEATURE_PCLMULQDQ) 334 #define cpu_has_perfctr_core boot_cpu_has(X86_FEATURE_PERFCTR_CORE) 335 #define cpu_has_perfctr_nb boot_cpu_has(X86_FEATURE_PERFCTR_NB) 336 #define cpu_has_perfctr_l2 boot_cpu_has(X86_FEATURE_PERFCTR_L2) 337 #define cpu_has_cx8 boot_cpu_has(X86_FEATURE_CX8) 338 #define cpu_has_cx16 boot_cpu_has(X86_FEATURE_CX16) 339 #define cpu_has_eager_fpu boot_cpu_has(X86_FEATURE_EAGER_FPU) 340 #define cpu_has_topoext boot_cpu_has(X86_FEATURE_TOPOEXT) 341 342 #ifdef CONFIG_X86_64 343 344 #undef cpu_has_vme 345 #define cpu_has_vme 0 346 347 #undef cpu_has_pae 348 #define cpu_has_pae ___BUG___ 349 350 #undef cpu_has_mp 351 #define cpu_has_mp 1 352 353 #undef cpu_has_k6_mtrr 354 #define cpu_has_k6_mtrr 0 355 356 #undef cpu_has_cyrix_arr 357 #define cpu_has_cyrix_arr 0 358 359 #undef cpu_has_centaur_mcr 360 #define cpu_has_centaur_mcr 0 361 362 #endif /* CONFIG_X86_64 */ 363 364 #if __GNUC__ >= 4 365 extern void warn_pre_alternatives(void); 366 extern bool __static_cpu_has_safe(u16 bit); 367 368 /* 369 * Static testing of CPU features. Used the same as boot_cpu_has(). 370 * These are only valid after alternatives have run, but will statically 371 * patch the target code for additional performance. 372 */ 373 static __always_inline __pure bool __static_cpu_has(u16 bit) 374 { 375 #ifdef CC_HAVE_ASM_GOTO 376 377 #ifdef CONFIG_X86_DEBUG_STATIC_CPU_HAS 378 379 /* 380 * Catch too early usage of this before alternatives 381 * have run. 382 */ 383 asm_volatile_goto("1: jmp %l[t_warn]\n" 384 "2:\n" 385 ".section .altinstructions,\"a\"\n" 386 " .long 1b - .\n" 387 " .long 0\n" /* no replacement */ 388 " .word %P0\n" /* 1: do replace */ 389 " .byte 2b - 1b\n" /* source len */ 390 " .byte 0\n" /* replacement len */ 391 ".previous\n" 392 /* skipping size check since replacement size = 0 */ 393 : : "i" (X86_FEATURE_ALWAYS) : : t_warn); 394 395 #endif 396 397 asm_volatile_goto("1: jmp %l[t_no]\n" 398 "2:\n" 399 ".section .altinstructions,\"a\"\n" 400 " .long 1b - .\n" 401 " .long 0\n" /* no replacement */ 402 " .word %P0\n" /* feature bit */ 403 " .byte 2b - 1b\n" /* source len */ 404 " .byte 0\n" /* replacement len */ 405 ".previous\n" 406 /* skipping size check since replacement size = 0 */ 407 : : "i" (bit) : : t_no); 408 return true; 409 t_no: 410 return false; 411 412 #ifdef CONFIG_X86_DEBUG_STATIC_CPU_HAS 413 t_warn: 414 warn_pre_alternatives(); 415 return false; 416 #endif 417 418 #else /* CC_HAVE_ASM_GOTO */ 419 420 u8 flag; 421 /* Open-coded due to __stringify() in ALTERNATIVE() */ 422 asm volatile("1: movb $0,%0\n" 423 "2:\n" 424 ".section .altinstructions,\"a\"\n" 425 " .long 1b - .\n" 426 " .long 3f - .\n" 427 " .word %P1\n" /* feature bit */ 428 " .byte 2b - 1b\n" /* source len */ 429 " .byte 4f - 3f\n" /* replacement len */ 430 ".previous\n" 431 ".section .discard,\"aw\",@progbits\n" 432 " .byte 0xff + (4f-3f) - (2b-1b)\n" /* size check */ 433 ".previous\n" 434 ".section .altinstr_replacement,\"ax\"\n" 435 "3: movb $1,%0\n" 436 "4:\n" 437 ".previous\n" 438 : "=qm" (flag) : "i" (bit)); 439 return flag; 440 441 #endif /* CC_HAVE_ASM_GOTO */ 442 } 443 444 #define static_cpu_has(bit) \ 445 ( \ 446 __builtin_constant_p(boot_cpu_has(bit)) ? \ 447 boot_cpu_has(bit) : \ 448 __builtin_constant_p(bit) ? \ 449 __static_cpu_has(bit) : \ 450 boot_cpu_has(bit) \ 451 ) 452 453 static __always_inline __pure bool _static_cpu_has_safe(u16 bit) 454 { 455 #ifdef CC_HAVE_ASM_GOTO 456 /* 457 * We need to spell the jumps to the compiler because, depending on the offset, 458 * the replacement jump can be bigger than the original jump, and this we cannot 459 * have. Thus, we force the jump to the widest, 4-byte, signed relative 460 * offset even though the last would often fit in less bytes. 461 */ 462 asm_volatile_goto("1: .byte 0xe9\n .long %l[t_dynamic] - 2f\n" 463 "2:\n" 464 ".section .altinstructions,\"a\"\n" 465 " .long 1b - .\n" /* src offset */ 466 " .long 3f - .\n" /* repl offset */ 467 " .word %P1\n" /* always replace */ 468 " .byte 2b - 1b\n" /* src len */ 469 " .byte 4f - 3f\n" /* repl len */ 470 ".previous\n" 471 ".section .altinstr_replacement,\"ax\"\n" 472 "3: .byte 0xe9\n .long %l[t_no] - 2b\n" 473 "4:\n" 474 ".previous\n" 475 ".section .altinstructions,\"a\"\n" 476 " .long 1b - .\n" /* src offset */ 477 " .long 0\n" /* no replacement */ 478 " .word %P0\n" /* feature bit */ 479 " .byte 2b - 1b\n" /* src len */ 480 " .byte 0\n" /* repl len */ 481 ".previous\n" 482 : : "i" (bit), "i" (X86_FEATURE_ALWAYS) 483 : : t_dynamic, t_no); 484 return true; 485 t_no: 486 return false; 487 t_dynamic: 488 return __static_cpu_has_safe(bit); 489 #else 490 u8 flag; 491 /* Open-coded due to __stringify() in ALTERNATIVE() */ 492 asm volatile("1: movb $2,%0\n" 493 "2:\n" 494 ".section .altinstructions,\"a\"\n" 495 " .long 1b - .\n" /* src offset */ 496 " .long 3f - .\n" /* repl offset */ 497 " .word %P2\n" /* always replace */ 498 " .byte 2b - 1b\n" /* source len */ 499 " .byte 4f - 3f\n" /* replacement len */ 500 ".previous\n" 501 ".section .discard,\"aw\",@progbits\n" 502 " .byte 0xff + (4f-3f) - (2b-1b)\n" /* size check */ 503 ".previous\n" 504 ".section .altinstr_replacement,\"ax\"\n" 505 "3: movb $0,%0\n" 506 "4:\n" 507 ".previous\n" 508 ".section .altinstructions,\"a\"\n" 509 " .long 1b - .\n" /* src offset */ 510 " .long 5f - .\n" /* repl offset */ 511 " .word %P1\n" /* feature bit */ 512 " .byte 4b - 3b\n" /* src len */ 513 " .byte 6f - 5f\n" /* repl len */ 514 ".previous\n" 515 ".section .discard,\"aw\",@progbits\n" 516 " .byte 0xff + (6f-5f) - (4b-3b)\n" /* size check */ 517 ".previous\n" 518 ".section .altinstr_replacement,\"ax\"\n" 519 "5: movb $1,%0\n" 520 "6:\n" 521 ".previous\n" 522 : "=qm" (flag) 523 : "i" (bit), "i" (X86_FEATURE_ALWAYS)); 524 return (flag == 2 ? __static_cpu_has_safe(bit) : flag); 525 #endif /* CC_HAVE_ASM_GOTO */ 526 } 527 528 #define static_cpu_has_safe(bit) \ 529 ( \ 530 __builtin_constant_p(boot_cpu_has(bit)) ? \ 531 boot_cpu_has(bit) : \ 532 _static_cpu_has_safe(bit) \ 533 ) 534 #else 535 /* 536 * gcc 3.x is too stupid to do the static test; fall back to dynamic. 537 */ 538 #define static_cpu_has(bit) boot_cpu_has(bit) 539 #define static_cpu_has_safe(bit) boot_cpu_has(bit) 540 #endif 541 542 #define cpu_has_bug(c, bit) cpu_has(c, (bit)) 543 #define set_cpu_bug(c, bit) set_cpu_cap(c, (bit)) 544 #define clear_cpu_bug(c, bit) clear_cpu_cap(c, (bit)); 545 546 #define static_cpu_has_bug(bit) static_cpu_has((bit)) 547 #define boot_cpu_has_bug(bit) cpu_has_bug(&boot_cpu_data, (bit)) 548 549 #define MAX_CPU_FEATURES (NCAPINTS * 32) 550 #define cpu_have_feature boot_cpu_has 551 552 #define CPU_FEATURE_TYPEFMT "x86,ven%04Xfam%04Xmod%04X" 553 #define CPU_FEATURE_TYPEVAL boot_cpu_data.x86_vendor, boot_cpu_data.x86, \ 554 boot_cpu_data.x86_model 555 556 #endif /* defined(__KERNEL__) && !defined(__ASSEMBLY__) */ 557 558 #endif /* _ASM_X86_CPUFEATURE_H */ 559