1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _ASM_X86_BITOPS_H 3 #define _ASM_X86_BITOPS_H 4 5 /* 6 * Copyright 1992, Linus Torvalds. 7 * 8 * Note: inlines with more than a single statement should be marked 9 * __always_inline to avoid problems with older gcc's inlining heuristics. 10 */ 11 12 #ifndef _LINUX_BITOPS_H 13 #error only <linux/bitops.h> can be included directly 14 #endif 15 16 #include <linux/compiler.h> 17 #include <asm/alternative.h> 18 #include <asm/rmwcc.h> 19 #include <asm/barrier.h> 20 21 #if BITS_PER_LONG == 32 22 # define _BITOPS_LONG_SHIFT 5 23 #elif BITS_PER_LONG == 64 24 # define _BITOPS_LONG_SHIFT 6 25 #else 26 # error "Unexpected BITS_PER_LONG" 27 #endif 28 29 #define BIT_64(n) (U64_C(1) << (n)) 30 31 /* 32 * These have to be done with inline assembly: that way the bit-setting 33 * is guaranteed to be atomic. All bit operations return 0 if the bit 34 * was cleared before the operation and != 0 if it was not. 35 * 36 * bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1). 37 */ 38 39 #define RLONG_ADDR(x) "m" (*(volatile long *) (x)) 40 #define WBYTE_ADDR(x) "+m" (*(volatile char *) (x)) 41 42 #define ADDR RLONG_ADDR(addr) 43 44 /* 45 * We do the locked ops that don't return the old value as 46 * a mask operation on a byte. 47 */ 48 #define CONST_MASK_ADDR(nr, addr) WBYTE_ADDR((void *)(addr) + ((nr)>>3)) 49 #define CONST_MASK(nr) (1 << ((nr) & 7)) 50 51 static __always_inline void 52 arch_set_bit(long nr, volatile unsigned long *addr) 53 { 54 if (__builtin_constant_p(nr)) { 55 asm volatile(LOCK_PREFIX "orb %b1,%0" 56 : CONST_MASK_ADDR(nr, addr) 57 : "iq" (CONST_MASK(nr)) 58 : "memory"); 59 } else { 60 asm volatile(LOCK_PREFIX __ASM_SIZE(bts) " %1,%0" 61 : : RLONG_ADDR(addr), "Ir" (nr) : "memory"); 62 } 63 } 64 65 static __always_inline void 66 arch___set_bit(unsigned long nr, volatile unsigned long *addr) 67 { 68 asm volatile(__ASM_SIZE(bts) " %1,%0" : : ADDR, "Ir" (nr) : "memory"); 69 } 70 71 static __always_inline void 72 arch_clear_bit(long nr, volatile unsigned long *addr) 73 { 74 if (__builtin_constant_p(nr)) { 75 asm volatile(LOCK_PREFIX "andb %b1,%0" 76 : CONST_MASK_ADDR(nr, addr) 77 : "iq" (~CONST_MASK(nr))); 78 } else { 79 asm volatile(LOCK_PREFIX __ASM_SIZE(btr) " %1,%0" 80 : : RLONG_ADDR(addr), "Ir" (nr) : "memory"); 81 } 82 } 83 84 static __always_inline void 85 arch_clear_bit_unlock(long nr, volatile unsigned long *addr) 86 { 87 barrier(); 88 arch_clear_bit(nr, addr); 89 } 90 91 static __always_inline void 92 arch___clear_bit(unsigned long nr, volatile unsigned long *addr) 93 { 94 asm volatile(__ASM_SIZE(btr) " %1,%0" : : ADDR, "Ir" (nr) : "memory"); 95 } 96 97 static __always_inline bool 98 arch_clear_bit_unlock_is_negative_byte(long nr, volatile unsigned long *addr) 99 { 100 bool negative; 101 asm volatile(LOCK_PREFIX "andb %2,%1" 102 CC_SET(s) 103 : CC_OUT(s) (negative), WBYTE_ADDR(addr) 104 : "ir" ((char) ~(1 << nr)) : "memory"); 105 return negative; 106 } 107 #define arch_clear_bit_unlock_is_negative_byte \ 108 arch_clear_bit_unlock_is_negative_byte 109 110 static __always_inline void 111 arch___clear_bit_unlock(long nr, volatile unsigned long *addr) 112 { 113 arch___clear_bit(nr, addr); 114 } 115 116 static __always_inline void 117 arch___change_bit(unsigned long nr, volatile unsigned long *addr) 118 { 119 asm volatile(__ASM_SIZE(btc) " %1,%0" : : ADDR, "Ir" (nr) : "memory"); 120 } 121 122 static __always_inline void 123 arch_change_bit(long nr, volatile unsigned long *addr) 124 { 125 if (__builtin_constant_p(nr)) { 126 asm volatile(LOCK_PREFIX "xorb %b1,%0" 127 : CONST_MASK_ADDR(nr, addr) 128 : "iq" (CONST_MASK(nr))); 129 } else { 130 asm volatile(LOCK_PREFIX __ASM_SIZE(btc) " %1,%0" 131 : : RLONG_ADDR(addr), "Ir" (nr) : "memory"); 132 } 133 } 134 135 static __always_inline bool 136 arch_test_and_set_bit(long nr, volatile unsigned long *addr) 137 { 138 return GEN_BINARY_RMWcc(LOCK_PREFIX __ASM_SIZE(bts), *addr, c, "Ir", nr); 139 } 140 141 static __always_inline bool 142 arch_test_and_set_bit_lock(long nr, volatile unsigned long *addr) 143 { 144 return arch_test_and_set_bit(nr, addr); 145 } 146 147 static __always_inline bool 148 arch___test_and_set_bit(unsigned long nr, volatile unsigned long *addr) 149 { 150 bool oldbit; 151 152 asm(__ASM_SIZE(bts) " %2,%1" 153 CC_SET(c) 154 : CC_OUT(c) (oldbit) 155 : ADDR, "Ir" (nr) : "memory"); 156 return oldbit; 157 } 158 159 static __always_inline bool 160 arch_test_and_clear_bit(long nr, volatile unsigned long *addr) 161 { 162 return GEN_BINARY_RMWcc(LOCK_PREFIX __ASM_SIZE(btr), *addr, c, "Ir", nr); 163 } 164 165 /* 166 * Note: the operation is performed atomically with respect to 167 * the local CPU, but not other CPUs. Portable code should not 168 * rely on this behaviour. 169 * KVM relies on this behaviour on x86 for modifying memory that is also 170 * accessed from a hypervisor on the same CPU if running in a VM: don't change 171 * this without also updating arch/x86/kernel/kvm.c 172 */ 173 static __always_inline bool 174 arch___test_and_clear_bit(unsigned long nr, volatile unsigned long *addr) 175 { 176 bool oldbit; 177 178 asm volatile(__ASM_SIZE(btr) " %2,%1" 179 CC_SET(c) 180 : CC_OUT(c) (oldbit) 181 : ADDR, "Ir" (nr) : "memory"); 182 return oldbit; 183 } 184 185 static __always_inline bool 186 arch___test_and_change_bit(unsigned long nr, volatile unsigned long *addr) 187 { 188 bool oldbit; 189 190 asm volatile(__ASM_SIZE(btc) " %2,%1" 191 CC_SET(c) 192 : CC_OUT(c) (oldbit) 193 : ADDR, "Ir" (nr) : "memory"); 194 195 return oldbit; 196 } 197 198 static __always_inline bool 199 arch_test_and_change_bit(long nr, volatile unsigned long *addr) 200 { 201 return GEN_BINARY_RMWcc(LOCK_PREFIX __ASM_SIZE(btc), *addr, c, "Ir", nr); 202 } 203 204 static __always_inline bool constant_test_bit(long nr, const volatile unsigned long *addr) 205 { 206 return ((1UL << (nr & (BITS_PER_LONG-1))) & 207 (addr[nr >> _BITOPS_LONG_SHIFT])) != 0; 208 } 209 210 static __always_inline bool constant_test_bit_acquire(long nr, const volatile unsigned long *addr) 211 { 212 bool oldbit; 213 214 asm volatile("testb %2,%1" 215 CC_SET(nz) 216 : CC_OUT(nz) (oldbit) 217 : "m" (((unsigned char *)addr)[nr >> 3]), 218 "i" (1 << (nr & 7)) 219 :"memory"); 220 221 return oldbit; 222 } 223 224 static __always_inline bool variable_test_bit(long nr, volatile const unsigned long *addr) 225 { 226 bool oldbit; 227 228 asm volatile(__ASM_SIZE(bt) " %2,%1" 229 CC_SET(c) 230 : CC_OUT(c) (oldbit) 231 : "m" (*(unsigned long *)addr), "Ir" (nr) : "memory"); 232 233 return oldbit; 234 } 235 236 static __always_inline bool 237 arch_test_bit(unsigned long nr, const volatile unsigned long *addr) 238 { 239 return __builtin_constant_p(nr) ? constant_test_bit(nr, addr) : 240 variable_test_bit(nr, addr); 241 } 242 243 static __always_inline bool 244 arch_test_bit_acquire(unsigned long nr, const volatile unsigned long *addr) 245 { 246 return __builtin_constant_p(nr) ? constant_test_bit_acquire(nr, addr) : 247 variable_test_bit(nr, addr); 248 } 249 250 /** 251 * __ffs - find first set bit in word 252 * @word: The word to search 253 * 254 * Undefined if no bit exists, so code should check against 0 first. 255 */ 256 static __always_inline unsigned long __ffs(unsigned long word) 257 { 258 asm("rep; bsf %1,%0" 259 : "=r" (word) 260 : "rm" (word)); 261 return word; 262 } 263 264 /** 265 * ffz - find first zero bit in word 266 * @word: The word to search 267 * 268 * Undefined if no zero exists, so code should check against ~0UL first. 269 */ 270 static __always_inline unsigned long ffz(unsigned long word) 271 { 272 asm("rep; bsf %1,%0" 273 : "=r" (word) 274 : "r" (~word)); 275 return word; 276 } 277 278 /* 279 * __fls: find last set bit in word 280 * @word: The word to search 281 * 282 * Undefined if no set bit exists, so code should check against 0 first. 283 */ 284 static __always_inline unsigned long __fls(unsigned long word) 285 { 286 asm("bsr %1,%0" 287 : "=r" (word) 288 : "rm" (word)); 289 return word; 290 } 291 292 #undef ADDR 293 294 #ifdef __KERNEL__ 295 /** 296 * ffs - find first set bit in word 297 * @x: the word to search 298 * 299 * This is defined the same way as the libc and compiler builtin ffs 300 * routines, therefore differs in spirit from the other bitops. 301 * 302 * ffs(value) returns 0 if value is 0 or the position of the first 303 * set bit if value is nonzero. The first (least significant) bit 304 * is at position 1. 305 */ 306 static __always_inline int ffs(int x) 307 { 308 int r; 309 310 #ifdef CONFIG_X86_64 311 /* 312 * AMD64 says BSFL won't clobber the dest reg if x==0; Intel64 says the 313 * dest reg is undefined if x==0, but their CPU architect says its 314 * value is written to set it to the same as before, except that the 315 * top 32 bits will be cleared. 316 * 317 * We cannot do this on 32 bits because at the very least some 318 * 486 CPUs did not behave this way. 319 */ 320 asm("bsfl %1,%0" 321 : "=r" (r) 322 : "rm" (x), "0" (-1)); 323 #elif defined(CONFIG_X86_CMOV) 324 asm("bsfl %1,%0\n\t" 325 "cmovzl %2,%0" 326 : "=&r" (r) : "rm" (x), "r" (-1)); 327 #else 328 asm("bsfl %1,%0\n\t" 329 "jnz 1f\n\t" 330 "movl $-1,%0\n" 331 "1:" : "=r" (r) : "rm" (x)); 332 #endif 333 return r + 1; 334 } 335 336 /** 337 * fls - find last set bit in word 338 * @x: the word to search 339 * 340 * This is defined in a similar way as the libc and compiler builtin 341 * ffs, but returns the position of the most significant set bit. 342 * 343 * fls(value) returns 0 if value is 0 or the position of the last 344 * set bit if value is nonzero. The last (most significant) bit is 345 * at position 32. 346 */ 347 static __always_inline int fls(unsigned int x) 348 { 349 int r; 350 351 #ifdef CONFIG_X86_64 352 /* 353 * AMD64 says BSRL won't clobber the dest reg if x==0; Intel64 says the 354 * dest reg is undefined if x==0, but their CPU architect says its 355 * value is written to set it to the same as before, except that the 356 * top 32 bits will be cleared. 357 * 358 * We cannot do this on 32 bits because at the very least some 359 * 486 CPUs did not behave this way. 360 */ 361 asm("bsrl %1,%0" 362 : "=r" (r) 363 : "rm" (x), "0" (-1)); 364 #elif defined(CONFIG_X86_CMOV) 365 asm("bsrl %1,%0\n\t" 366 "cmovzl %2,%0" 367 : "=&r" (r) : "rm" (x), "rm" (-1)); 368 #else 369 asm("bsrl %1,%0\n\t" 370 "jnz 1f\n\t" 371 "movl $-1,%0\n" 372 "1:" : "=r" (r) : "rm" (x)); 373 #endif 374 return r + 1; 375 } 376 377 /** 378 * fls64 - find last set bit in a 64-bit word 379 * @x: the word to search 380 * 381 * This is defined in a similar way as the libc and compiler builtin 382 * ffsll, but returns the position of the most significant set bit. 383 * 384 * fls64(value) returns 0 if value is 0 or the position of the last 385 * set bit if value is nonzero. The last (most significant) bit is 386 * at position 64. 387 */ 388 #ifdef CONFIG_X86_64 389 static __always_inline int fls64(__u64 x) 390 { 391 int bitpos = -1; 392 /* 393 * AMD64 says BSRQ won't clobber the dest reg if x==0; Intel64 says the 394 * dest reg is undefined if x==0, but their CPU architect says its 395 * value is written to set it to the same as before. 396 */ 397 asm("bsrq %1,%q0" 398 : "+r" (bitpos) 399 : "rm" (x)); 400 return bitpos + 1; 401 } 402 #else 403 #include <asm-generic/bitops/fls64.h> 404 #endif 405 406 #include <asm-generic/bitops/sched.h> 407 408 #include <asm/arch_hweight.h> 409 410 #include <asm-generic/bitops/const_hweight.h> 411 412 #include <asm-generic/bitops/instrumented-atomic.h> 413 #include <asm-generic/bitops/instrumented-non-atomic.h> 414 #include <asm-generic/bitops/instrumented-lock.h> 415 416 #include <asm-generic/bitops/le.h> 417 418 #include <asm-generic/bitops/ext2-atomic-setbit.h> 419 420 #endif /* __KERNEL__ */ 421 #endif /* _ASM_X86_BITOPS_H */ 422