1 #ifndef _ASM_X86_APICDEF_H 2 #define _ASM_X86_APICDEF_H 3 4 /* 5 * Constants for various Intel APICs. (local APIC, IOAPIC, etc.) 6 * 7 * Alan Cox <Alan.Cox@linux.org>, 1995. 8 * Ingo Molnar <mingo@redhat.com>, 1999, 2000 9 */ 10 11 #define APIC_DEFAULT_PHYS_BASE 0xfee00000 12 13 #define APIC_ID 0x20 14 15 #define APIC_LVR 0x30 16 #define APIC_LVR_MASK 0xFF00FF 17 #define GET_APIC_VERSION(x) ((x) & 0xFFu) 18 #define GET_APIC_MAXLVT(x) (((x) >> 16) & 0xFFu) 19 #ifdef CONFIG_X86_32 20 # define APIC_INTEGRATED(x) ((x) & 0xF0u) 21 #else 22 # define APIC_INTEGRATED(x) (1) 23 #endif 24 #define APIC_XAPIC(x) ((x) >= 0x14) 25 #define APIC_TASKPRI 0x80 26 #define APIC_TPRI_MASK 0xFFu 27 #define APIC_ARBPRI 0x90 28 #define APIC_ARBPRI_MASK 0xFFu 29 #define APIC_PROCPRI 0xA0 30 #define APIC_EOI 0xB0 31 #define APIC_EIO_ACK 0x0 32 #define APIC_RRR 0xC0 33 #define APIC_LDR 0xD0 34 #define APIC_LDR_MASK (0xFFu << 24) 35 #define GET_APIC_LOGICAL_ID(x) (((x) >> 24) & 0xFFu) 36 #define SET_APIC_LOGICAL_ID(x) (((x) << 24)) 37 #define APIC_ALL_CPUS 0xFFu 38 #define APIC_DFR 0xE0 39 #define APIC_DFR_CLUSTER 0x0FFFFFFFul 40 #define APIC_DFR_FLAT 0xFFFFFFFFul 41 #define APIC_SPIV 0xF0 42 #define APIC_SPIV_FOCUS_DISABLED (1 << 9) 43 #define APIC_SPIV_APIC_ENABLED (1 << 8) 44 #define APIC_ISR 0x100 45 #define APIC_ISR_NR 0x8 /* Number of 32 bit ISR registers. */ 46 #define APIC_TMR 0x180 47 #define APIC_IRR 0x200 48 #define APIC_ESR 0x280 49 #define APIC_ESR_SEND_CS 0x00001 50 #define APIC_ESR_RECV_CS 0x00002 51 #define APIC_ESR_SEND_ACC 0x00004 52 #define APIC_ESR_RECV_ACC 0x00008 53 #define APIC_ESR_SENDILL 0x00020 54 #define APIC_ESR_RECVILL 0x00040 55 #define APIC_ESR_ILLREGA 0x00080 56 #define APIC_LVTCMCI 0x2f0 57 #define APIC_ICR 0x300 58 #define APIC_DEST_SELF 0x40000 59 #define APIC_DEST_ALLINC 0x80000 60 #define APIC_DEST_ALLBUT 0xC0000 61 #define APIC_ICR_RR_MASK 0x30000 62 #define APIC_ICR_RR_INVALID 0x00000 63 #define APIC_ICR_RR_INPROG 0x10000 64 #define APIC_ICR_RR_VALID 0x20000 65 #define APIC_INT_LEVELTRIG 0x08000 66 #define APIC_INT_ASSERT 0x04000 67 #define APIC_ICR_BUSY 0x01000 68 #define APIC_DEST_LOGICAL 0x00800 69 #define APIC_DEST_PHYSICAL 0x00000 70 #define APIC_DM_FIXED 0x00000 71 #define APIC_DM_LOWEST 0x00100 72 #define APIC_DM_SMI 0x00200 73 #define APIC_DM_REMRD 0x00300 74 #define APIC_DM_NMI 0x00400 75 #define APIC_DM_INIT 0x00500 76 #define APIC_DM_STARTUP 0x00600 77 #define APIC_DM_EXTINT 0x00700 78 #define APIC_VECTOR_MASK 0x000FF 79 #define APIC_ICR2 0x310 80 #define GET_APIC_DEST_FIELD(x) (((x) >> 24) & 0xFF) 81 #define SET_APIC_DEST_FIELD(x) ((x) << 24) 82 #define APIC_LVTT 0x320 83 #define APIC_LVTTHMR 0x330 84 #define APIC_LVTPC 0x340 85 #define APIC_LVT0 0x350 86 #define APIC_LVT_TIMER_BASE_MASK (0x3 << 18) 87 #define GET_APIC_TIMER_BASE(x) (((x) >> 18) & 0x3) 88 #define SET_APIC_TIMER_BASE(x) (((x) << 18)) 89 #define APIC_TIMER_BASE_CLKIN 0x0 90 #define APIC_TIMER_BASE_TMBASE 0x1 91 #define APIC_TIMER_BASE_DIV 0x2 92 #define APIC_LVT_TIMER_PERIODIC (1 << 17) 93 #define APIC_LVT_MASKED (1 << 16) 94 #define APIC_LVT_LEVEL_TRIGGER (1 << 15) 95 #define APIC_LVT_REMOTE_IRR (1 << 14) 96 #define APIC_INPUT_POLARITY (1 << 13) 97 #define APIC_SEND_PENDING (1 << 12) 98 #define APIC_MODE_MASK 0x700 99 #define GET_APIC_DELIVERY_MODE(x) (((x) >> 8) & 0x7) 100 #define SET_APIC_DELIVERY_MODE(x, y) (((x) & ~0x700) | ((y) << 8)) 101 #define APIC_MODE_FIXED 0x0 102 #define APIC_MODE_NMI 0x4 103 #define APIC_MODE_EXTINT 0x7 104 #define APIC_LVT1 0x360 105 #define APIC_LVTERR 0x370 106 #define APIC_TMICT 0x380 107 #define APIC_TMCCT 0x390 108 #define APIC_TDCR 0x3E0 109 #define APIC_SELF_IPI 0x3F0 110 #define APIC_TDR_DIV_TMBASE (1 << 2) 111 #define APIC_TDR_DIV_1 0xB 112 #define APIC_TDR_DIV_2 0x0 113 #define APIC_TDR_DIV_4 0x1 114 #define APIC_TDR_DIV_8 0x2 115 #define APIC_TDR_DIV_16 0x3 116 #define APIC_TDR_DIV_32 0x8 117 #define APIC_TDR_DIV_64 0x9 118 #define APIC_TDR_DIV_128 0xA 119 #define APIC_EILVT0 0x500 120 #define APIC_EILVT_NR_AMD_K8 1 /* # of extended interrupts */ 121 #define APIC_EILVT_NR_AMD_10H 4 122 #define APIC_EILVT_LVTOFF(x) (((x) >> 4) & 0xF) 123 #define APIC_EILVT_MSG_FIX 0x0 124 #define APIC_EILVT_MSG_SMI 0x2 125 #define APIC_EILVT_MSG_NMI 0x4 126 #define APIC_EILVT_MSG_EXT 0x7 127 #define APIC_EILVT_MASKED (1 << 16) 128 #define APIC_EILVT1 0x510 129 #define APIC_EILVT2 0x520 130 #define APIC_EILVT3 0x530 131 132 #define APIC_BASE (fix_to_virt(FIX_APIC_BASE)) 133 #define APIC_BASE_MSR 0x800 134 #define X2APIC_ENABLE (1UL << 10) 135 136 #ifdef CONFIG_X86_32 137 # define MAX_IO_APICS 64 138 #else 139 # define MAX_IO_APICS 128 140 # define MAX_LOCAL_APIC 32768 141 #endif 142 143 /* 144 * All x86-64 systems are xAPIC compatible. 145 * In the following, "apicid" is a physical APIC ID. 146 */ 147 #define XAPIC_DEST_CPUS_SHIFT 4 148 #define XAPIC_DEST_CPUS_MASK ((1u << XAPIC_DEST_CPUS_SHIFT) - 1) 149 #define XAPIC_DEST_CLUSTER_MASK (XAPIC_DEST_CPUS_MASK << XAPIC_DEST_CPUS_SHIFT) 150 #define APIC_CLUSTER(apicid) ((apicid) & XAPIC_DEST_CLUSTER_MASK) 151 #define APIC_CLUSTERID(apicid) (APIC_CLUSTER(apicid) >> XAPIC_DEST_CPUS_SHIFT) 152 #define APIC_CPUID(apicid) ((apicid) & XAPIC_DEST_CPUS_MASK) 153 #define NUM_APIC_CLUSTERS ((BAD_APICID + 1) >> XAPIC_DEST_CPUS_SHIFT) 154 155 /* 156 * the local APIC register structure, memory mapped. Not terribly well 157 * tested, but we might eventually use this one in the future - the 158 * problem why we cannot use it right now is the P5 APIC, it has an 159 * errata which cannot take 8-bit reads and writes, only 32-bit ones ... 160 */ 161 #define u32 unsigned int 162 163 struct local_apic { 164 165 /*000*/ struct { u32 __reserved[4]; } __reserved_01; 166 167 /*010*/ struct { u32 __reserved[4]; } __reserved_02; 168 169 /*020*/ struct { /* APIC ID Register */ 170 u32 __reserved_1 : 24, 171 phys_apic_id : 4, 172 __reserved_2 : 4; 173 u32 __reserved[3]; 174 } id; 175 176 /*030*/ const 177 struct { /* APIC Version Register */ 178 u32 version : 8, 179 __reserved_1 : 8, 180 max_lvt : 8, 181 __reserved_2 : 8; 182 u32 __reserved[3]; 183 } version; 184 185 /*040*/ struct { u32 __reserved[4]; } __reserved_03; 186 187 /*050*/ struct { u32 __reserved[4]; } __reserved_04; 188 189 /*060*/ struct { u32 __reserved[4]; } __reserved_05; 190 191 /*070*/ struct { u32 __reserved[4]; } __reserved_06; 192 193 /*080*/ struct { /* Task Priority Register */ 194 u32 priority : 8, 195 __reserved_1 : 24; 196 u32 __reserved_2[3]; 197 } tpr; 198 199 /*090*/ const 200 struct { /* Arbitration Priority Register */ 201 u32 priority : 8, 202 __reserved_1 : 24; 203 u32 __reserved_2[3]; 204 } apr; 205 206 /*0A0*/ const 207 struct { /* Processor Priority Register */ 208 u32 priority : 8, 209 __reserved_1 : 24; 210 u32 __reserved_2[3]; 211 } ppr; 212 213 /*0B0*/ struct { /* End Of Interrupt Register */ 214 u32 eoi; 215 u32 __reserved[3]; 216 } eoi; 217 218 /*0C0*/ struct { u32 __reserved[4]; } __reserved_07; 219 220 /*0D0*/ struct { /* Logical Destination Register */ 221 u32 __reserved_1 : 24, 222 logical_dest : 8; 223 u32 __reserved_2[3]; 224 } ldr; 225 226 /*0E0*/ struct { /* Destination Format Register */ 227 u32 __reserved_1 : 28, 228 model : 4; 229 u32 __reserved_2[3]; 230 } dfr; 231 232 /*0F0*/ struct { /* Spurious Interrupt Vector Register */ 233 u32 spurious_vector : 8, 234 apic_enabled : 1, 235 focus_cpu : 1, 236 __reserved_2 : 22; 237 u32 __reserved_3[3]; 238 } svr; 239 240 /*100*/ struct { /* In Service Register */ 241 /*170*/ u32 bitfield; 242 u32 __reserved[3]; 243 } isr [8]; 244 245 /*180*/ struct { /* Trigger Mode Register */ 246 /*1F0*/ u32 bitfield; 247 u32 __reserved[3]; 248 } tmr [8]; 249 250 /*200*/ struct { /* Interrupt Request Register */ 251 /*270*/ u32 bitfield; 252 u32 __reserved[3]; 253 } irr [8]; 254 255 /*280*/ union { /* Error Status Register */ 256 struct { 257 u32 send_cs_error : 1, 258 receive_cs_error : 1, 259 send_accept_error : 1, 260 receive_accept_error : 1, 261 __reserved_1 : 1, 262 send_illegal_vector : 1, 263 receive_illegal_vector : 1, 264 illegal_register_address : 1, 265 __reserved_2 : 24; 266 u32 __reserved_3[3]; 267 } error_bits; 268 struct { 269 u32 errors; 270 u32 __reserved_3[3]; 271 } all_errors; 272 } esr; 273 274 /*290*/ struct { u32 __reserved[4]; } __reserved_08; 275 276 /*2A0*/ struct { u32 __reserved[4]; } __reserved_09; 277 278 /*2B0*/ struct { u32 __reserved[4]; } __reserved_10; 279 280 /*2C0*/ struct { u32 __reserved[4]; } __reserved_11; 281 282 /*2D0*/ struct { u32 __reserved[4]; } __reserved_12; 283 284 /*2E0*/ struct { u32 __reserved[4]; } __reserved_13; 285 286 /*2F0*/ struct { u32 __reserved[4]; } __reserved_14; 287 288 /*300*/ struct { /* Interrupt Command Register 1 */ 289 u32 vector : 8, 290 delivery_mode : 3, 291 destination_mode : 1, 292 delivery_status : 1, 293 __reserved_1 : 1, 294 level : 1, 295 trigger : 1, 296 __reserved_2 : 2, 297 shorthand : 2, 298 __reserved_3 : 12; 299 u32 __reserved_4[3]; 300 } icr1; 301 302 /*310*/ struct { /* Interrupt Command Register 2 */ 303 union { 304 u32 __reserved_1 : 24, 305 phys_dest : 4, 306 __reserved_2 : 4; 307 u32 __reserved_3 : 24, 308 logical_dest : 8; 309 } dest; 310 u32 __reserved_4[3]; 311 } icr2; 312 313 /*320*/ struct { /* LVT - Timer */ 314 u32 vector : 8, 315 __reserved_1 : 4, 316 delivery_status : 1, 317 __reserved_2 : 3, 318 mask : 1, 319 timer_mode : 1, 320 __reserved_3 : 14; 321 u32 __reserved_4[3]; 322 } lvt_timer; 323 324 /*330*/ struct { /* LVT - Thermal Sensor */ 325 u32 vector : 8, 326 delivery_mode : 3, 327 __reserved_1 : 1, 328 delivery_status : 1, 329 __reserved_2 : 3, 330 mask : 1, 331 __reserved_3 : 15; 332 u32 __reserved_4[3]; 333 } lvt_thermal; 334 335 /*340*/ struct { /* LVT - Performance Counter */ 336 u32 vector : 8, 337 delivery_mode : 3, 338 __reserved_1 : 1, 339 delivery_status : 1, 340 __reserved_2 : 3, 341 mask : 1, 342 __reserved_3 : 15; 343 u32 __reserved_4[3]; 344 } lvt_pc; 345 346 /*350*/ struct { /* LVT - LINT0 */ 347 u32 vector : 8, 348 delivery_mode : 3, 349 __reserved_1 : 1, 350 delivery_status : 1, 351 polarity : 1, 352 remote_irr : 1, 353 trigger : 1, 354 mask : 1, 355 __reserved_2 : 15; 356 u32 __reserved_3[3]; 357 } lvt_lint0; 358 359 /*360*/ struct { /* LVT - LINT1 */ 360 u32 vector : 8, 361 delivery_mode : 3, 362 __reserved_1 : 1, 363 delivery_status : 1, 364 polarity : 1, 365 remote_irr : 1, 366 trigger : 1, 367 mask : 1, 368 __reserved_2 : 15; 369 u32 __reserved_3[3]; 370 } lvt_lint1; 371 372 /*370*/ struct { /* LVT - Error */ 373 u32 vector : 8, 374 __reserved_1 : 4, 375 delivery_status : 1, 376 __reserved_2 : 3, 377 mask : 1, 378 __reserved_3 : 15; 379 u32 __reserved_4[3]; 380 } lvt_error; 381 382 /*380*/ struct { /* Timer Initial Count Register */ 383 u32 initial_count; 384 u32 __reserved_2[3]; 385 } timer_icr; 386 387 /*390*/ const 388 struct { /* Timer Current Count Register */ 389 u32 curr_count; 390 u32 __reserved_2[3]; 391 } timer_ccr; 392 393 /*3A0*/ struct { u32 __reserved[4]; } __reserved_16; 394 395 /*3B0*/ struct { u32 __reserved[4]; } __reserved_17; 396 397 /*3C0*/ struct { u32 __reserved[4]; } __reserved_18; 398 399 /*3D0*/ struct { u32 __reserved[4]; } __reserved_19; 400 401 /*3E0*/ struct { /* Timer Divide Configuration Register */ 402 u32 divisor : 4, 403 __reserved_1 : 28; 404 u32 __reserved_2[3]; 405 } timer_dcr; 406 407 /*3F0*/ struct { u32 __reserved[4]; } __reserved_20; 408 409 } __attribute__ ((packed)); 410 411 #undef u32 412 413 #ifdef CONFIG_X86_32 414 #define BAD_APICID 0xFFu 415 #else 416 #define BAD_APICID 0xFFFFu 417 #endif 418 #endif /* _ASM_X86_APICDEF_H */ 419