1 #ifndef _ASM_X86_APICDEF_H 2 #define _ASM_X86_APICDEF_H 3 4 /* 5 * Constants for various Intel APICs. (local APIC, IOAPIC, etc.) 6 * 7 * Alan Cox <Alan.Cox@linux.org>, 1995. 8 * Ingo Molnar <mingo@redhat.com>, 1999, 2000 9 */ 10 11 #define IO_APIC_DEFAULT_PHYS_BASE 0xfec00000 12 #define APIC_DEFAULT_PHYS_BASE 0xfee00000 13 14 /* 15 * This is the IO-APIC register space as specified 16 * by Intel docs: 17 */ 18 #define IO_APIC_SLOT_SIZE 1024 19 20 #define APIC_ID 0x20 21 22 #define APIC_LVR 0x30 23 #define APIC_LVR_MASK 0xFF00FF 24 #define APIC_LVR_DIRECTED_EOI (1 << 24) 25 #define GET_APIC_VERSION(x) ((x) & 0xFFu) 26 #define GET_APIC_MAXLVT(x) (((x) >> 16) & 0xFFu) 27 #ifdef CONFIG_X86_32 28 # define APIC_INTEGRATED(x) ((x) & 0xF0u) 29 #else 30 # define APIC_INTEGRATED(x) (1) 31 #endif 32 #define APIC_XAPIC(x) ((x) >= 0x14) 33 #define APIC_EXT_SPACE(x) ((x) & 0x80000000) 34 #define APIC_TASKPRI 0x80 35 #define APIC_TPRI_MASK 0xFFu 36 #define APIC_ARBPRI 0x90 37 #define APIC_ARBPRI_MASK 0xFFu 38 #define APIC_PROCPRI 0xA0 39 #define APIC_EOI 0xB0 40 #define APIC_EIO_ACK 0x0 41 #define APIC_RRR 0xC0 42 #define APIC_LDR 0xD0 43 #define APIC_LDR_MASK (0xFFu << 24) 44 #define GET_APIC_LOGICAL_ID(x) (((x) >> 24) & 0xFFu) 45 #define SET_APIC_LOGICAL_ID(x) (((x) << 24)) 46 #define APIC_ALL_CPUS 0xFFu 47 #define APIC_DFR 0xE0 48 #define APIC_DFR_CLUSTER 0x0FFFFFFFul 49 #define APIC_DFR_FLAT 0xFFFFFFFFul 50 #define APIC_SPIV 0xF0 51 #define APIC_SPIV_DIRECTED_EOI (1 << 12) 52 #define APIC_SPIV_FOCUS_DISABLED (1 << 9) 53 #define APIC_SPIV_APIC_ENABLED (1 << 8) 54 #define APIC_ISR 0x100 55 #define APIC_ISR_NR 0x8 /* Number of 32 bit ISR registers. */ 56 #define APIC_TMR 0x180 57 #define APIC_IRR 0x200 58 #define APIC_ESR 0x280 59 #define APIC_ESR_SEND_CS 0x00001 60 #define APIC_ESR_RECV_CS 0x00002 61 #define APIC_ESR_SEND_ACC 0x00004 62 #define APIC_ESR_RECV_ACC 0x00008 63 #define APIC_ESR_SENDILL 0x00020 64 #define APIC_ESR_RECVILL 0x00040 65 #define APIC_ESR_ILLREGA 0x00080 66 #define APIC_LVTCMCI 0x2f0 67 #define APIC_ICR 0x300 68 #define APIC_DEST_SELF 0x40000 69 #define APIC_DEST_ALLINC 0x80000 70 #define APIC_DEST_ALLBUT 0xC0000 71 #define APIC_ICR_RR_MASK 0x30000 72 #define APIC_ICR_RR_INVALID 0x00000 73 #define APIC_ICR_RR_INPROG 0x10000 74 #define APIC_ICR_RR_VALID 0x20000 75 #define APIC_INT_LEVELTRIG 0x08000 76 #define APIC_INT_ASSERT 0x04000 77 #define APIC_ICR_BUSY 0x01000 78 #define APIC_DEST_LOGICAL 0x00800 79 #define APIC_DEST_PHYSICAL 0x00000 80 #define APIC_DM_FIXED 0x00000 81 #define APIC_DM_LOWEST 0x00100 82 #define APIC_DM_SMI 0x00200 83 #define APIC_DM_REMRD 0x00300 84 #define APIC_DM_NMI 0x00400 85 #define APIC_DM_INIT 0x00500 86 #define APIC_DM_STARTUP 0x00600 87 #define APIC_DM_EXTINT 0x00700 88 #define APIC_VECTOR_MASK 0x000FF 89 #define APIC_ICR2 0x310 90 #define GET_APIC_DEST_FIELD(x) (((x) >> 24) & 0xFF) 91 #define SET_APIC_DEST_FIELD(x) ((x) << 24) 92 #define APIC_LVTT 0x320 93 #define APIC_LVTTHMR 0x330 94 #define APIC_LVTPC 0x340 95 #define APIC_LVT0 0x350 96 #define APIC_LVT_TIMER_BASE_MASK (0x3 << 18) 97 #define GET_APIC_TIMER_BASE(x) (((x) >> 18) & 0x3) 98 #define SET_APIC_TIMER_BASE(x) (((x) << 18)) 99 #define APIC_TIMER_BASE_CLKIN 0x0 100 #define APIC_TIMER_BASE_TMBASE 0x1 101 #define APIC_TIMER_BASE_DIV 0x2 102 #define APIC_LVT_TIMER_PERIODIC (1 << 17) 103 #define APIC_LVT_MASKED (1 << 16) 104 #define APIC_LVT_LEVEL_TRIGGER (1 << 15) 105 #define APIC_LVT_REMOTE_IRR (1 << 14) 106 #define APIC_INPUT_POLARITY (1 << 13) 107 #define APIC_SEND_PENDING (1 << 12) 108 #define APIC_MODE_MASK 0x700 109 #define GET_APIC_DELIVERY_MODE(x) (((x) >> 8) & 0x7) 110 #define SET_APIC_DELIVERY_MODE(x, y) (((x) & ~0x700) | ((y) << 8)) 111 #define APIC_MODE_FIXED 0x0 112 #define APIC_MODE_NMI 0x4 113 #define APIC_MODE_EXTINT 0x7 114 #define APIC_LVT1 0x360 115 #define APIC_LVTERR 0x370 116 #define APIC_TMICT 0x380 117 #define APIC_TMCCT 0x390 118 #define APIC_TDCR 0x3E0 119 #define APIC_SELF_IPI 0x3F0 120 #define APIC_TDR_DIV_TMBASE (1 << 2) 121 #define APIC_TDR_DIV_1 0xB 122 #define APIC_TDR_DIV_2 0x0 123 #define APIC_TDR_DIV_4 0x1 124 #define APIC_TDR_DIV_8 0x2 125 #define APIC_TDR_DIV_16 0x3 126 #define APIC_TDR_DIV_32 0x8 127 #define APIC_TDR_DIV_64 0x9 128 #define APIC_TDR_DIV_128 0xA 129 #define APIC_EFEAT 0x400 130 #define APIC_ECTRL 0x410 131 #define APIC_EILVTn(n) (0x500 + 0x10 * n) 132 #define APIC_EILVT_NR_AMD_K8 1 /* # of extended interrupts */ 133 #define APIC_EILVT_NR_AMD_10H 4 134 #define APIC_EILVT_LVTOFF(x) (((x) >> 4) & 0xF) 135 #define APIC_EILVT_MSG_FIX 0x0 136 #define APIC_EILVT_MSG_SMI 0x2 137 #define APIC_EILVT_MSG_NMI 0x4 138 #define APIC_EILVT_MSG_EXT 0x7 139 #define APIC_EILVT_MASKED (1 << 16) 140 141 #define APIC_BASE (fix_to_virt(FIX_APIC_BASE)) 142 #define APIC_BASE_MSR 0x800 143 #define X2APIC_ENABLE (1UL << 10) 144 145 #ifdef CONFIG_X86_32 146 # define MAX_IO_APICS 64 147 #else 148 # define MAX_IO_APICS 128 149 # define MAX_LOCAL_APIC 32768 150 #endif 151 152 /* 153 * All x86-64 systems are xAPIC compatible. 154 * In the following, "apicid" is a physical APIC ID. 155 */ 156 #define XAPIC_DEST_CPUS_SHIFT 4 157 #define XAPIC_DEST_CPUS_MASK ((1u << XAPIC_DEST_CPUS_SHIFT) - 1) 158 #define XAPIC_DEST_CLUSTER_MASK (XAPIC_DEST_CPUS_MASK << XAPIC_DEST_CPUS_SHIFT) 159 #define APIC_CLUSTER(apicid) ((apicid) & XAPIC_DEST_CLUSTER_MASK) 160 #define APIC_CLUSTERID(apicid) (APIC_CLUSTER(apicid) >> XAPIC_DEST_CPUS_SHIFT) 161 #define APIC_CPUID(apicid) ((apicid) & XAPIC_DEST_CPUS_MASK) 162 #define NUM_APIC_CLUSTERS ((BAD_APICID + 1) >> XAPIC_DEST_CPUS_SHIFT) 163 164 /* 165 * the local APIC register structure, memory mapped. Not terribly well 166 * tested, but we might eventually use this one in the future - the 167 * problem why we cannot use it right now is the P5 APIC, it has an 168 * errata which cannot take 8-bit reads and writes, only 32-bit ones ... 169 */ 170 #define u32 unsigned int 171 172 struct local_apic { 173 174 /*000*/ struct { u32 __reserved[4]; } __reserved_01; 175 176 /*010*/ struct { u32 __reserved[4]; } __reserved_02; 177 178 /*020*/ struct { /* APIC ID Register */ 179 u32 __reserved_1 : 24, 180 phys_apic_id : 4, 181 __reserved_2 : 4; 182 u32 __reserved[3]; 183 } id; 184 185 /*030*/ const 186 struct { /* APIC Version Register */ 187 u32 version : 8, 188 __reserved_1 : 8, 189 max_lvt : 8, 190 __reserved_2 : 8; 191 u32 __reserved[3]; 192 } version; 193 194 /*040*/ struct { u32 __reserved[4]; } __reserved_03; 195 196 /*050*/ struct { u32 __reserved[4]; } __reserved_04; 197 198 /*060*/ struct { u32 __reserved[4]; } __reserved_05; 199 200 /*070*/ struct { u32 __reserved[4]; } __reserved_06; 201 202 /*080*/ struct { /* Task Priority Register */ 203 u32 priority : 8, 204 __reserved_1 : 24; 205 u32 __reserved_2[3]; 206 } tpr; 207 208 /*090*/ const 209 struct { /* Arbitration Priority Register */ 210 u32 priority : 8, 211 __reserved_1 : 24; 212 u32 __reserved_2[3]; 213 } apr; 214 215 /*0A0*/ const 216 struct { /* Processor Priority Register */ 217 u32 priority : 8, 218 __reserved_1 : 24; 219 u32 __reserved_2[3]; 220 } ppr; 221 222 /*0B0*/ struct { /* End Of Interrupt Register */ 223 u32 eoi; 224 u32 __reserved[3]; 225 } eoi; 226 227 /*0C0*/ struct { u32 __reserved[4]; } __reserved_07; 228 229 /*0D0*/ struct { /* Logical Destination Register */ 230 u32 __reserved_1 : 24, 231 logical_dest : 8; 232 u32 __reserved_2[3]; 233 } ldr; 234 235 /*0E0*/ struct { /* Destination Format Register */ 236 u32 __reserved_1 : 28, 237 model : 4; 238 u32 __reserved_2[3]; 239 } dfr; 240 241 /*0F0*/ struct { /* Spurious Interrupt Vector Register */ 242 u32 spurious_vector : 8, 243 apic_enabled : 1, 244 focus_cpu : 1, 245 __reserved_2 : 22; 246 u32 __reserved_3[3]; 247 } svr; 248 249 /*100*/ struct { /* In Service Register */ 250 /*170*/ u32 bitfield; 251 u32 __reserved[3]; 252 } isr [8]; 253 254 /*180*/ struct { /* Trigger Mode Register */ 255 /*1F0*/ u32 bitfield; 256 u32 __reserved[3]; 257 } tmr [8]; 258 259 /*200*/ struct { /* Interrupt Request Register */ 260 /*270*/ u32 bitfield; 261 u32 __reserved[3]; 262 } irr [8]; 263 264 /*280*/ union { /* Error Status Register */ 265 struct { 266 u32 send_cs_error : 1, 267 receive_cs_error : 1, 268 send_accept_error : 1, 269 receive_accept_error : 1, 270 __reserved_1 : 1, 271 send_illegal_vector : 1, 272 receive_illegal_vector : 1, 273 illegal_register_address : 1, 274 __reserved_2 : 24; 275 u32 __reserved_3[3]; 276 } error_bits; 277 struct { 278 u32 errors; 279 u32 __reserved_3[3]; 280 } all_errors; 281 } esr; 282 283 /*290*/ struct { u32 __reserved[4]; } __reserved_08; 284 285 /*2A0*/ struct { u32 __reserved[4]; } __reserved_09; 286 287 /*2B0*/ struct { u32 __reserved[4]; } __reserved_10; 288 289 /*2C0*/ struct { u32 __reserved[4]; } __reserved_11; 290 291 /*2D0*/ struct { u32 __reserved[4]; } __reserved_12; 292 293 /*2E0*/ struct { u32 __reserved[4]; } __reserved_13; 294 295 /*2F0*/ struct { u32 __reserved[4]; } __reserved_14; 296 297 /*300*/ struct { /* Interrupt Command Register 1 */ 298 u32 vector : 8, 299 delivery_mode : 3, 300 destination_mode : 1, 301 delivery_status : 1, 302 __reserved_1 : 1, 303 level : 1, 304 trigger : 1, 305 __reserved_2 : 2, 306 shorthand : 2, 307 __reserved_3 : 12; 308 u32 __reserved_4[3]; 309 } icr1; 310 311 /*310*/ struct { /* Interrupt Command Register 2 */ 312 union { 313 u32 __reserved_1 : 24, 314 phys_dest : 4, 315 __reserved_2 : 4; 316 u32 __reserved_3 : 24, 317 logical_dest : 8; 318 } dest; 319 u32 __reserved_4[3]; 320 } icr2; 321 322 /*320*/ struct { /* LVT - Timer */ 323 u32 vector : 8, 324 __reserved_1 : 4, 325 delivery_status : 1, 326 __reserved_2 : 3, 327 mask : 1, 328 timer_mode : 1, 329 __reserved_3 : 14; 330 u32 __reserved_4[3]; 331 } lvt_timer; 332 333 /*330*/ struct { /* LVT - Thermal Sensor */ 334 u32 vector : 8, 335 delivery_mode : 3, 336 __reserved_1 : 1, 337 delivery_status : 1, 338 __reserved_2 : 3, 339 mask : 1, 340 __reserved_3 : 15; 341 u32 __reserved_4[3]; 342 } lvt_thermal; 343 344 /*340*/ struct { /* LVT - Performance Counter */ 345 u32 vector : 8, 346 delivery_mode : 3, 347 __reserved_1 : 1, 348 delivery_status : 1, 349 __reserved_2 : 3, 350 mask : 1, 351 __reserved_3 : 15; 352 u32 __reserved_4[3]; 353 } lvt_pc; 354 355 /*350*/ struct { /* LVT - LINT0 */ 356 u32 vector : 8, 357 delivery_mode : 3, 358 __reserved_1 : 1, 359 delivery_status : 1, 360 polarity : 1, 361 remote_irr : 1, 362 trigger : 1, 363 mask : 1, 364 __reserved_2 : 15; 365 u32 __reserved_3[3]; 366 } lvt_lint0; 367 368 /*360*/ struct { /* LVT - LINT1 */ 369 u32 vector : 8, 370 delivery_mode : 3, 371 __reserved_1 : 1, 372 delivery_status : 1, 373 polarity : 1, 374 remote_irr : 1, 375 trigger : 1, 376 mask : 1, 377 __reserved_2 : 15; 378 u32 __reserved_3[3]; 379 } lvt_lint1; 380 381 /*370*/ struct { /* LVT - Error */ 382 u32 vector : 8, 383 __reserved_1 : 4, 384 delivery_status : 1, 385 __reserved_2 : 3, 386 mask : 1, 387 __reserved_3 : 15; 388 u32 __reserved_4[3]; 389 } lvt_error; 390 391 /*380*/ struct { /* Timer Initial Count Register */ 392 u32 initial_count; 393 u32 __reserved_2[3]; 394 } timer_icr; 395 396 /*390*/ const 397 struct { /* Timer Current Count Register */ 398 u32 curr_count; 399 u32 __reserved_2[3]; 400 } timer_ccr; 401 402 /*3A0*/ struct { u32 __reserved[4]; } __reserved_16; 403 404 /*3B0*/ struct { u32 __reserved[4]; } __reserved_17; 405 406 /*3C0*/ struct { u32 __reserved[4]; } __reserved_18; 407 408 /*3D0*/ struct { u32 __reserved[4]; } __reserved_19; 409 410 /*3E0*/ struct { /* Timer Divide Configuration Register */ 411 u32 divisor : 4, 412 __reserved_1 : 28; 413 u32 __reserved_2[3]; 414 } timer_dcr; 415 416 /*3F0*/ struct { u32 __reserved[4]; } __reserved_20; 417 418 } __attribute__ ((packed)); 419 420 #undef u32 421 422 #ifdef CONFIG_X86_32 423 #define BAD_APICID 0xFFu 424 #else 425 #define BAD_APICID 0xFFFFu 426 #endif 427 #endif /* _ASM_X86_APICDEF_H */ 428