1 #ifndef _ASM_X86_APIC_H 2 #define _ASM_X86_APIC_H 3 4 #include <linux/cpumask.h> 5 #include <linux/delay.h> 6 #include <linux/pm.h> 7 8 #include <asm/alternative.h> 9 #include <asm/cpufeature.h> 10 #include <asm/processor.h> 11 #include <asm/apicdef.h> 12 #include <asm/atomic.h> 13 #include <asm/fixmap.h> 14 #include <asm/mpspec.h> 15 #include <asm/system.h> 16 #include <asm/msr.h> 17 18 #define ARCH_APICTIMER_STOPS_ON_C3 1 19 20 /* 21 * Debugging macros 22 */ 23 #define APIC_QUIET 0 24 #define APIC_VERBOSE 1 25 #define APIC_DEBUG 2 26 27 /* 28 * Define the default level of output to be very little 29 * This can be turned up by using apic=verbose for more 30 * information and apic=debug for _lots_ of information. 31 * apic_verbosity is defined in apic.c 32 */ 33 #define apic_printk(v, s, a...) do { \ 34 if ((v) <= apic_verbosity) \ 35 printk(s, ##a); \ 36 } while (0) 37 38 39 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32) 40 extern void generic_apic_probe(void); 41 #else 42 static inline void generic_apic_probe(void) 43 { 44 } 45 #endif 46 47 #ifdef CONFIG_X86_LOCAL_APIC 48 49 extern unsigned int apic_verbosity; 50 extern int local_apic_timer_c2_ok; 51 52 extern int disable_apic; 53 54 #ifdef CONFIG_SMP 55 extern void __inquire_remote_apic(int apicid); 56 #else /* CONFIG_SMP */ 57 static inline void __inquire_remote_apic(int apicid) 58 { 59 } 60 #endif /* CONFIG_SMP */ 61 62 static inline void default_inquire_remote_apic(int apicid) 63 { 64 if (apic_verbosity >= APIC_DEBUG) 65 __inquire_remote_apic(apicid); 66 } 67 68 /* 69 * Basic functions accessing APICs. 70 */ 71 #ifdef CONFIG_PARAVIRT 72 #include <asm/paravirt.h> 73 #endif 74 75 #ifdef CONFIG_X86_64 76 extern int is_vsmp_box(void); 77 #else 78 static inline int is_vsmp_box(void) 79 { 80 return 0; 81 } 82 #endif 83 extern void xapic_wait_icr_idle(void); 84 extern u32 safe_xapic_wait_icr_idle(void); 85 extern void xapic_icr_write(u32, u32); 86 extern int setup_profiling_timer(unsigned int); 87 88 static inline void native_apic_mem_write(u32 reg, u32 v) 89 { 90 volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg); 91 92 alternative_io("movl %0, %1", "xchgl %0, %1", X86_FEATURE_11AP, 93 ASM_OUTPUT2("=r" (v), "=m" (*addr)), 94 ASM_OUTPUT2("0" (v), "m" (*addr))); 95 } 96 97 static inline u32 native_apic_mem_read(u32 reg) 98 { 99 return *((volatile u32 *)(APIC_BASE + reg)); 100 } 101 102 extern void native_apic_wait_icr_idle(void); 103 extern u32 native_safe_apic_wait_icr_idle(void); 104 extern void native_apic_icr_write(u32 low, u32 id); 105 extern u64 native_apic_icr_read(void); 106 107 extern int x2apic_mode; 108 109 #ifdef CONFIG_X86_X2APIC 110 /* 111 * Make previous memory operations globally visible before 112 * sending the IPI through x2apic wrmsr. We need a serializing instruction or 113 * mfence for this. 114 */ 115 static inline void x2apic_wrmsr_fence(void) 116 { 117 asm volatile("mfence" : : : "memory"); 118 } 119 120 static inline void native_apic_msr_write(u32 reg, u32 v) 121 { 122 if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR || 123 reg == APIC_LVR) 124 return; 125 126 wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0); 127 } 128 129 static inline u32 native_apic_msr_read(u32 reg) 130 { 131 u32 low, high; 132 133 if (reg == APIC_DFR) 134 return -1; 135 136 rdmsr(APIC_BASE_MSR + (reg >> 4), low, high); 137 return low; 138 } 139 140 static inline void native_x2apic_wait_icr_idle(void) 141 { 142 /* no need to wait for icr idle in x2apic */ 143 return; 144 } 145 146 static inline u32 native_safe_x2apic_wait_icr_idle(void) 147 { 148 /* no need to wait for icr idle in x2apic */ 149 return 0; 150 } 151 152 static inline void native_x2apic_icr_write(u32 low, u32 id) 153 { 154 wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low); 155 } 156 157 static inline u64 native_x2apic_icr_read(void) 158 { 159 unsigned long val; 160 161 rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val); 162 return val; 163 } 164 165 extern int x2apic_phys; 166 extern void check_x2apic(void); 167 extern void enable_x2apic(void); 168 extern void x2apic_icr_write(u32 low, u32 id); 169 static inline int x2apic_enabled(void) 170 { 171 int msr, msr2; 172 173 if (!cpu_has_x2apic) 174 return 0; 175 176 rdmsr(MSR_IA32_APICBASE, msr, msr2); 177 if (msr & X2APIC_ENABLE) 178 return 1; 179 return 0; 180 } 181 182 #define x2apic_supported() (cpu_has_x2apic) 183 static inline void x2apic_force_phys(void) 184 { 185 x2apic_phys = 1; 186 } 187 #else 188 static inline void check_x2apic(void) 189 { 190 } 191 static inline void enable_x2apic(void) 192 { 193 } 194 static inline int x2apic_enabled(void) 195 { 196 return 0; 197 } 198 static inline void x2apic_force_phys(void) 199 { 200 } 201 202 #define x2apic_preenabled 0 203 #define x2apic_supported() 0 204 #endif 205 206 extern void enable_IR_x2apic(void); 207 208 extern int get_physical_broadcast(void); 209 210 extern void apic_disable(void); 211 extern int lapic_get_maxlvt(void); 212 extern void clear_local_APIC(void); 213 extern void connect_bsp_APIC(void); 214 extern void disconnect_bsp_APIC(int virt_wire_setup); 215 extern void disable_local_APIC(void); 216 extern void lapic_shutdown(void); 217 extern int verify_local_APIC(void); 218 extern void cache_APIC_registers(void); 219 extern void sync_Arb_IDs(void); 220 extern void init_bsp_APIC(void); 221 extern void setup_local_APIC(void); 222 extern void end_local_APIC_setup(void); 223 extern void init_apic_mappings(void); 224 extern void setup_boot_APIC_clock(void); 225 extern void setup_secondary_APIC_clock(void); 226 extern int APIC_init_uniprocessor(void); 227 extern void enable_NMI_through_LVT0(void); 228 229 /* 230 * On 32bit this is mach-xxx local 231 */ 232 #ifdef CONFIG_X86_64 233 extern void early_init_lapic_mapping(void); 234 extern int apic_is_clustered_box(void); 235 #else 236 static inline int apic_is_clustered_box(void) 237 { 238 return 0; 239 } 240 #endif 241 242 extern u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask); 243 extern u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask); 244 245 246 #else /* !CONFIG_X86_LOCAL_APIC */ 247 static inline void lapic_shutdown(void) { } 248 #define local_apic_timer_c2_ok 1 249 static inline void init_apic_mappings(void) { } 250 static inline void disable_local_APIC(void) { } 251 static inline void apic_disable(void) { } 252 # define setup_boot_APIC_clock x86_init_noop 253 # define setup_secondary_APIC_clock x86_init_noop 254 #endif /* !CONFIG_X86_LOCAL_APIC */ 255 256 #ifdef CONFIG_X86_64 257 #define SET_APIC_ID(x) (apic->set_apic_id(x)) 258 #else 259 260 #endif 261 262 /* 263 * Copyright 2004 James Cleverdon, IBM. 264 * Subject to the GNU Public License, v.2 265 * 266 * Generic APIC sub-arch data struct. 267 * 268 * Hacked for x86-64 by James Cleverdon from i386 architecture code by 269 * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and 270 * James Cleverdon. 271 */ 272 struct apic { 273 char *name; 274 275 int (*probe)(void); 276 int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id); 277 int (*apic_id_registered)(void); 278 279 u32 irq_delivery_mode; 280 u32 irq_dest_mode; 281 282 const struct cpumask *(*target_cpus)(void); 283 284 int disable_esr; 285 286 int dest_logical; 287 unsigned long (*check_apicid_used)(physid_mask_t bitmap, int apicid); 288 unsigned long (*check_apicid_present)(int apicid); 289 290 void (*vector_allocation_domain)(int cpu, struct cpumask *retmask); 291 void (*init_apic_ldr)(void); 292 293 physid_mask_t (*ioapic_phys_id_map)(physid_mask_t map); 294 295 void (*setup_apic_routing)(void); 296 int (*multi_timer_check)(int apic, int irq); 297 int (*apicid_to_node)(int logical_apicid); 298 int (*cpu_to_logical_apicid)(int cpu); 299 int (*cpu_present_to_apicid)(int mps_cpu); 300 physid_mask_t (*apicid_to_cpu_present)(int phys_apicid); 301 void (*setup_portio_remap)(void); 302 int (*check_phys_apicid_present)(int phys_apicid); 303 void (*enable_apic_mode)(void); 304 int (*phys_pkg_id)(int cpuid_apic, int index_msb); 305 306 /* 307 * When one of the next two hooks returns 1 the apic 308 * is switched to this. Essentially they are additional 309 * probe functions: 310 */ 311 int (*mps_oem_check)(struct mpc_table *mpc, char *oem, char *productid); 312 313 unsigned int (*get_apic_id)(unsigned long x); 314 unsigned long (*set_apic_id)(unsigned int id); 315 unsigned long apic_id_mask; 316 317 unsigned int (*cpu_mask_to_apicid)(const struct cpumask *cpumask); 318 unsigned int (*cpu_mask_to_apicid_and)(const struct cpumask *cpumask, 319 const struct cpumask *andmask); 320 321 /* ipi */ 322 void (*send_IPI_mask)(const struct cpumask *mask, int vector); 323 void (*send_IPI_mask_allbutself)(const struct cpumask *mask, 324 int vector); 325 void (*send_IPI_allbutself)(int vector); 326 void (*send_IPI_all)(int vector); 327 void (*send_IPI_self)(int vector); 328 329 /* wakeup_secondary_cpu */ 330 int (*wakeup_secondary_cpu)(int apicid, unsigned long start_eip); 331 332 int trampoline_phys_low; 333 int trampoline_phys_high; 334 335 void (*wait_for_init_deassert)(atomic_t *deassert); 336 void (*smp_callin_clear_local_apic)(void); 337 void (*inquire_remote_apic)(int apicid); 338 339 /* apic ops */ 340 u32 (*read)(u32 reg); 341 void (*write)(u32 reg, u32 v); 342 u64 (*icr_read)(void); 343 void (*icr_write)(u32 low, u32 high); 344 void (*wait_icr_idle)(void); 345 u32 (*safe_wait_icr_idle)(void); 346 }; 347 348 /* 349 * Pointer to the local APIC driver in use on this system (there's 350 * always just one such driver in use - the kernel decides via an 351 * early probing process which one it picks - and then sticks to it): 352 */ 353 extern struct apic *apic; 354 355 /* 356 * APIC functionality to boot other CPUs - only used on SMP: 357 */ 358 #ifdef CONFIG_SMP 359 extern atomic_t init_deasserted; 360 extern int wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip); 361 #endif 362 363 static inline u32 apic_read(u32 reg) 364 { 365 return apic->read(reg); 366 } 367 368 static inline void apic_write(u32 reg, u32 val) 369 { 370 apic->write(reg, val); 371 } 372 373 static inline u64 apic_icr_read(void) 374 { 375 return apic->icr_read(); 376 } 377 378 static inline void apic_icr_write(u32 low, u32 high) 379 { 380 apic->icr_write(low, high); 381 } 382 383 static inline void apic_wait_icr_idle(void) 384 { 385 apic->wait_icr_idle(); 386 } 387 388 static inline u32 safe_apic_wait_icr_idle(void) 389 { 390 return apic->safe_wait_icr_idle(); 391 } 392 393 394 static inline void ack_APIC_irq(void) 395 { 396 #ifdef CONFIG_X86_LOCAL_APIC 397 /* 398 * ack_APIC_irq() actually gets compiled as a single instruction 399 * ... yummie. 400 */ 401 402 /* Docs say use 0 for future compatibility */ 403 apic_write(APIC_EOI, 0); 404 #endif 405 } 406 407 static inline unsigned default_get_apic_id(unsigned long x) 408 { 409 unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR)); 410 411 if (APIC_XAPIC(ver) || boot_cpu_has(X86_FEATURE_EXTD_APICID)) 412 return (x >> 24) & 0xFF; 413 else 414 return (x >> 24) & 0x0F; 415 } 416 417 /* 418 * Warm reset vector default position: 419 */ 420 #define DEFAULT_TRAMPOLINE_PHYS_LOW 0x467 421 #define DEFAULT_TRAMPOLINE_PHYS_HIGH 0x469 422 423 #ifdef CONFIG_X86_64 424 extern struct apic apic_flat; 425 extern struct apic apic_physflat; 426 extern struct apic apic_x2apic_cluster; 427 extern struct apic apic_x2apic_phys; 428 extern int default_acpi_madt_oem_check(char *, char *); 429 430 extern void apic_send_IPI_self(int vector); 431 432 extern struct apic apic_x2apic_uv_x; 433 DECLARE_PER_CPU(int, x2apic_extra_bits); 434 435 extern int default_cpu_present_to_apicid(int mps_cpu); 436 extern int default_check_phys_apicid_present(int phys_apicid); 437 #endif 438 439 static inline void default_wait_for_init_deassert(atomic_t *deassert) 440 { 441 while (!atomic_read(deassert)) 442 cpu_relax(); 443 return; 444 } 445 446 extern void generic_bigsmp_probe(void); 447 448 449 #ifdef CONFIG_X86_LOCAL_APIC 450 451 #include <asm/smp.h> 452 453 #define APIC_DFR_VALUE (APIC_DFR_FLAT) 454 455 static inline const struct cpumask *default_target_cpus(void) 456 { 457 #ifdef CONFIG_SMP 458 return cpu_online_mask; 459 #else 460 return cpumask_of(0); 461 #endif 462 } 463 464 DECLARE_EARLY_PER_CPU(u16, x86_bios_cpu_apicid); 465 466 467 static inline unsigned int read_apic_id(void) 468 { 469 unsigned int reg; 470 471 reg = apic_read(APIC_ID); 472 473 return apic->get_apic_id(reg); 474 } 475 476 extern void default_setup_apic_routing(void); 477 478 #ifdef CONFIG_X86_32 479 480 extern struct apic apic_default; 481 482 /* 483 * Set up the logical destination ID. 484 * 485 * Intel recommends to set DFR, LDR and TPR before enabling 486 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel 487 * document number 292116). So here it goes... 488 */ 489 extern void default_init_apic_ldr(void); 490 491 static inline int default_apic_id_registered(void) 492 { 493 return physid_isset(read_apic_id(), phys_cpu_present_map); 494 } 495 496 static inline int default_phys_pkg_id(int cpuid_apic, int index_msb) 497 { 498 return cpuid_apic >> index_msb; 499 } 500 501 extern int default_apicid_to_node(int logical_apicid); 502 503 #endif 504 505 static inline unsigned int 506 default_cpu_mask_to_apicid(const struct cpumask *cpumask) 507 { 508 return cpumask_bits(cpumask)[0] & APIC_ALL_CPUS; 509 } 510 511 static inline unsigned int 512 default_cpu_mask_to_apicid_and(const struct cpumask *cpumask, 513 const struct cpumask *andmask) 514 { 515 unsigned long mask1 = cpumask_bits(cpumask)[0]; 516 unsigned long mask2 = cpumask_bits(andmask)[0]; 517 unsigned long mask3 = cpumask_bits(cpu_online_mask)[0]; 518 519 return (unsigned int)(mask1 & mask2 & mask3); 520 } 521 522 static inline unsigned long default_check_apicid_used(physid_mask_t bitmap, int apicid) 523 { 524 return physid_isset(apicid, bitmap); 525 } 526 527 static inline unsigned long default_check_apicid_present(int bit) 528 { 529 return physid_isset(bit, phys_cpu_present_map); 530 } 531 532 static inline physid_mask_t default_ioapic_phys_id_map(physid_mask_t phys_map) 533 { 534 return phys_map; 535 } 536 537 /* Mapping from cpu number to logical apicid */ 538 static inline int default_cpu_to_logical_apicid(int cpu) 539 { 540 return 1 << cpu; 541 } 542 543 static inline int __default_cpu_present_to_apicid(int mps_cpu) 544 { 545 if (mps_cpu < nr_cpu_ids && cpu_present(mps_cpu)) 546 return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu); 547 else 548 return BAD_APICID; 549 } 550 551 static inline int 552 __default_check_phys_apicid_present(int phys_apicid) 553 { 554 return physid_isset(phys_apicid, phys_cpu_present_map); 555 } 556 557 #ifdef CONFIG_X86_32 558 static inline int default_cpu_present_to_apicid(int mps_cpu) 559 { 560 return __default_cpu_present_to_apicid(mps_cpu); 561 } 562 563 static inline int 564 default_check_phys_apicid_present(int phys_apicid) 565 { 566 return __default_check_phys_apicid_present(phys_apicid); 567 } 568 #else 569 extern int default_cpu_present_to_apicid(int mps_cpu); 570 extern int default_check_phys_apicid_present(int phys_apicid); 571 #endif 572 573 static inline physid_mask_t default_apicid_to_cpu_present(int phys_apicid) 574 { 575 return physid_mask_of_physid(phys_apicid); 576 } 577 578 #endif /* CONFIG_X86_LOCAL_APIC */ 579 580 #ifdef CONFIG_X86_32 581 extern u8 cpu_2_logical_apicid[NR_CPUS]; 582 #endif 583 584 #endif /* _ASM_X86_APIC_H */ 585