1 #ifndef _ASM_X86_APIC_H 2 #define _ASM_X86_APIC_H 3 4 #include <linux/cpumask.h> 5 #include <linux/pm.h> 6 7 #include <asm/alternative.h> 8 #include <asm/cpufeature.h> 9 #include <asm/processor.h> 10 #include <asm/apicdef.h> 11 #include <linux/atomic.h> 12 #include <asm/fixmap.h> 13 #include <asm/mpspec.h> 14 #include <asm/system.h> 15 #include <asm/msr.h> 16 17 #define ARCH_APICTIMER_STOPS_ON_C3 1 18 19 /* 20 * Debugging macros 21 */ 22 #define APIC_QUIET 0 23 #define APIC_VERBOSE 1 24 #define APIC_DEBUG 2 25 26 /* 27 * Define the default level of output to be very little 28 * This can be turned up by using apic=verbose for more 29 * information and apic=debug for _lots_ of information. 30 * apic_verbosity is defined in apic.c 31 */ 32 #define apic_printk(v, s, a...) do { \ 33 if ((v) <= apic_verbosity) \ 34 printk(s, ##a); \ 35 } while (0) 36 37 38 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32) 39 extern void generic_apic_probe(void); 40 #else 41 static inline void generic_apic_probe(void) 42 { 43 } 44 #endif 45 46 #ifdef CONFIG_X86_LOCAL_APIC 47 48 extern unsigned int apic_verbosity; 49 extern int local_apic_timer_c2_ok; 50 51 extern int disable_apic; 52 extern unsigned int lapic_timer_frequency; 53 54 #ifdef CONFIG_SMP 55 extern void __inquire_remote_apic(int apicid); 56 #else /* CONFIG_SMP */ 57 static inline void __inquire_remote_apic(int apicid) 58 { 59 } 60 #endif /* CONFIG_SMP */ 61 62 static inline void default_inquire_remote_apic(int apicid) 63 { 64 if (apic_verbosity >= APIC_DEBUG) 65 __inquire_remote_apic(apicid); 66 } 67 68 /* 69 * With 82489DX we can't rely on apic feature bit 70 * retrieved via cpuid but still have to deal with 71 * such an apic chip so we assume that SMP configuration 72 * is found from MP table (64bit case uses ACPI mostly 73 * which set smp presence flag as well so we are safe 74 * to use this helper too). 75 */ 76 static inline bool apic_from_smp_config(void) 77 { 78 return smp_found_config && !disable_apic; 79 } 80 81 /* 82 * Basic functions accessing APICs. 83 */ 84 #ifdef CONFIG_PARAVIRT 85 #include <asm/paravirt.h> 86 #endif 87 88 #ifdef CONFIG_X86_64 89 extern int is_vsmp_box(void); 90 #else 91 static inline int is_vsmp_box(void) 92 { 93 return 0; 94 } 95 #endif 96 extern void xapic_wait_icr_idle(void); 97 extern u32 safe_xapic_wait_icr_idle(void); 98 extern void xapic_icr_write(u32, u32); 99 extern int setup_profiling_timer(unsigned int); 100 101 static inline void native_apic_mem_write(u32 reg, u32 v) 102 { 103 volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg); 104 105 alternative_io("movl %0, %1", "xchgl %0, %1", X86_FEATURE_11AP, 106 ASM_OUTPUT2("=r" (v), "=m" (*addr)), 107 ASM_OUTPUT2("0" (v), "m" (*addr))); 108 } 109 110 static inline u32 native_apic_mem_read(u32 reg) 111 { 112 return *((volatile u32 *)(APIC_BASE + reg)); 113 } 114 115 extern void native_apic_wait_icr_idle(void); 116 extern u32 native_safe_apic_wait_icr_idle(void); 117 extern void native_apic_icr_write(u32 low, u32 id); 118 extern u64 native_apic_icr_read(void); 119 120 extern int x2apic_mode; 121 122 #ifdef CONFIG_X86_X2APIC 123 /* 124 * Make previous memory operations globally visible before 125 * sending the IPI through x2apic wrmsr. We need a serializing instruction or 126 * mfence for this. 127 */ 128 static inline void x2apic_wrmsr_fence(void) 129 { 130 asm volatile("mfence" : : : "memory"); 131 } 132 133 static inline void native_apic_msr_write(u32 reg, u32 v) 134 { 135 if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR || 136 reg == APIC_LVR) 137 return; 138 139 wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0); 140 } 141 142 static inline u32 native_apic_msr_read(u32 reg) 143 { 144 u64 msr; 145 146 if (reg == APIC_DFR) 147 return -1; 148 149 rdmsrl(APIC_BASE_MSR + (reg >> 4), msr); 150 return (u32)msr; 151 } 152 153 static inline void native_x2apic_wait_icr_idle(void) 154 { 155 /* no need to wait for icr idle in x2apic */ 156 return; 157 } 158 159 static inline u32 native_safe_x2apic_wait_icr_idle(void) 160 { 161 /* no need to wait for icr idle in x2apic */ 162 return 0; 163 } 164 165 static inline void native_x2apic_icr_write(u32 low, u32 id) 166 { 167 wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low); 168 } 169 170 static inline u64 native_x2apic_icr_read(void) 171 { 172 unsigned long val; 173 174 rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val); 175 return val; 176 } 177 178 extern int x2apic_phys; 179 extern int x2apic_preenabled; 180 extern void check_x2apic(void); 181 extern void enable_x2apic(void); 182 extern void x2apic_icr_write(u32 low, u32 id); 183 static inline int x2apic_enabled(void) 184 { 185 u64 msr; 186 187 if (!cpu_has_x2apic) 188 return 0; 189 190 rdmsrl(MSR_IA32_APICBASE, msr); 191 if (msr & X2APIC_ENABLE) 192 return 1; 193 return 0; 194 } 195 196 #define x2apic_supported() (cpu_has_x2apic) 197 static inline void x2apic_force_phys(void) 198 { 199 x2apic_phys = 1; 200 } 201 #else 202 static inline void disable_x2apic(void) 203 { 204 } 205 static inline void check_x2apic(void) 206 { 207 } 208 static inline void enable_x2apic(void) 209 { 210 } 211 static inline int x2apic_enabled(void) 212 { 213 return 0; 214 } 215 static inline void x2apic_force_phys(void) 216 { 217 } 218 219 #define nox2apic 0 220 #define x2apic_preenabled 0 221 #define x2apic_supported() 0 222 #endif 223 224 extern void enable_IR_x2apic(void); 225 226 extern int get_physical_broadcast(void); 227 228 extern int lapic_get_maxlvt(void); 229 extern void clear_local_APIC(void); 230 extern void connect_bsp_APIC(void); 231 extern void disconnect_bsp_APIC(int virt_wire_setup); 232 extern void disable_local_APIC(void); 233 extern void lapic_shutdown(void); 234 extern int verify_local_APIC(void); 235 extern void sync_Arb_IDs(void); 236 extern void init_bsp_APIC(void); 237 extern void setup_local_APIC(void); 238 extern void end_local_APIC_setup(void); 239 extern void bsp_end_local_APIC_setup(void); 240 extern void init_apic_mappings(void); 241 void register_lapic_address(unsigned long address); 242 extern void setup_boot_APIC_clock(void); 243 extern void setup_secondary_APIC_clock(void); 244 extern int APIC_init_uniprocessor(void); 245 extern int apic_force_enable(unsigned long addr); 246 247 /* 248 * On 32bit this is mach-xxx local 249 */ 250 #ifdef CONFIG_X86_64 251 extern int apic_is_clustered_box(void); 252 #else 253 static inline int apic_is_clustered_box(void) 254 { 255 return 0; 256 } 257 #endif 258 259 extern int setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask); 260 261 #else /* !CONFIG_X86_LOCAL_APIC */ 262 static inline void lapic_shutdown(void) { } 263 #define local_apic_timer_c2_ok 1 264 static inline void init_apic_mappings(void) { } 265 static inline void disable_local_APIC(void) { } 266 # define setup_boot_APIC_clock x86_init_noop 267 # define setup_secondary_APIC_clock x86_init_noop 268 #endif /* !CONFIG_X86_LOCAL_APIC */ 269 270 #ifdef CONFIG_X86_64 271 #define SET_APIC_ID(x) (apic->set_apic_id(x)) 272 #else 273 274 #endif 275 276 /* 277 * Copyright 2004 James Cleverdon, IBM. 278 * Subject to the GNU Public License, v.2 279 * 280 * Generic APIC sub-arch data struct. 281 * 282 * Hacked for x86-64 by James Cleverdon from i386 architecture code by 283 * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and 284 * James Cleverdon. 285 */ 286 struct apic { 287 char *name; 288 289 int (*probe)(void); 290 int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id); 291 int (*apic_id_valid)(int apicid); 292 int (*apic_id_registered)(void); 293 294 u32 irq_delivery_mode; 295 u32 irq_dest_mode; 296 297 const struct cpumask *(*target_cpus)(void); 298 299 int disable_esr; 300 301 int dest_logical; 302 unsigned long (*check_apicid_used)(physid_mask_t *map, int apicid); 303 unsigned long (*check_apicid_present)(int apicid); 304 305 void (*vector_allocation_domain)(int cpu, struct cpumask *retmask); 306 void (*init_apic_ldr)(void); 307 308 void (*ioapic_phys_id_map)(physid_mask_t *phys_map, physid_mask_t *retmap); 309 310 void (*setup_apic_routing)(void); 311 int (*multi_timer_check)(int apic, int irq); 312 int (*cpu_present_to_apicid)(int mps_cpu); 313 void (*apicid_to_cpu_present)(int phys_apicid, physid_mask_t *retmap); 314 void (*setup_portio_remap)(void); 315 int (*check_phys_apicid_present)(int phys_apicid); 316 void (*enable_apic_mode)(void); 317 int (*phys_pkg_id)(int cpuid_apic, int index_msb); 318 319 /* 320 * When one of the next two hooks returns 1 the apic 321 * is switched to this. Essentially they are additional 322 * probe functions: 323 */ 324 int (*mps_oem_check)(struct mpc_table *mpc, char *oem, char *productid); 325 326 unsigned int (*get_apic_id)(unsigned long x); 327 unsigned long (*set_apic_id)(unsigned int id); 328 unsigned long apic_id_mask; 329 330 unsigned int (*cpu_mask_to_apicid)(const struct cpumask *cpumask); 331 unsigned int (*cpu_mask_to_apicid_and)(const struct cpumask *cpumask, 332 const struct cpumask *andmask); 333 334 /* ipi */ 335 void (*send_IPI_mask)(const struct cpumask *mask, int vector); 336 void (*send_IPI_mask_allbutself)(const struct cpumask *mask, 337 int vector); 338 void (*send_IPI_allbutself)(int vector); 339 void (*send_IPI_all)(int vector); 340 void (*send_IPI_self)(int vector); 341 342 /* wakeup_secondary_cpu */ 343 int (*wakeup_secondary_cpu)(int apicid, unsigned long start_eip); 344 345 int trampoline_phys_low; 346 int trampoline_phys_high; 347 348 void (*wait_for_init_deassert)(atomic_t *deassert); 349 void (*smp_callin_clear_local_apic)(void); 350 void (*inquire_remote_apic)(int apicid); 351 352 /* apic ops */ 353 u32 (*read)(u32 reg); 354 void (*write)(u32 reg, u32 v); 355 u64 (*icr_read)(void); 356 void (*icr_write)(u32 low, u32 high); 357 void (*wait_icr_idle)(void); 358 u32 (*safe_wait_icr_idle)(void); 359 360 #ifdef CONFIG_X86_32 361 /* 362 * Called very early during boot from get_smp_config(). It should 363 * return the logical apicid. x86_[bios]_cpu_to_apicid is 364 * initialized before this function is called. 365 * 366 * If logical apicid can't be determined that early, the function 367 * may return BAD_APICID. Logical apicid will be configured after 368 * init_apic_ldr() while bringing up CPUs. Note that NUMA affinity 369 * won't be applied properly during early boot in this case. 370 */ 371 int (*x86_32_early_logical_apicid)(int cpu); 372 373 /* 374 * Optional method called from setup_local_APIC() after logical 375 * apicid is guaranteed to be known to initialize apicid -> node 376 * mapping if NUMA initialization hasn't done so already. Don't 377 * add new users. 378 */ 379 int (*x86_32_numa_cpu_node)(int cpu); 380 #endif 381 }; 382 383 /* 384 * Pointer to the local APIC driver in use on this system (there's 385 * always just one such driver in use - the kernel decides via an 386 * early probing process which one it picks - and then sticks to it): 387 */ 388 extern struct apic *apic; 389 390 /* 391 * APIC drivers are probed based on how they are listed in the .apicdrivers 392 * section. So the order is important and enforced by the ordering 393 * of different apic driver files in the Makefile. 394 * 395 * For the files having two apic drivers, we use apic_drivers() 396 * to enforce the order with in them. 397 */ 398 #define apic_driver(sym) \ 399 static struct apic *__apicdrivers_##sym __used \ 400 __aligned(sizeof(struct apic *)) \ 401 __section(.apicdrivers) = { &sym } 402 403 #define apic_drivers(sym1, sym2) \ 404 static struct apic *__apicdrivers_##sym1##sym2[2] __used \ 405 __aligned(sizeof(struct apic *)) \ 406 __section(.apicdrivers) = { &sym1, &sym2 } 407 408 extern struct apic *__apicdrivers[], *__apicdrivers_end[]; 409 410 /* 411 * APIC functionality to boot other CPUs - only used on SMP: 412 */ 413 #ifdef CONFIG_SMP 414 extern atomic_t init_deasserted; 415 extern int wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip); 416 #endif 417 418 #ifdef CONFIG_X86_LOCAL_APIC 419 420 static inline u32 apic_read(u32 reg) 421 { 422 return apic->read(reg); 423 } 424 425 static inline void apic_write(u32 reg, u32 val) 426 { 427 apic->write(reg, val); 428 } 429 430 static inline u64 apic_icr_read(void) 431 { 432 return apic->icr_read(); 433 } 434 435 static inline void apic_icr_write(u32 low, u32 high) 436 { 437 apic->icr_write(low, high); 438 } 439 440 static inline void apic_wait_icr_idle(void) 441 { 442 apic->wait_icr_idle(); 443 } 444 445 static inline u32 safe_apic_wait_icr_idle(void) 446 { 447 return apic->safe_wait_icr_idle(); 448 } 449 450 #else /* CONFIG_X86_LOCAL_APIC */ 451 452 static inline u32 apic_read(u32 reg) { return 0; } 453 static inline void apic_write(u32 reg, u32 val) { } 454 static inline u64 apic_icr_read(void) { return 0; } 455 static inline void apic_icr_write(u32 low, u32 high) { } 456 static inline void apic_wait_icr_idle(void) { } 457 static inline u32 safe_apic_wait_icr_idle(void) { return 0; } 458 459 #endif /* CONFIG_X86_LOCAL_APIC */ 460 461 static inline void ack_APIC_irq(void) 462 { 463 /* 464 * ack_APIC_irq() actually gets compiled as a single instruction 465 * ... yummie. 466 */ 467 468 /* Docs say use 0 for future compatibility */ 469 apic_write(APIC_EOI, 0); 470 } 471 472 static inline unsigned default_get_apic_id(unsigned long x) 473 { 474 unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR)); 475 476 if (APIC_XAPIC(ver) || boot_cpu_has(X86_FEATURE_EXTD_APICID)) 477 return (x >> 24) & 0xFF; 478 else 479 return (x >> 24) & 0x0F; 480 } 481 482 /* 483 * Warm reset vector default position: 484 */ 485 #define DEFAULT_TRAMPOLINE_PHYS_LOW 0x467 486 #define DEFAULT_TRAMPOLINE_PHYS_HIGH 0x469 487 488 #ifdef CONFIG_X86_64 489 extern int default_acpi_madt_oem_check(char *, char *); 490 491 extern void apic_send_IPI_self(int vector); 492 493 DECLARE_PER_CPU(int, x2apic_extra_bits); 494 495 extern int default_cpu_present_to_apicid(int mps_cpu); 496 extern int default_check_phys_apicid_present(int phys_apicid); 497 #endif 498 499 static inline void default_wait_for_init_deassert(atomic_t *deassert) 500 { 501 while (!atomic_read(deassert)) 502 cpu_relax(); 503 return; 504 } 505 506 extern void generic_bigsmp_probe(void); 507 508 509 #ifdef CONFIG_X86_LOCAL_APIC 510 511 #include <asm/smp.h> 512 513 #define APIC_DFR_VALUE (APIC_DFR_FLAT) 514 515 static inline const struct cpumask *default_target_cpus(void) 516 { 517 #ifdef CONFIG_SMP 518 return cpu_online_mask; 519 #else 520 return cpumask_of(0); 521 #endif 522 } 523 524 DECLARE_EARLY_PER_CPU(u16, x86_bios_cpu_apicid); 525 526 527 static inline unsigned int read_apic_id(void) 528 { 529 unsigned int reg; 530 531 reg = apic_read(APIC_ID); 532 533 return apic->get_apic_id(reg); 534 } 535 536 static inline int default_apic_id_valid(int apicid) 537 { 538 return x2apic_mode || (apicid < 255); 539 } 540 541 extern void default_setup_apic_routing(void); 542 543 extern struct apic apic_noop; 544 545 #ifdef CONFIG_X86_32 546 547 static inline int noop_x86_32_early_logical_apicid(int cpu) 548 { 549 return BAD_APICID; 550 } 551 552 /* 553 * Set up the logical destination ID. 554 * 555 * Intel recommends to set DFR, LDR and TPR before enabling 556 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel 557 * document number 292116). So here it goes... 558 */ 559 extern void default_init_apic_ldr(void); 560 561 static inline int default_apic_id_registered(void) 562 { 563 return physid_isset(read_apic_id(), phys_cpu_present_map); 564 } 565 566 static inline int default_phys_pkg_id(int cpuid_apic, int index_msb) 567 { 568 return cpuid_apic >> index_msb; 569 } 570 571 #endif 572 573 static inline unsigned int 574 default_cpu_mask_to_apicid(const struct cpumask *cpumask) 575 { 576 return cpumask_bits(cpumask)[0] & APIC_ALL_CPUS; 577 } 578 579 static inline unsigned int 580 default_cpu_mask_to_apicid_and(const struct cpumask *cpumask, 581 const struct cpumask *andmask) 582 { 583 unsigned long mask1 = cpumask_bits(cpumask)[0]; 584 unsigned long mask2 = cpumask_bits(andmask)[0]; 585 unsigned long mask3 = cpumask_bits(cpu_online_mask)[0]; 586 587 return (unsigned int)(mask1 & mask2 & mask3); 588 } 589 590 static inline unsigned long default_check_apicid_used(physid_mask_t *map, int apicid) 591 { 592 return physid_isset(apicid, *map); 593 } 594 595 static inline unsigned long default_check_apicid_present(int bit) 596 { 597 return physid_isset(bit, phys_cpu_present_map); 598 } 599 600 static inline void default_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mask_t *retmap) 601 { 602 *retmap = *phys_map; 603 } 604 605 static inline int __default_cpu_present_to_apicid(int mps_cpu) 606 { 607 if (mps_cpu < nr_cpu_ids && cpu_present(mps_cpu)) 608 return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu); 609 else 610 return BAD_APICID; 611 } 612 613 static inline int 614 __default_check_phys_apicid_present(int phys_apicid) 615 { 616 return physid_isset(phys_apicid, phys_cpu_present_map); 617 } 618 619 #ifdef CONFIG_X86_32 620 static inline int default_cpu_present_to_apicid(int mps_cpu) 621 { 622 return __default_cpu_present_to_apicid(mps_cpu); 623 } 624 625 static inline int 626 default_check_phys_apicid_present(int phys_apicid) 627 { 628 return __default_check_phys_apicid_present(phys_apicid); 629 } 630 #else 631 extern int default_cpu_present_to_apicid(int mps_cpu); 632 extern int default_check_phys_apicid_present(int phys_apicid); 633 #endif 634 635 #endif /* CONFIG_X86_LOCAL_APIC */ 636 637 #endif /* _ASM_X86_APIC_H */ 638