1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 #ifndef _ASM_X86_APIC_H 3 #define _ASM_X86_APIC_H 4 5 #include <linux/cpumask.h> 6 7 #include <asm/alternative.h> 8 #include <asm/cpufeature.h> 9 #include <asm/apicdef.h> 10 #include <linux/atomic.h> 11 #include <asm/fixmap.h> 12 #include <asm/mpspec.h> 13 #include <asm/msr.h> 14 #include <asm/hardirq.h> 15 16 #define ARCH_APICTIMER_STOPS_ON_C3 1 17 18 /* 19 * Debugging macros 20 */ 21 #define APIC_QUIET 0 22 #define APIC_VERBOSE 1 23 #define APIC_DEBUG 2 24 25 /* Macros for apic_extnmi which controls external NMI masking */ 26 #define APIC_EXTNMI_BSP 0 /* Default */ 27 #define APIC_EXTNMI_ALL 1 28 #define APIC_EXTNMI_NONE 2 29 30 /* 31 * Define the default level of output to be very little 32 * This can be turned up by using apic=verbose for more 33 * information and apic=debug for _lots_ of information. 34 * apic_verbosity is defined in apic.c 35 */ 36 #define apic_printk(v, s, a...) do { \ 37 if ((v) <= apic_verbosity) \ 38 printk(s, ##a); \ 39 } while (0) 40 41 42 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32) 43 extern void x86_32_probe_apic(void); 44 #else 45 static inline void x86_32_probe_apic(void) { } 46 #endif 47 48 #ifdef CONFIG_X86_LOCAL_APIC 49 50 extern int apic_verbosity; 51 extern int local_apic_timer_c2_ok; 52 53 extern bool apic_is_disabled; 54 extern unsigned int lapic_timer_period; 55 56 extern int cpuid_to_apicid[]; 57 58 extern enum apic_intr_mode_id apic_intr_mode; 59 enum apic_intr_mode_id { 60 APIC_PIC, 61 APIC_VIRTUAL_WIRE, 62 APIC_VIRTUAL_WIRE_NO_CONFIG, 63 APIC_SYMMETRIC_IO, 64 APIC_SYMMETRIC_IO_NO_ROUTING 65 }; 66 67 /* 68 * With 82489DX we can't rely on apic feature bit 69 * retrieved via cpuid but still have to deal with 70 * such an apic chip so we assume that SMP configuration 71 * is found from MP table (64bit case uses ACPI mostly 72 * which set smp presence flag as well so we are safe 73 * to use this helper too). 74 */ 75 static inline bool apic_from_smp_config(void) 76 { 77 return smp_found_config && !apic_is_disabled; 78 } 79 80 /* 81 * Basic functions accessing APICs. 82 */ 83 #ifdef CONFIG_PARAVIRT 84 #include <asm/paravirt.h> 85 #endif 86 87 static inline void native_apic_mem_write(u32 reg, u32 v) 88 { 89 volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg); 90 91 alternative_io("movl %0, %P1", "xchgl %0, %P1", X86_BUG_11AP, 92 ASM_OUTPUT2("=r" (v), "=m" (*addr)), 93 ASM_OUTPUT2("0" (v), "m" (*addr))); 94 } 95 96 static inline u32 native_apic_mem_read(u32 reg) 97 { 98 return *((volatile u32 *)(APIC_BASE + reg)); 99 } 100 101 extern void native_apic_icr_write(u32 low, u32 id); 102 extern u64 native_apic_icr_read(void); 103 104 static inline bool apic_is_x2apic_enabled(void) 105 { 106 u64 msr; 107 108 if (rdmsrl_safe(MSR_IA32_APICBASE, &msr)) 109 return false; 110 return msr & X2APIC_ENABLE; 111 } 112 113 extern void enable_IR_x2apic(void); 114 115 extern int get_physical_broadcast(void); 116 117 extern int lapic_get_maxlvt(void); 118 extern void clear_local_APIC(void); 119 extern void disconnect_bsp_APIC(int virt_wire_setup); 120 extern void disable_local_APIC(void); 121 extern void apic_soft_disable(void); 122 extern void lapic_shutdown(void); 123 extern void sync_Arb_IDs(void); 124 extern void init_bsp_APIC(void); 125 extern void apic_intr_mode_select(void); 126 extern void apic_intr_mode_init(void); 127 extern void init_apic_mappings(void); 128 void register_lapic_address(unsigned long address); 129 extern void setup_boot_APIC_clock(void); 130 extern void setup_secondary_APIC_clock(void); 131 extern void lapic_update_tsc_freq(void); 132 133 #ifdef CONFIG_X86_64 134 static inline bool apic_force_enable(unsigned long addr) 135 { 136 return false; 137 } 138 #else 139 extern bool apic_force_enable(unsigned long addr); 140 #endif 141 142 extern void apic_ap_setup(void); 143 144 /* 145 * On 32bit this is mach-xxx local 146 */ 147 #ifdef CONFIG_X86_64 148 extern int apic_is_clustered_box(void); 149 #else 150 static inline int apic_is_clustered_box(void) 151 { 152 return 0; 153 } 154 #endif 155 156 extern int setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask); 157 extern void lapic_assign_system_vectors(void); 158 extern void lapic_assign_legacy_vector(unsigned int isairq, bool replace); 159 extern void lapic_update_legacy_vectors(void); 160 extern void lapic_online(void); 161 extern void lapic_offline(void); 162 extern bool apic_needs_pit(void); 163 164 extern void apic_send_IPI_allbutself(unsigned int vector); 165 166 #else /* !CONFIG_X86_LOCAL_APIC */ 167 static inline void lapic_shutdown(void) { } 168 #define local_apic_timer_c2_ok 1 169 static inline void init_apic_mappings(void) { } 170 static inline void disable_local_APIC(void) { } 171 # define setup_boot_APIC_clock x86_init_noop 172 # define setup_secondary_APIC_clock x86_init_noop 173 static inline void lapic_update_tsc_freq(void) { } 174 static inline void init_bsp_APIC(void) { } 175 static inline void apic_intr_mode_select(void) { } 176 static inline void apic_intr_mode_init(void) { } 177 static inline void lapic_assign_system_vectors(void) { } 178 static inline void lapic_assign_legacy_vector(unsigned int i, bool r) { } 179 static inline bool apic_needs_pit(void) { return true; } 180 #endif /* !CONFIG_X86_LOCAL_APIC */ 181 182 #ifdef CONFIG_X86_X2APIC 183 static inline void native_apic_msr_write(u32 reg, u32 v) 184 { 185 if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR || 186 reg == APIC_LVR) 187 return; 188 189 wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0); 190 } 191 192 static inline void native_apic_msr_eoi_write(u32 reg, u32 v) 193 { 194 __wrmsr(APIC_BASE_MSR + (APIC_EOI >> 4), APIC_EOI_ACK, 0); 195 } 196 197 static inline u32 native_apic_msr_read(u32 reg) 198 { 199 u64 msr; 200 201 if (reg == APIC_DFR) 202 return -1; 203 204 rdmsrl(APIC_BASE_MSR + (reg >> 4), msr); 205 return (u32)msr; 206 } 207 208 static inline void native_x2apic_icr_write(u32 low, u32 id) 209 { 210 wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low); 211 } 212 213 static inline u64 native_x2apic_icr_read(void) 214 { 215 unsigned long val; 216 217 rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val); 218 return val; 219 } 220 221 extern int x2apic_mode; 222 extern int x2apic_phys; 223 extern void __init x2apic_set_max_apicid(u32 apicid); 224 extern void x2apic_setup(void); 225 static inline int x2apic_enabled(void) 226 { 227 return boot_cpu_has(X86_FEATURE_X2APIC) && apic_is_x2apic_enabled(); 228 } 229 230 #define x2apic_supported() (boot_cpu_has(X86_FEATURE_X2APIC)) 231 #else /* !CONFIG_X86_X2APIC */ 232 static inline void x2apic_setup(void) { } 233 static inline int x2apic_enabled(void) { return 0; } 234 static inline u32 native_apic_msr_read(u32 reg) { BUG(); } 235 #define x2apic_mode (0) 236 #define x2apic_supported() (0) 237 #endif /* !CONFIG_X86_X2APIC */ 238 extern void __init check_x2apic(void); 239 240 struct irq_data; 241 242 /* 243 * Copyright 2004 James Cleverdon, IBM. 244 * 245 * Generic APIC sub-arch data struct. 246 * 247 * Hacked for x86-64 by James Cleverdon from i386 architecture code by 248 * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and 249 * James Cleverdon. 250 */ 251 struct apic { 252 /* Hotpath functions first */ 253 void (*eoi_write)(u32 reg, u32 v); 254 void (*native_eoi_write)(u32 reg, u32 v); 255 void (*write)(u32 reg, u32 v); 256 u32 (*read)(u32 reg); 257 258 /* IPI related functions */ 259 void (*wait_icr_idle)(void); 260 u32 (*safe_wait_icr_idle)(void); 261 262 void (*send_IPI)(int cpu, int vector); 263 void (*send_IPI_mask)(const struct cpumask *mask, int vector); 264 void (*send_IPI_mask_allbutself)(const struct cpumask *msk, int vec); 265 void (*send_IPI_allbutself)(int vector); 266 void (*send_IPI_all)(int vector); 267 void (*send_IPI_self)(int vector); 268 269 u32 disable_esr; 270 271 enum apic_delivery_modes delivery_mode; 272 bool dest_mode_logical; 273 274 u32 (*calc_dest_apicid)(unsigned int cpu); 275 276 /* ICR related functions */ 277 u64 (*icr_read)(void); 278 void (*icr_write)(u32 low, u32 high); 279 280 /* Probe, setup and smpboot functions */ 281 int (*probe)(void); 282 int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id); 283 int (*apic_id_valid)(u32 apicid); 284 bool (*apic_id_registered)(void); 285 286 bool (*check_apicid_used)(physid_mask_t *map, int apicid); 287 void (*init_apic_ldr)(void); 288 void (*ioapic_phys_id_map)(physid_mask_t *phys_map, physid_mask_t *retmap); 289 int (*cpu_present_to_apicid)(int mps_cpu); 290 int (*phys_pkg_id)(int cpuid_apic, int index_msb); 291 292 u32 (*get_apic_id)(unsigned long x); 293 u32 (*set_apic_id)(unsigned int id); 294 295 /* wakeup_secondary_cpu */ 296 int (*wakeup_secondary_cpu)(int apicid, unsigned long start_eip); 297 /* wakeup secondary CPU using 64-bit wakeup point */ 298 int (*wakeup_secondary_cpu_64)(int apicid, unsigned long start_eip); 299 300 char *name; 301 }; 302 303 /* 304 * Pointer to the local APIC driver in use on this system (there's 305 * always just one such driver in use - the kernel decides via an 306 * early probing process which one it picks - and then sticks to it): 307 */ 308 extern struct apic *apic; 309 310 /* 311 * APIC drivers are probed based on how they are listed in the .apicdrivers 312 * section. So the order is important and enforced by the ordering 313 * of different apic driver files in the Makefile. 314 * 315 * For the files having two apic drivers, we use apic_drivers() 316 * to enforce the order with in them. 317 */ 318 #define apic_driver(sym) \ 319 static const struct apic *__apicdrivers_##sym __used \ 320 __aligned(sizeof(struct apic *)) \ 321 __section(".apicdrivers") = { &sym } 322 323 #define apic_drivers(sym1, sym2) \ 324 static struct apic *__apicdrivers_##sym1##sym2[2] __used \ 325 __aligned(sizeof(struct apic *)) \ 326 __section(".apicdrivers") = { &sym1, &sym2 } 327 328 extern struct apic *__apicdrivers[], *__apicdrivers_end[]; 329 330 /* 331 * APIC functionality to boot other CPUs - only used on SMP: 332 */ 333 #ifdef CONFIG_SMP 334 extern int lapic_can_unplug_cpu(void); 335 #endif 336 337 #ifdef CONFIG_X86_LOCAL_APIC 338 339 static inline u32 apic_read(u32 reg) 340 { 341 return apic->read(reg); 342 } 343 344 static inline void apic_write(u32 reg, u32 val) 345 { 346 apic->write(reg, val); 347 } 348 349 static inline void apic_eoi(void) 350 { 351 apic->eoi_write(APIC_EOI, APIC_EOI_ACK); 352 } 353 354 static inline u64 apic_icr_read(void) 355 { 356 return apic->icr_read(); 357 } 358 359 static inline void apic_icr_write(u32 low, u32 high) 360 { 361 apic->icr_write(low, high); 362 } 363 364 static inline void apic_wait_icr_idle(void) 365 { 366 if (apic->wait_icr_idle) 367 apic->wait_icr_idle(); 368 } 369 370 static inline u32 safe_apic_wait_icr_idle(void) 371 { 372 return apic->safe_wait_icr_idle ? apic->safe_wait_icr_idle() : 0; 373 } 374 375 extern void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)); 376 377 #else /* CONFIG_X86_LOCAL_APIC */ 378 379 static inline u32 apic_read(u32 reg) { return 0; } 380 static inline void apic_write(u32 reg, u32 val) { } 381 static inline void apic_eoi(void) { } 382 static inline u64 apic_icr_read(void) { return 0; } 383 static inline void apic_icr_write(u32 low, u32 high) { } 384 static inline void apic_wait_icr_idle(void) { } 385 static inline u32 safe_apic_wait_icr_idle(void) { return 0; } 386 static inline void apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) {} 387 388 #endif /* CONFIG_X86_LOCAL_APIC */ 389 390 extern void apic_ack_irq(struct irq_data *data); 391 392 static inline void ack_APIC_irq(void) 393 { 394 /* 395 * ack_APIC_irq() actually gets compiled as a single instruction 396 * ... yummie. 397 */ 398 apic_eoi(); 399 } 400 401 402 static inline bool lapic_vector_set_in_irr(unsigned int vector) 403 { 404 u32 irr = apic_read(APIC_IRR + (vector / 32 * 0x10)); 405 406 return !!(irr & (1U << (vector % 32))); 407 } 408 409 static inline unsigned default_get_apic_id(unsigned long x) 410 { 411 unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR)); 412 413 if (APIC_XAPIC(ver) || boot_cpu_has(X86_FEATURE_EXTD_APICID)) 414 return (x >> 24) & 0xFF; 415 else 416 return (x >> 24) & 0x0F; 417 } 418 419 /* 420 * Warm reset vector position: 421 */ 422 #define TRAMPOLINE_PHYS_LOW 0x467 423 #define TRAMPOLINE_PHYS_HIGH 0x469 424 425 extern void generic_bigsmp_probe(void); 426 427 #ifdef CONFIG_X86_LOCAL_APIC 428 429 #include <asm/smp.h> 430 431 extern struct apic apic_noop; 432 433 static inline unsigned int read_apic_id(void) 434 { 435 unsigned int reg = apic_read(APIC_ID); 436 437 return apic->get_apic_id(reg); 438 } 439 440 #ifdef CONFIG_X86_64 441 typedef int (*wakeup_cpu_handler)(int apicid, unsigned long start_eip); 442 extern void acpi_wake_cpu_handler_update(wakeup_cpu_handler handler); 443 extern int default_acpi_madt_oem_check(char *, char *); 444 extern void x86_64_probe_apic(void); 445 #else 446 static inline int default_acpi_madt_oem_check(char *a, char *b) { return 0; } 447 static inline void x86_64_probe_apic(void) { } 448 #endif 449 450 extern int default_apic_id_valid(u32 apicid); 451 452 extern u32 apic_default_calc_apicid(unsigned int cpu); 453 extern u32 apic_flat_calc_apicid(unsigned int cpu); 454 455 extern bool default_check_apicid_used(physid_mask_t *map, int apicid); 456 extern void default_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mask_t *retmap); 457 extern int default_cpu_present_to_apicid(int mps_cpu); 458 459 #else /* CONFIG_X86_LOCAL_APIC */ 460 461 static inline unsigned int read_apic_id(void) { return 0; } 462 463 #endif /* !CONFIG_X86_LOCAL_APIC */ 464 465 #ifdef CONFIG_SMP 466 void apic_smt_update(void); 467 #else 468 static inline void apic_smt_update(void) { } 469 #endif 470 471 struct msi_msg; 472 struct irq_cfg; 473 474 extern void __irq_msi_compose_msg(struct irq_cfg *cfg, struct msi_msg *msg, 475 bool dmar); 476 477 extern void ioapic_zap_locks(void); 478 479 #endif /* _ASM_X86_APIC_H */ 480