1 #ifndef _ASM_X86_APIC_H 2 #define _ASM_X86_APIC_H 3 4 #include <linux/cpumask.h> 5 #include <linux/delay.h> 6 #include <linux/pm.h> 7 8 #include <asm/alternative.h> 9 #include <asm/cpufeature.h> 10 #include <asm/processor.h> 11 #include <asm/apicdef.h> 12 #include <asm/atomic.h> 13 #include <asm/fixmap.h> 14 #include <asm/mpspec.h> 15 #include <asm/system.h> 16 #include <asm/msr.h> 17 18 #define ARCH_APICTIMER_STOPS_ON_C3 1 19 20 /* 21 * Debugging macros 22 */ 23 #define APIC_QUIET 0 24 #define APIC_VERBOSE 1 25 #define APIC_DEBUG 2 26 27 /* 28 * Define the default level of output to be very little 29 * This can be turned up by using apic=verbose for more 30 * information and apic=debug for _lots_ of information. 31 * apic_verbosity is defined in apic.c 32 */ 33 #define apic_printk(v, s, a...) do { \ 34 if ((v) <= apic_verbosity) \ 35 printk(s, ##a); \ 36 } while (0) 37 38 39 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32) 40 extern void generic_apic_probe(void); 41 #else 42 static inline void generic_apic_probe(void) 43 { 44 } 45 #endif 46 47 #ifdef CONFIG_X86_LOCAL_APIC 48 49 extern unsigned int apic_verbosity; 50 extern int local_apic_timer_c2_ok; 51 52 extern int disable_apic; 53 54 #ifdef CONFIG_SMP 55 extern void __inquire_remote_apic(int apicid); 56 #else /* CONFIG_SMP */ 57 static inline void __inquire_remote_apic(int apicid) 58 { 59 } 60 #endif /* CONFIG_SMP */ 61 62 static inline void default_inquire_remote_apic(int apicid) 63 { 64 if (apic_verbosity >= APIC_DEBUG) 65 __inquire_remote_apic(apicid); 66 } 67 68 /* 69 * Basic functions accessing APICs. 70 */ 71 #ifdef CONFIG_PARAVIRT 72 #include <asm/paravirt.h> 73 #else 74 #define setup_boot_clock setup_boot_APIC_clock 75 #define setup_secondary_clock setup_secondary_APIC_clock 76 #endif 77 78 extern int is_vsmp_box(void); 79 extern void xapic_wait_icr_idle(void); 80 extern u32 safe_xapic_wait_icr_idle(void); 81 extern void xapic_icr_write(u32, u32); 82 extern int setup_profiling_timer(unsigned int); 83 84 static inline void native_apic_mem_write(u32 reg, u32 v) 85 { 86 volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg); 87 88 alternative_io("movl %0, %1", "xchgl %0, %1", X86_FEATURE_11AP, 89 ASM_OUTPUT2("=r" (v), "=m" (*addr)), 90 ASM_OUTPUT2("0" (v), "m" (*addr))); 91 } 92 93 static inline u32 native_apic_mem_read(u32 reg) 94 { 95 return *((volatile u32 *)(APIC_BASE + reg)); 96 } 97 98 extern void native_apic_wait_icr_idle(void); 99 extern u32 native_safe_apic_wait_icr_idle(void); 100 extern void native_apic_icr_write(u32 low, u32 id); 101 extern u64 native_apic_icr_read(void); 102 103 #ifdef CONFIG_X86_X2APIC 104 static inline void native_apic_msr_write(u32 reg, u32 v) 105 { 106 if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR || 107 reg == APIC_LVR) 108 return; 109 110 wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0); 111 } 112 113 static inline u32 native_apic_msr_read(u32 reg) 114 { 115 u32 low, high; 116 117 if (reg == APIC_DFR) 118 return -1; 119 120 rdmsr(APIC_BASE_MSR + (reg >> 4), low, high); 121 return low; 122 } 123 124 static inline void native_x2apic_wait_icr_idle(void) 125 { 126 /* no need to wait for icr idle in x2apic */ 127 return; 128 } 129 130 static inline u32 native_safe_x2apic_wait_icr_idle(void) 131 { 132 /* no need to wait for icr idle in x2apic */ 133 return 0; 134 } 135 136 static inline void native_x2apic_icr_write(u32 low, u32 id) 137 { 138 wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low); 139 } 140 141 static inline u64 native_x2apic_icr_read(void) 142 { 143 unsigned long val; 144 145 rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val); 146 return val; 147 } 148 149 extern int x2apic; 150 extern void check_x2apic(void); 151 extern void enable_x2apic(void); 152 extern void enable_IR_x2apic(void); 153 extern void x2apic_icr_write(u32 low, u32 id); 154 static inline int x2apic_enabled(void) 155 { 156 int msr, msr2; 157 158 if (!cpu_has_x2apic) 159 return 0; 160 161 rdmsr(MSR_IA32_APICBASE, msr, msr2); 162 if (msr & X2APIC_ENABLE) 163 return 1; 164 return 0; 165 } 166 #else 167 static inline void check_x2apic(void) 168 { 169 } 170 static inline void enable_x2apic(void) 171 { 172 } 173 static inline void enable_IR_x2apic(void) 174 { 175 } 176 static inline int x2apic_enabled(void) 177 { 178 return 0; 179 } 180 #endif 181 182 extern int get_physical_broadcast(void); 183 184 #ifdef CONFIG_X86_X2APIC 185 static inline void ack_x2APIC_irq(void) 186 { 187 /* Docs say use 0 for future compatibility */ 188 native_apic_msr_write(APIC_EOI, 0); 189 } 190 #endif 191 192 extern int lapic_get_maxlvt(void); 193 extern void clear_local_APIC(void); 194 extern void connect_bsp_APIC(void); 195 extern void disconnect_bsp_APIC(int virt_wire_setup); 196 extern void disable_local_APIC(void); 197 extern void lapic_shutdown(void); 198 extern int verify_local_APIC(void); 199 extern void cache_APIC_registers(void); 200 extern void sync_Arb_IDs(void); 201 extern void init_bsp_APIC(void); 202 extern void setup_local_APIC(void); 203 extern void end_local_APIC_setup(void); 204 extern void init_apic_mappings(void); 205 extern void setup_boot_APIC_clock(void); 206 extern void setup_secondary_APIC_clock(void); 207 extern int APIC_init_uniprocessor(void); 208 extern void enable_NMI_through_LVT0(void); 209 210 /* 211 * On 32bit this is mach-xxx local 212 */ 213 #ifdef CONFIG_X86_64 214 extern void early_init_lapic_mapping(void); 215 extern int apic_is_clustered_box(void); 216 #else 217 static inline int apic_is_clustered_box(void) 218 { 219 return 0; 220 } 221 #endif 222 223 extern u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask); 224 extern u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask); 225 226 227 #else /* !CONFIG_X86_LOCAL_APIC */ 228 static inline void lapic_shutdown(void) { } 229 #define local_apic_timer_c2_ok 1 230 static inline void init_apic_mappings(void) { } 231 static inline void disable_local_APIC(void) { } 232 233 #endif /* !CONFIG_X86_LOCAL_APIC */ 234 235 #ifdef CONFIG_X86_64 236 #define SET_APIC_ID(x) (apic->set_apic_id(x)) 237 #else 238 239 #endif 240 241 /* 242 * Copyright 2004 James Cleverdon, IBM. 243 * Subject to the GNU Public License, v.2 244 * 245 * Generic APIC sub-arch data struct. 246 * 247 * Hacked for x86-64 by James Cleverdon from i386 architecture code by 248 * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and 249 * James Cleverdon. 250 */ 251 struct genapic { 252 char *name; 253 254 int (*probe)(void); 255 int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id); 256 int (*apic_id_registered)(void); 257 258 u32 irq_delivery_mode; 259 u32 irq_dest_mode; 260 261 const struct cpumask *(*target_cpus)(void); 262 263 int disable_esr; 264 265 int dest_logical; 266 unsigned long (*check_apicid_used)(physid_mask_t bitmap, int apicid); 267 unsigned long (*check_apicid_present)(int apicid); 268 269 void (*vector_allocation_domain)(int cpu, struct cpumask *retmask); 270 void (*init_apic_ldr)(void); 271 272 physid_mask_t (*ioapic_phys_id_map)(physid_mask_t map); 273 274 void (*setup_apic_routing)(void); 275 int (*multi_timer_check)(int apic, int irq); 276 int (*apicid_to_node)(int logical_apicid); 277 int (*cpu_to_logical_apicid)(int cpu); 278 int (*cpu_present_to_apicid)(int mps_cpu); 279 physid_mask_t (*apicid_to_cpu_present)(int phys_apicid); 280 void (*setup_portio_remap)(void); 281 int (*check_phys_apicid_present)(int boot_cpu_physical_apicid); 282 void (*enable_apic_mode)(void); 283 int (*phys_pkg_id)(int cpuid_apic, int index_msb); 284 285 /* 286 * When one of the next two hooks returns 1 the genapic 287 * is switched to this. Essentially they are additional 288 * probe functions: 289 */ 290 int (*mps_oem_check)(struct mpc_table *mpc, char *oem, char *productid); 291 292 unsigned int (*get_apic_id)(unsigned long x); 293 unsigned long (*set_apic_id)(unsigned int id); 294 unsigned long apic_id_mask; 295 296 unsigned int (*cpu_mask_to_apicid)(const struct cpumask *cpumask); 297 unsigned int (*cpu_mask_to_apicid_and)(const struct cpumask *cpumask, 298 const struct cpumask *andmask); 299 300 /* ipi */ 301 void (*send_IPI_mask)(const struct cpumask *mask, int vector); 302 void (*send_IPI_mask_allbutself)(const struct cpumask *mask, 303 int vector); 304 void (*send_IPI_allbutself)(int vector); 305 void (*send_IPI_all)(int vector); 306 void (*send_IPI_self)(int vector); 307 308 /* wakeup_secondary_cpu */ 309 int (*wakeup_cpu)(int apicid, unsigned long start_eip); 310 311 int trampoline_phys_low; 312 int trampoline_phys_high; 313 314 void (*wait_for_init_deassert)(atomic_t *deassert); 315 void (*smp_callin_clear_local_apic)(void); 316 void (*store_NMI_vector)(unsigned short *high, unsigned short *low); 317 void (*inquire_remote_apic)(int apicid); 318 319 /* apic ops */ 320 u32 (*read)(u32 reg); 321 void (*write)(u32 reg, u32 v); 322 u64 (*icr_read)(void); 323 void (*icr_write)(u32 low, u32 high); 324 void (*wait_icr_idle)(void); 325 u32 (*safe_wait_icr_idle)(void); 326 }; 327 328 extern struct genapic *apic; 329 330 static inline u32 apic_read(u32 reg) 331 { 332 return apic->read(reg); 333 } 334 335 static inline void apic_write(u32 reg, u32 val) 336 { 337 apic->write(reg, val); 338 } 339 340 static inline u64 apic_icr_read(void) 341 { 342 return apic->icr_read(); 343 } 344 345 static inline void apic_icr_write(u32 low, u32 high) 346 { 347 apic->icr_write(low, high); 348 } 349 350 static inline void apic_wait_icr_idle(void) 351 { 352 apic->wait_icr_idle(); 353 } 354 355 static inline u32 safe_apic_wait_icr_idle(void) 356 { 357 return apic->safe_wait_icr_idle(); 358 } 359 360 361 static inline void ack_APIC_irq(void) 362 { 363 /* 364 * ack_APIC_irq() actually gets compiled as a single instruction 365 * ... yummie. 366 */ 367 368 /* Docs say use 0 for future compatibility */ 369 apic_write(APIC_EOI, 0); 370 } 371 372 static inline unsigned default_get_apic_id(unsigned long x) 373 { 374 unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR)); 375 376 if (APIC_XAPIC(ver)) 377 return (x >> 24) & 0xFF; 378 else 379 return (x >> 24) & 0x0F; 380 } 381 382 /* 383 * Warm reset vector default position: 384 */ 385 #define DEFAULT_TRAMPOLINE_PHYS_LOW 0x467 386 #define DEFAULT_TRAMPOLINE_PHYS_HIGH 0x469 387 388 #ifdef CONFIG_X86_32 389 extern void es7000_update_genapic_to_cluster(void); 390 #else 391 extern struct genapic apic_flat; 392 extern struct genapic apic_physflat; 393 extern struct genapic apic_x2apic_cluster; 394 extern struct genapic apic_x2apic_phys; 395 extern int default_acpi_madt_oem_check(char *, char *); 396 397 extern void apic_send_IPI_self(int vector); 398 399 extern struct genapic apic_x2apic_uv_x; 400 DECLARE_PER_CPU(int, x2apic_extra_bits); 401 402 extern int default_cpu_present_to_apicid(int mps_cpu); 403 extern int default_check_phys_apicid_present(int boot_cpu_physical_apicid); 404 #endif 405 406 static inline void default_wait_for_init_deassert(atomic_t *deassert) 407 { 408 while (!atomic_read(deassert)) 409 cpu_relax(); 410 return; 411 } 412 413 extern void generic_bigsmp_probe(void); 414 415 416 #ifdef CONFIG_X86_LOCAL_APIC 417 418 #include <asm/smp.h> 419 420 #define APIC_DFR_VALUE (APIC_DFR_FLAT) 421 422 static inline const struct cpumask *default_target_cpus(void) 423 { 424 #ifdef CONFIG_SMP 425 return cpu_online_mask; 426 #else 427 return cpumask_of(0); 428 #endif 429 } 430 431 DECLARE_EARLY_PER_CPU(u16, x86_bios_cpu_apicid); 432 433 434 static inline unsigned int read_apic_id(void) 435 { 436 unsigned int reg; 437 438 reg = apic_read(APIC_ID); 439 440 return apic->get_apic_id(reg); 441 } 442 443 extern void default_setup_apic_routing(void); 444 445 #ifdef CONFIG_X86_32 446 /* 447 * Set up the logical destination ID. 448 * 449 * Intel recommends to set DFR, LDR and TPR before enabling 450 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel 451 * document number 292116). So here it goes... 452 */ 453 extern void default_init_apic_ldr(void); 454 455 static inline int default_apic_id_registered(void) 456 { 457 return physid_isset(read_apic_id(), phys_cpu_present_map); 458 } 459 460 static inline unsigned int 461 default_cpu_mask_to_apicid(const struct cpumask *cpumask) 462 { 463 return cpumask_bits(cpumask)[0]; 464 } 465 466 static inline unsigned int 467 default_cpu_mask_to_apicid_and(const struct cpumask *cpumask, 468 const struct cpumask *andmask) 469 { 470 unsigned long mask1 = cpumask_bits(cpumask)[0]; 471 unsigned long mask2 = cpumask_bits(andmask)[0]; 472 unsigned long mask3 = cpumask_bits(cpu_online_mask)[0]; 473 474 return (unsigned int)(mask1 & mask2 & mask3); 475 } 476 477 static inline int default_phys_pkg_id(int cpuid_apic, int index_msb) 478 { 479 return cpuid_apic >> index_msb; 480 } 481 482 extern int default_apicid_to_node(int logical_apicid); 483 484 #endif 485 486 static inline unsigned long default_check_apicid_used(physid_mask_t bitmap, int apicid) 487 { 488 return physid_isset(apicid, bitmap); 489 } 490 491 static inline unsigned long default_check_apicid_present(int bit) 492 { 493 return physid_isset(bit, phys_cpu_present_map); 494 } 495 496 static inline physid_mask_t default_ioapic_phys_id_map(physid_mask_t phys_map) 497 { 498 return phys_map; 499 } 500 501 /* Mapping from cpu number to logical apicid */ 502 static inline int default_cpu_to_logical_apicid(int cpu) 503 { 504 return 1 << cpu; 505 } 506 507 static inline int __default_cpu_present_to_apicid(int mps_cpu) 508 { 509 if (mps_cpu < nr_cpu_ids && cpu_present(mps_cpu)) 510 return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu); 511 else 512 return BAD_APICID; 513 } 514 515 static inline int 516 __default_check_phys_apicid_present(int boot_cpu_physical_apicid) 517 { 518 return physid_isset(boot_cpu_physical_apicid, phys_cpu_present_map); 519 } 520 521 #ifdef CONFIG_X86_32 522 static inline int default_cpu_present_to_apicid(int mps_cpu) 523 { 524 return __default_cpu_present_to_apicid(mps_cpu); 525 } 526 527 static inline int 528 default_check_phys_apicid_present(int boot_cpu_physical_apicid) 529 { 530 return __default_check_phys_apicid_present(boot_cpu_physical_apicid); 531 } 532 #else 533 extern int default_cpu_present_to_apicid(int mps_cpu); 534 extern int default_check_phys_apicid_present(int boot_cpu_physical_apicid); 535 #endif 536 537 static inline physid_mask_t default_apicid_to_cpu_present(int phys_apicid) 538 { 539 return physid_mask_of_physid(phys_apicid); 540 } 541 542 #endif /* CONFIG_X86_LOCAL_APIC */ 543 544 #endif /* _ASM_X86_APIC_H */ 545