1 #ifndef _ASM_X86_APIC_H 2 #define _ASM_X86_APIC_H 3 4 #include <linux/cpumask.h> 5 #include <linux/pm.h> 6 7 #include <asm/alternative.h> 8 #include <asm/cpufeature.h> 9 #include <asm/processor.h> 10 #include <asm/apicdef.h> 11 #include <linux/atomic.h> 12 #include <asm/fixmap.h> 13 #include <asm/mpspec.h> 14 #include <asm/msr.h> 15 #include <asm/idle.h> 16 17 #define ARCH_APICTIMER_STOPS_ON_C3 1 18 19 /* 20 * Debugging macros 21 */ 22 #define APIC_QUIET 0 23 #define APIC_VERBOSE 1 24 #define APIC_DEBUG 2 25 26 /* 27 * Define the default level of output to be very little 28 * This can be turned up by using apic=verbose for more 29 * information and apic=debug for _lots_ of information. 30 * apic_verbosity is defined in apic.c 31 */ 32 #define apic_printk(v, s, a...) do { \ 33 if ((v) <= apic_verbosity) \ 34 printk(s, ##a); \ 35 } while (0) 36 37 38 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32) 39 extern void generic_apic_probe(void); 40 #else 41 static inline void generic_apic_probe(void) 42 { 43 } 44 #endif 45 46 #ifdef CONFIG_X86_LOCAL_APIC 47 48 extern unsigned int apic_verbosity; 49 extern int local_apic_timer_c2_ok; 50 51 extern int disable_apic; 52 extern unsigned int lapic_timer_frequency; 53 54 #ifdef CONFIG_SMP 55 extern void __inquire_remote_apic(int apicid); 56 #else /* CONFIG_SMP */ 57 static inline void __inquire_remote_apic(int apicid) 58 { 59 } 60 #endif /* CONFIG_SMP */ 61 62 static inline void default_inquire_remote_apic(int apicid) 63 { 64 if (apic_verbosity >= APIC_DEBUG) 65 __inquire_remote_apic(apicid); 66 } 67 68 /* 69 * With 82489DX we can't rely on apic feature bit 70 * retrieved via cpuid but still have to deal with 71 * such an apic chip so we assume that SMP configuration 72 * is found from MP table (64bit case uses ACPI mostly 73 * which set smp presence flag as well so we are safe 74 * to use this helper too). 75 */ 76 static inline bool apic_from_smp_config(void) 77 { 78 return smp_found_config && !disable_apic; 79 } 80 81 /* 82 * Basic functions accessing APICs. 83 */ 84 #ifdef CONFIG_PARAVIRT 85 #include <asm/paravirt.h> 86 #endif 87 88 extern int setup_profiling_timer(unsigned int); 89 90 static inline void native_apic_mem_write(u32 reg, u32 v) 91 { 92 volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg); 93 94 alternative_io("movl %0, %P1", "xchgl %0, %P1", X86_BUG_11AP, 95 ASM_OUTPUT2("=r" (v), "=m" (*addr)), 96 ASM_OUTPUT2("0" (v), "m" (*addr))); 97 } 98 99 static inline u32 native_apic_mem_read(u32 reg) 100 { 101 return *((volatile u32 *)(APIC_BASE + reg)); 102 } 103 104 extern void native_apic_wait_icr_idle(void); 105 extern u32 native_safe_apic_wait_icr_idle(void); 106 extern void native_apic_icr_write(u32 low, u32 id); 107 extern u64 native_apic_icr_read(void); 108 109 static inline bool apic_is_x2apic_enabled(void) 110 { 111 u64 msr; 112 113 if (rdmsrl_safe(MSR_IA32_APICBASE, &msr)) 114 return false; 115 return msr & X2APIC_ENABLE; 116 } 117 118 extern void enable_IR_x2apic(void); 119 120 extern int get_physical_broadcast(void); 121 122 extern int lapic_get_maxlvt(void); 123 extern void clear_local_APIC(void); 124 extern void disconnect_bsp_APIC(int virt_wire_setup); 125 extern void disable_local_APIC(void); 126 extern void lapic_shutdown(void); 127 extern void sync_Arb_IDs(void); 128 extern void init_bsp_APIC(void); 129 extern void setup_local_APIC(void); 130 extern void init_apic_mappings(void); 131 void register_lapic_address(unsigned long address); 132 extern void setup_boot_APIC_clock(void); 133 extern void setup_secondary_APIC_clock(void); 134 extern int APIC_init_uniprocessor(void); 135 136 #ifdef CONFIG_X86_64 137 static inline int apic_force_enable(unsigned long addr) 138 { 139 return -1; 140 } 141 #else 142 extern int apic_force_enable(unsigned long addr); 143 #endif 144 145 extern int apic_bsp_setup(bool upmode); 146 extern void apic_ap_setup(void); 147 148 /* 149 * On 32bit this is mach-xxx local 150 */ 151 #ifdef CONFIG_X86_64 152 extern int apic_is_clustered_box(void); 153 #else 154 static inline int apic_is_clustered_box(void) 155 { 156 return 0; 157 } 158 #endif 159 160 extern int setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask); 161 162 #else /* !CONFIG_X86_LOCAL_APIC */ 163 static inline void lapic_shutdown(void) { } 164 #define local_apic_timer_c2_ok 1 165 static inline void init_apic_mappings(void) { } 166 static inline void disable_local_APIC(void) { } 167 # define setup_boot_APIC_clock x86_init_noop 168 # define setup_secondary_APIC_clock x86_init_noop 169 #endif /* !CONFIG_X86_LOCAL_APIC */ 170 171 #ifdef CONFIG_X86_X2APIC 172 /* 173 * Make previous memory operations globally visible before 174 * sending the IPI through x2apic wrmsr. We need a serializing instruction or 175 * mfence for this. 176 */ 177 static inline void x2apic_wrmsr_fence(void) 178 { 179 asm volatile("mfence" : : : "memory"); 180 } 181 182 static inline void native_apic_msr_write(u32 reg, u32 v) 183 { 184 if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR || 185 reg == APIC_LVR) 186 return; 187 188 wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0); 189 } 190 191 static inline void native_apic_msr_eoi_write(u32 reg, u32 v) 192 { 193 wrmsr(APIC_BASE_MSR + (APIC_EOI >> 4), APIC_EOI_ACK, 0); 194 } 195 196 static inline u32 native_apic_msr_read(u32 reg) 197 { 198 u64 msr; 199 200 if (reg == APIC_DFR) 201 return -1; 202 203 rdmsrl(APIC_BASE_MSR + (reg >> 4), msr); 204 return (u32)msr; 205 } 206 207 static inline void native_x2apic_wait_icr_idle(void) 208 { 209 /* no need to wait for icr idle in x2apic */ 210 return; 211 } 212 213 static inline u32 native_safe_x2apic_wait_icr_idle(void) 214 { 215 /* no need to wait for icr idle in x2apic */ 216 return 0; 217 } 218 219 static inline void native_x2apic_icr_write(u32 low, u32 id) 220 { 221 wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low); 222 } 223 224 static inline u64 native_x2apic_icr_read(void) 225 { 226 unsigned long val; 227 228 rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val); 229 return val; 230 } 231 232 extern int x2apic_mode; 233 extern int x2apic_phys; 234 extern void __init check_x2apic(void); 235 extern void x2apic_setup(void); 236 static inline int x2apic_enabled(void) 237 { 238 return cpu_has_x2apic && apic_is_x2apic_enabled(); 239 } 240 241 #define x2apic_supported() (cpu_has_x2apic) 242 #else /* !CONFIG_X86_X2APIC */ 243 static inline void check_x2apic(void) { } 244 static inline void x2apic_setup(void) { } 245 static inline int x2apic_enabled(void) { return 0; } 246 247 #define x2apic_mode (0) 248 #define x2apic_supported() (0) 249 #endif /* !CONFIG_X86_X2APIC */ 250 251 #ifdef CONFIG_X86_64 252 #define SET_APIC_ID(x) (apic->set_apic_id(x)) 253 #else 254 255 #endif 256 257 /* 258 * Copyright 2004 James Cleverdon, IBM. 259 * Subject to the GNU Public License, v.2 260 * 261 * Generic APIC sub-arch data struct. 262 * 263 * Hacked for x86-64 by James Cleverdon from i386 architecture code by 264 * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and 265 * James Cleverdon. 266 */ 267 struct apic { 268 char *name; 269 270 int (*probe)(void); 271 int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id); 272 int (*apic_id_valid)(int apicid); 273 int (*apic_id_registered)(void); 274 275 u32 irq_delivery_mode; 276 u32 irq_dest_mode; 277 278 const struct cpumask *(*target_cpus)(void); 279 280 int disable_esr; 281 282 int dest_logical; 283 unsigned long (*check_apicid_used)(physid_mask_t *map, int apicid); 284 285 void (*vector_allocation_domain)(int cpu, struct cpumask *retmask, 286 const struct cpumask *mask); 287 void (*init_apic_ldr)(void); 288 289 void (*ioapic_phys_id_map)(physid_mask_t *phys_map, physid_mask_t *retmap); 290 291 void (*setup_apic_routing)(void); 292 int (*cpu_present_to_apicid)(int mps_cpu); 293 void (*apicid_to_cpu_present)(int phys_apicid, physid_mask_t *retmap); 294 int (*check_phys_apicid_present)(int phys_apicid); 295 int (*phys_pkg_id)(int cpuid_apic, int index_msb); 296 297 unsigned int (*get_apic_id)(unsigned long x); 298 unsigned long (*set_apic_id)(unsigned int id); 299 unsigned long apic_id_mask; 300 301 int (*cpu_mask_to_apicid_and)(const struct cpumask *cpumask, 302 const struct cpumask *andmask, 303 unsigned int *apicid); 304 305 /* ipi */ 306 void (*send_IPI_mask)(const struct cpumask *mask, int vector); 307 void (*send_IPI_mask_allbutself)(const struct cpumask *mask, 308 int vector); 309 void (*send_IPI_allbutself)(int vector); 310 void (*send_IPI_all)(int vector); 311 void (*send_IPI_self)(int vector); 312 313 /* wakeup_secondary_cpu */ 314 int (*wakeup_secondary_cpu)(int apicid, unsigned long start_eip); 315 316 void (*inquire_remote_apic)(int apicid); 317 318 /* apic ops */ 319 u32 (*read)(u32 reg); 320 void (*write)(u32 reg, u32 v); 321 /* 322 * ->eoi_write() has the same signature as ->write(). 323 * 324 * Drivers can support both ->eoi_write() and ->write() by passing the same 325 * callback value. Kernel can override ->eoi_write() and fall back 326 * on write for EOI. 327 */ 328 void (*eoi_write)(u32 reg, u32 v); 329 u64 (*icr_read)(void); 330 void (*icr_write)(u32 low, u32 high); 331 void (*wait_icr_idle)(void); 332 u32 (*safe_wait_icr_idle)(void); 333 334 #ifdef CONFIG_X86_32 335 /* 336 * Called very early during boot from get_smp_config(). It should 337 * return the logical apicid. x86_[bios]_cpu_to_apicid is 338 * initialized before this function is called. 339 * 340 * If logical apicid can't be determined that early, the function 341 * may return BAD_APICID. Logical apicid will be configured after 342 * init_apic_ldr() while bringing up CPUs. Note that NUMA affinity 343 * won't be applied properly during early boot in this case. 344 */ 345 int (*x86_32_early_logical_apicid)(int cpu); 346 #endif 347 }; 348 349 /* 350 * Pointer to the local APIC driver in use on this system (there's 351 * always just one such driver in use - the kernel decides via an 352 * early probing process which one it picks - and then sticks to it): 353 */ 354 extern struct apic *apic; 355 356 /* 357 * APIC drivers are probed based on how they are listed in the .apicdrivers 358 * section. So the order is important and enforced by the ordering 359 * of different apic driver files in the Makefile. 360 * 361 * For the files having two apic drivers, we use apic_drivers() 362 * to enforce the order with in them. 363 */ 364 #define apic_driver(sym) \ 365 static const struct apic *__apicdrivers_##sym __used \ 366 __aligned(sizeof(struct apic *)) \ 367 __section(.apicdrivers) = { &sym } 368 369 #define apic_drivers(sym1, sym2) \ 370 static struct apic *__apicdrivers_##sym1##sym2[2] __used \ 371 __aligned(sizeof(struct apic *)) \ 372 __section(.apicdrivers) = { &sym1, &sym2 } 373 374 extern struct apic *__apicdrivers[], *__apicdrivers_end[]; 375 376 /* 377 * APIC functionality to boot other CPUs - only used on SMP: 378 */ 379 #ifdef CONFIG_SMP 380 extern int wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip); 381 #endif 382 383 #ifdef CONFIG_X86_LOCAL_APIC 384 385 static inline u32 apic_read(u32 reg) 386 { 387 return apic->read(reg); 388 } 389 390 static inline void apic_write(u32 reg, u32 val) 391 { 392 apic->write(reg, val); 393 } 394 395 static inline void apic_eoi(void) 396 { 397 apic->eoi_write(APIC_EOI, APIC_EOI_ACK); 398 } 399 400 static inline u64 apic_icr_read(void) 401 { 402 return apic->icr_read(); 403 } 404 405 static inline void apic_icr_write(u32 low, u32 high) 406 { 407 apic->icr_write(low, high); 408 } 409 410 static inline void apic_wait_icr_idle(void) 411 { 412 apic->wait_icr_idle(); 413 } 414 415 static inline u32 safe_apic_wait_icr_idle(void) 416 { 417 return apic->safe_wait_icr_idle(); 418 } 419 420 extern void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)); 421 422 #else /* CONFIG_X86_LOCAL_APIC */ 423 424 static inline u32 apic_read(u32 reg) { return 0; } 425 static inline void apic_write(u32 reg, u32 val) { } 426 static inline void apic_eoi(void) { } 427 static inline u64 apic_icr_read(void) { return 0; } 428 static inline void apic_icr_write(u32 low, u32 high) { } 429 static inline void apic_wait_icr_idle(void) { } 430 static inline u32 safe_apic_wait_icr_idle(void) { return 0; } 431 static inline void apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) {} 432 433 #endif /* CONFIG_X86_LOCAL_APIC */ 434 435 static inline void ack_APIC_irq(void) 436 { 437 /* 438 * ack_APIC_irq() actually gets compiled as a single instruction 439 * ... yummie. 440 */ 441 apic_eoi(); 442 } 443 444 static inline unsigned default_get_apic_id(unsigned long x) 445 { 446 unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR)); 447 448 if (APIC_XAPIC(ver) || boot_cpu_has(X86_FEATURE_EXTD_APICID)) 449 return (x >> 24) & 0xFF; 450 else 451 return (x >> 24) & 0x0F; 452 } 453 454 /* 455 * Warm reset vector position: 456 */ 457 #define TRAMPOLINE_PHYS_LOW 0x467 458 #define TRAMPOLINE_PHYS_HIGH 0x469 459 460 #ifdef CONFIG_X86_64 461 extern void apic_send_IPI_self(int vector); 462 463 DECLARE_PER_CPU(int, x2apic_extra_bits); 464 465 extern int default_cpu_present_to_apicid(int mps_cpu); 466 extern int default_check_phys_apicid_present(int phys_apicid); 467 #endif 468 469 extern void generic_bigsmp_probe(void); 470 471 472 #ifdef CONFIG_X86_LOCAL_APIC 473 474 #include <asm/smp.h> 475 476 #define APIC_DFR_VALUE (APIC_DFR_FLAT) 477 478 static inline const struct cpumask *default_target_cpus(void) 479 { 480 #ifdef CONFIG_SMP 481 return cpu_online_mask; 482 #else 483 return cpumask_of(0); 484 #endif 485 } 486 487 static inline const struct cpumask *online_target_cpus(void) 488 { 489 return cpu_online_mask; 490 } 491 492 DECLARE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid); 493 494 495 static inline unsigned int read_apic_id(void) 496 { 497 unsigned int reg; 498 499 reg = apic_read(APIC_ID); 500 501 return apic->get_apic_id(reg); 502 } 503 504 static inline int default_apic_id_valid(int apicid) 505 { 506 return (apicid < 255); 507 } 508 509 extern int default_acpi_madt_oem_check(char *, char *); 510 511 extern void default_setup_apic_routing(void); 512 513 extern struct apic apic_noop; 514 515 #ifdef CONFIG_X86_32 516 517 static inline int noop_x86_32_early_logical_apicid(int cpu) 518 { 519 return BAD_APICID; 520 } 521 522 /* 523 * Set up the logical destination ID. 524 * 525 * Intel recommends to set DFR, LDR and TPR before enabling 526 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel 527 * document number 292116). So here it goes... 528 */ 529 extern void default_init_apic_ldr(void); 530 531 static inline int default_apic_id_registered(void) 532 { 533 return physid_isset(read_apic_id(), phys_cpu_present_map); 534 } 535 536 static inline int default_phys_pkg_id(int cpuid_apic, int index_msb) 537 { 538 return cpuid_apic >> index_msb; 539 } 540 541 #endif 542 543 static inline int 544 flat_cpu_mask_to_apicid_and(const struct cpumask *cpumask, 545 const struct cpumask *andmask, 546 unsigned int *apicid) 547 { 548 unsigned long cpu_mask = cpumask_bits(cpumask)[0] & 549 cpumask_bits(andmask)[0] & 550 cpumask_bits(cpu_online_mask)[0] & 551 APIC_ALL_CPUS; 552 553 if (likely(cpu_mask)) { 554 *apicid = (unsigned int)cpu_mask; 555 return 0; 556 } else { 557 return -EINVAL; 558 } 559 } 560 561 extern int 562 default_cpu_mask_to_apicid_and(const struct cpumask *cpumask, 563 const struct cpumask *andmask, 564 unsigned int *apicid); 565 566 static inline void 567 flat_vector_allocation_domain(int cpu, struct cpumask *retmask, 568 const struct cpumask *mask) 569 { 570 /* Careful. Some cpus do not strictly honor the set of cpus 571 * specified in the interrupt destination when using lowest 572 * priority interrupt delivery mode. 573 * 574 * In particular there was a hyperthreading cpu observed to 575 * deliver interrupts to the wrong hyperthread when only one 576 * hyperthread was specified in the interrupt desitination. 577 */ 578 cpumask_clear(retmask); 579 cpumask_bits(retmask)[0] = APIC_ALL_CPUS; 580 } 581 582 static inline void 583 default_vector_allocation_domain(int cpu, struct cpumask *retmask, 584 const struct cpumask *mask) 585 { 586 cpumask_copy(retmask, cpumask_of(cpu)); 587 } 588 589 static inline unsigned long default_check_apicid_used(physid_mask_t *map, int apicid) 590 { 591 return physid_isset(apicid, *map); 592 } 593 594 static inline void default_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mask_t *retmap) 595 { 596 *retmap = *phys_map; 597 } 598 599 static inline int __default_cpu_present_to_apicid(int mps_cpu) 600 { 601 if (mps_cpu < nr_cpu_ids && cpu_present(mps_cpu)) 602 return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu); 603 else 604 return BAD_APICID; 605 } 606 607 static inline int 608 __default_check_phys_apicid_present(int phys_apicid) 609 { 610 return physid_isset(phys_apicid, phys_cpu_present_map); 611 } 612 613 #ifdef CONFIG_X86_32 614 static inline int default_cpu_present_to_apicid(int mps_cpu) 615 { 616 return __default_cpu_present_to_apicid(mps_cpu); 617 } 618 619 static inline int 620 default_check_phys_apicid_present(int phys_apicid) 621 { 622 return __default_check_phys_apicid_present(phys_apicid); 623 } 624 #else 625 extern int default_cpu_present_to_apicid(int mps_cpu); 626 extern int default_check_phys_apicid_present(int phys_apicid); 627 #endif 628 629 #endif /* CONFIG_X86_LOCAL_APIC */ 630 extern void irq_enter(void); 631 extern void irq_exit(void); 632 633 static inline void entering_irq(void) 634 { 635 irq_enter(); 636 exit_idle(); 637 } 638 639 static inline void entering_ack_irq(void) 640 { 641 ack_APIC_irq(); 642 entering_irq(); 643 } 644 645 static inline void ipi_entering_ack_irq(void) 646 { 647 ack_APIC_irq(); 648 irq_enter(); 649 } 650 651 static inline void exiting_irq(void) 652 { 653 irq_exit(); 654 } 655 656 static inline void exiting_ack_irq(void) 657 { 658 irq_exit(); 659 /* Ack only at the end to avoid potential reentry */ 660 ack_APIC_irq(); 661 } 662 663 extern void ioapic_zap_locks(void); 664 665 #endif /* _ASM_X86_APIC_H */ 666