1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 #ifndef _ASM_X86_APIC_H 3 #define _ASM_X86_APIC_H 4 5 #include <linux/cpumask.h> 6 7 #include <asm/alternative.h> 8 #include <asm/cpufeature.h> 9 #include <asm/apicdef.h> 10 #include <linux/atomic.h> 11 #include <asm/fixmap.h> 12 #include <asm/mpspec.h> 13 #include <asm/msr.h> 14 #include <asm/hardirq.h> 15 16 #define ARCH_APICTIMER_STOPS_ON_C3 1 17 18 /* 19 * Debugging macros 20 */ 21 #define APIC_QUIET 0 22 #define APIC_VERBOSE 1 23 #define APIC_DEBUG 2 24 25 /* Macros for apic_extnmi which controls external NMI masking */ 26 #define APIC_EXTNMI_BSP 0 /* Default */ 27 #define APIC_EXTNMI_ALL 1 28 #define APIC_EXTNMI_NONE 2 29 30 /* 31 * Define the default level of output to be very little 32 * This can be turned up by using apic=verbose for more 33 * information and apic=debug for _lots_ of information. 34 * apic_verbosity is defined in apic.c 35 */ 36 #define apic_printk(v, s, a...) do { \ 37 if ((v) <= apic_verbosity) \ 38 printk(s, ##a); \ 39 } while (0) 40 41 42 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32) 43 extern void generic_apic_probe(void); 44 #else 45 static inline void generic_apic_probe(void) 46 { 47 } 48 #endif 49 50 #ifdef CONFIG_X86_LOCAL_APIC 51 52 extern int apic_verbosity; 53 extern int local_apic_timer_c2_ok; 54 55 extern bool apic_is_disabled; 56 extern unsigned int lapic_timer_period; 57 58 extern int cpuid_to_apicid[]; 59 60 extern enum apic_intr_mode_id apic_intr_mode; 61 enum apic_intr_mode_id { 62 APIC_PIC, 63 APIC_VIRTUAL_WIRE, 64 APIC_VIRTUAL_WIRE_NO_CONFIG, 65 APIC_SYMMETRIC_IO, 66 APIC_SYMMETRIC_IO_NO_ROUTING 67 }; 68 69 /* 70 * With 82489DX we can't rely on apic feature bit 71 * retrieved via cpuid but still have to deal with 72 * such an apic chip so we assume that SMP configuration 73 * is found from MP table (64bit case uses ACPI mostly 74 * which set smp presence flag as well so we are safe 75 * to use this helper too). 76 */ 77 static inline bool apic_from_smp_config(void) 78 { 79 return smp_found_config && !apic_is_disabled; 80 } 81 82 /* 83 * Basic functions accessing APICs. 84 */ 85 #ifdef CONFIG_PARAVIRT 86 #include <asm/paravirt.h> 87 #endif 88 89 static inline void native_apic_mem_write(u32 reg, u32 v) 90 { 91 volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg); 92 93 alternative_io("movl %0, %P1", "xchgl %0, %P1", X86_BUG_11AP, 94 ASM_OUTPUT2("=r" (v), "=m" (*addr)), 95 ASM_OUTPUT2("0" (v), "m" (*addr))); 96 } 97 98 static inline u32 native_apic_mem_read(u32 reg) 99 { 100 return *((volatile u32 *)(APIC_BASE + reg)); 101 } 102 103 extern void native_apic_wait_icr_idle(void); 104 extern u32 native_safe_apic_wait_icr_idle(void); 105 extern void native_apic_icr_write(u32 low, u32 id); 106 extern u64 native_apic_icr_read(void); 107 108 static inline bool apic_is_x2apic_enabled(void) 109 { 110 u64 msr; 111 112 if (rdmsrl_safe(MSR_IA32_APICBASE, &msr)) 113 return false; 114 return msr & X2APIC_ENABLE; 115 } 116 117 extern void enable_IR_x2apic(void); 118 119 extern int get_physical_broadcast(void); 120 121 extern int lapic_get_maxlvt(void); 122 extern void clear_local_APIC(void); 123 extern void disconnect_bsp_APIC(int virt_wire_setup); 124 extern void disable_local_APIC(void); 125 extern void apic_soft_disable(void); 126 extern void lapic_shutdown(void); 127 extern void sync_Arb_IDs(void); 128 extern void init_bsp_APIC(void); 129 extern void apic_intr_mode_select(void); 130 extern void apic_intr_mode_init(void); 131 extern void init_apic_mappings(void); 132 void register_lapic_address(unsigned long address); 133 extern void setup_boot_APIC_clock(void); 134 extern void setup_secondary_APIC_clock(void); 135 extern void lapic_update_tsc_freq(void); 136 137 #ifdef CONFIG_X86_64 138 static inline bool apic_force_enable(unsigned long addr) 139 { 140 return false; 141 } 142 #else 143 extern bool apic_force_enable(unsigned long addr); 144 #endif 145 146 extern void apic_ap_setup(void); 147 148 /* 149 * On 32bit this is mach-xxx local 150 */ 151 #ifdef CONFIG_X86_64 152 extern int apic_is_clustered_box(void); 153 #else 154 static inline int apic_is_clustered_box(void) 155 { 156 return 0; 157 } 158 #endif 159 160 extern int setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask); 161 extern void lapic_assign_system_vectors(void); 162 extern void lapic_assign_legacy_vector(unsigned int isairq, bool replace); 163 extern void lapic_update_legacy_vectors(void); 164 extern void lapic_online(void); 165 extern void lapic_offline(void); 166 extern bool apic_needs_pit(void); 167 168 extern void apic_send_IPI_allbutself(unsigned int vector); 169 170 #else /* !CONFIG_X86_LOCAL_APIC */ 171 static inline void lapic_shutdown(void) { } 172 #define local_apic_timer_c2_ok 1 173 static inline void init_apic_mappings(void) { } 174 static inline void disable_local_APIC(void) { } 175 # define setup_boot_APIC_clock x86_init_noop 176 # define setup_secondary_APIC_clock x86_init_noop 177 static inline void lapic_update_tsc_freq(void) { } 178 static inline void init_bsp_APIC(void) { } 179 static inline void apic_intr_mode_select(void) { } 180 static inline void apic_intr_mode_init(void) { } 181 static inline void lapic_assign_system_vectors(void) { } 182 static inline void lapic_assign_legacy_vector(unsigned int i, bool r) { } 183 static inline bool apic_needs_pit(void) { return true; } 184 #endif /* !CONFIG_X86_LOCAL_APIC */ 185 186 #ifdef CONFIG_X86_X2APIC 187 static inline void native_apic_msr_write(u32 reg, u32 v) 188 { 189 if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR || 190 reg == APIC_LVR) 191 return; 192 193 wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0); 194 } 195 196 static inline void native_apic_msr_eoi_write(u32 reg, u32 v) 197 { 198 __wrmsr(APIC_BASE_MSR + (APIC_EOI >> 4), APIC_EOI_ACK, 0); 199 } 200 201 static inline u32 native_apic_msr_read(u32 reg) 202 { 203 u64 msr; 204 205 if (reg == APIC_DFR) 206 return -1; 207 208 rdmsrl(APIC_BASE_MSR + (reg >> 4), msr); 209 return (u32)msr; 210 } 211 212 static inline void native_x2apic_wait_icr_idle(void) 213 { 214 /* no need to wait for icr idle in x2apic */ 215 return; 216 } 217 218 static inline u32 native_safe_x2apic_wait_icr_idle(void) 219 { 220 /* no need to wait for icr idle in x2apic */ 221 return 0; 222 } 223 224 static inline void native_x2apic_icr_write(u32 low, u32 id) 225 { 226 wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low); 227 } 228 229 static inline u64 native_x2apic_icr_read(void) 230 { 231 unsigned long val; 232 233 rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val); 234 return val; 235 } 236 237 extern int x2apic_mode; 238 extern int x2apic_phys; 239 extern void __init x2apic_set_max_apicid(u32 apicid); 240 extern void x2apic_setup(void); 241 static inline int x2apic_enabled(void) 242 { 243 return boot_cpu_has(X86_FEATURE_X2APIC) && apic_is_x2apic_enabled(); 244 } 245 246 #define x2apic_supported() (boot_cpu_has(X86_FEATURE_X2APIC)) 247 #else /* !CONFIG_X86_X2APIC */ 248 static inline void x2apic_setup(void) { } 249 static inline int x2apic_enabled(void) { return 0; } 250 static inline u32 native_apic_msr_read(u32 reg) { BUG(); } 251 #define x2apic_mode (0) 252 #define x2apic_supported() (0) 253 #endif /* !CONFIG_X86_X2APIC */ 254 extern void __init check_x2apic(void); 255 256 struct irq_data; 257 258 /* 259 * Copyright 2004 James Cleverdon, IBM. 260 * 261 * Generic APIC sub-arch data struct. 262 * 263 * Hacked for x86-64 by James Cleverdon from i386 architecture code by 264 * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and 265 * James Cleverdon. 266 */ 267 struct apic { 268 /* Hotpath functions first */ 269 void (*eoi_write)(u32 reg, u32 v); 270 void (*native_eoi_write)(u32 reg, u32 v); 271 void (*write)(u32 reg, u32 v); 272 u32 (*read)(u32 reg); 273 274 /* IPI related functions */ 275 void (*wait_icr_idle)(void); 276 u32 (*safe_wait_icr_idle)(void); 277 278 void (*send_IPI)(int cpu, int vector); 279 void (*send_IPI_mask)(const struct cpumask *mask, int vector); 280 void (*send_IPI_mask_allbutself)(const struct cpumask *msk, int vec); 281 void (*send_IPI_allbutself)(int vector); 282 void (*send_IPI_all)(int vector); 283 void (*send_IPI_self)(int vector); 284 285 u32 disable_esr; 286 287 enum apic_delivery_modes delivery_mode; 288 bool dest_mode_logical; 289 290 u32 (*calc_dest_apicid)(unsigned int cpu); 291 292 /* ICR related functions */ 293 u64 (*icr_read)(void); 294 void (*icr_write)(u32 low, u32 high); 295 296 /* Probe, setup and smpboot functions */ 297 int (*probe)(void); 298 int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id); 299 int (*apic_id_valid)(u32 apicid); 300 int (*apic_id_registered)(void); 301 302 bool (*check_apicid_used)(physid_mask_t *map, int apicid); 303 void (*init_apic_ldr)(void); 304 void (*ioapic_phys_id_map)(physid_mask_t *phys_map, physid_mask_t *retmap); 305 void (*setup_apic_routing)(void); 306 int (*cpu_present_to_apicid)(int mps_cpu); 307 void (*apicid_to_cpu_present)(int phys_apicid, physid_mask_t *retmap); 308 int (*phys_pkg_id)(int cpuid_apic, int index_msb); 309 310 u32 (*get_apic_id)(unsigned long x); 311 u32 (*set_apic_id)(unsigned int id); 312 313 /* wakeup_secondary_cpu */ 314 int (*wakeup_secondary_cpu)(int apicid, unsigned long start_eip); 315 /* wakeup secondary CPU using 64-bit wakeup point */ 316 int (*wakeup_secondary_cpu_64)(int apicid, unsigned long start_eip); 317 318 char *name; 319 }; 320 321 /* 322 * Pointer to the local APIC driver in use on this system (there's 323 * always just one such driver in use - the kernel decides via an 324 * early probing process which one it picks - and then sticks to it): 325 */ 326 extern struct apic *apic; 327 328 /* 329 * APIC drivers are probed based on how they are listed in the .apicdrivers 330 * section. So the order is important and enforced by the ordering 331 * of different apic driver files in the Makefile. 332 * 333 * For the files having two apic drivers, we use apic_drivers() 334 * to enforce the order with in them. 335 */ 336 #define apic_driver(sym) \ 337 static const struct apic *__apicdrivers_##sym __used \ 338 __aligned(sizeof(struct apic *)) \ 339 __section(".apicdrivers") = { &sym } 340 341 #define apic_drivers(sym1, sym2) \ 342 static struct apic *__apicdrivers_##sym1##sym2[2] __used \ 343 __aligned(sizeof(struct apic *)) \ 344 __section(".apicdrivers") = { &sym1, &sym2 } 345 346 extern struct apic *__apicdrivers[], *__apicdrivers_end[]; 347 348 /* 349 * APIC functionality to boot other CPUs - only used on SMP: 350 */ 351 #ifdef CONFIG_SMP 352 extern int lapic_can_unplug_cpu(void); 353 #endif 354 355 #ifdef CONFIG_X86_LOCAL_APIC 356 357 static inline u32 apic_read(u32 reg) 358 { 359 return apic->read(reg); 360 } 361 362 static inline void apic_write(u32 reg, u32 val) 363 { 364 apic->write(reg, val); 365 } 366 367 static inline void apic_eoi(void) 368 { 369 apic->eoi_write(APIC_EOI, APIC_EOI_ACK); 370 } 371 372 static inline u64 apic_icr_read(void) 373 { 374 return apic->icr_read(); 375 } 376 377 static inline void apic_icr_write(u32 low, u32 high) 378 { 379 apic->icr_write(low, high); 380 } 381 382 static inline void apic_wait_icr_idle(void) 383 { 384 apic->wait_icr_idle(); 385 } 386 387 static inline u32 safe_apic_wait_icr_idle(void) 388 { 389 return apic->safe_wait_icr_idle(); 390 } 391 392 extern void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)); 393 394 #else /* CONFIG_X86_LOCAL_APIC */ 395 396 static inline u32 apic_read(u32 reg) { return 0; } 397 static inline void apic_write(u32 reg, u32 val) { } 398 static inline void apic_eoi(void) { } 399 static inline u64 apic_icr_read(void) { return 0; } 400 static inline void apic_icr_write(u32 low, u32 high) { } 401 static inline void apic_wait_icr_idle(void) { } 402 static inline u32 safe_apic_wait_icr_idle(void) { return 0; } 403 static inline void apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) {} 404 405 #endif /* CONFIG_X86_LOCAL_APIC */ 406 407 extern void apic_ack_irq(struct irq_data *data); 408 409 static inline void ack_APIC_irq(void) 410 { 411 /* 412 * ack_APIC_irq() actually gets compiled as a single instruction 413 * ... yummie. 414 */ 415 apic_eoi(); 416 } 417 418 419 static inline bool lapic_vector_set_in_irr(unsigned int vector) 420 { 421 u32 irr = apic_read(APIC_IRR + (vector / 32 * 0x10)); 422 423 return !!(irr & (1U << (vector % 32))); 424 } 425 426 static inline unsigned default_get_apic_id(unsigned long x) 427 { 428 unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR)); 429 430 if (APIC_XAPIC(ver) || boot_cpu_has(X86_FEATURE_EXTD_APICID)) 431 return (x >> 24) & 0xFF; 432 else 433 return (x >> 24) & 0x0F; 434 } 435 436 /* 437 * Warm reset vector position: 438 */ 439 #define TRAMPOLINE_PHYS_LOW 0x467 440 #define TRAMPOLINE_PHYS_HIGH 0x469 441 442 extern void generic_bigsmp_probe(void); 443 444 #ifdef CONFIG_X86_LOCAL_APIC 445 446 #include <asm/smp.h> 447 448 #define APIC_DFR_VALUE (APIC_DFR_FLAT) 449 450 extern struct apic apic_noop; 451 452 static inline unsigned int read_apic_id(void) 453 { 454 unsigned int reg = apic_read(APIC_ID); 455 456 return apic->get_apic_id(reg); 457 } 458 459 #ifdef CONFIG_X86_64 460 typedef int (*wakeup_cpu_handler)(int apicid, unsigned long start_eip); 461 extern void acpi_wake_cpu_handler_update(wakeup_cpu_handler handler); 462 extern int default_acpi_madt_oem_check(char *, char *); 463 #else 464 static inline int default_acpi_madt_oem_check(char *a, char *b) { return 0; } 465 #endif 466 467 extern int default_apic_id_valid(u32 apicid); 468 extern void default_setup_apic_routing(void); 469 470 extern u32 apic_default_calc_apicid(unsigned int cpu); 471 extern u32 apic_flat_calc_apicid(unsigned int cpu); 472 473 extern bool default_check_apicid_used(physid_mask_t *map, int apicid); 474 extern void default_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mask_t *retmap); 475 extern int default_cpu_present_to_apicid(int mps_cpu); 476 477 #else /* CONFIG_X86_LOCAL_APIC */ 478 479 static inline unsigned int read_apic_id(void) { return 0; } 480 481 #endif /* !CONFIG_X86_LOCAL_APIC */ 482 483 #ifdef CONFIG_SMP 484 void apic_smt_update(void); 485 #else 486 static inline void apic_smt_update(void) { } 487 #endif 488 489 struct msi_msg; 490 struct irq_cfg; 491 492 extern void __irq_msi_compose_msg(struct irq_cfg *cfg, struct msi_msg *msg, 493 bool dmar); 494 495 extern void ioapic_zap_locks(void); 496 497 #endif /* _ASM_X86_APIC_H */ 498