1 #ifndef _ASM_X86_APIC_H 2 #define _ASM_X86_APIC_H 3 4 #include <linux/cpumask.h> 5 #include <linux/pm.h> 6 7 #include <asm/alternative.h> 8 #include <asm/cpufeature.h> 9 #include <asm/processor.h> 10 #include <asm/apicdef.h> 11 #include <linux/atomic.h> 12 #include <asm/fixmap.h> 13 #include <asm/mpspec.h> 14 #include <asm/msr.h> 15 #include <asm/idle.h> 16 17 #define ARCH_APICTIMER_STOPS_ON_C3 1 18 19 /* 20 * Debugging macros 21 */ 22 #define APIC_QUIET 0 23 #define APIC_VERBOSE 1 24 #define APIC_DEBUG 2 25 26 /* 27 * Define the default level of output to be very little 28 * This can be turned up by using apic=verbose for more 29 * information and apic=debug for _lots_ of information. 30 * apic_verbosity is defined in apic.c 31 */ 32 #define apic_printk(v, s, a...) do { \ 33 if ((v) <= apic_verbosity) \ 34 printk(s, ##a); \ 35 } while (0) 36 37 38 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32) 39 extern void generic_apic_probe(void); 40 #else 41 static inline void generic_apic_probe(void) 42 { 43 } 44 #endif 45 46 #ifdef CONFIG_X86_LOCAL_APIC 47 48 extern unsigned int apic_verbosity; 49 extern int local_apic_timer_c2_ok; 50 51 extern int disable_apic; 52 extern unsigned int lapic_timer_frequency; 53 54 #ifdef CONFIG_SMP 55 extern void __inquire_remote_apic(int apicid); 56 #else /* CONFIG_SMP */ 57 static inline void __inquire_remote_apic(int apicid) 58 { 59 } 60 #endif /* CONFIG_SMP */ 61 62 static inline void default_inquire_remote_apic(int apicid) 63 { 64 if (apic_verbosity >= APIC_DEBUG) 65 __inquire_remote_apic(apicid); 66 } 67 68 /* 69 * With 82489DX we can't rely on apic feature bit 70 * retrieved via cpuid but still have to deal with 71 * such an apic chip so we assume that SMP configuration 72 * is found from MP table (64bit case uses ACPI mostly 73 * which set smp presence flag as well so we are safe 74 * to use this helper too). 75 */ 76 static inline bool apic_from_smp_config(void) 77 { 78 return smp_found_config && !disable_apic; 79 } 80 81 /* 82 * Basic functions accessing APICs. 83 */ 84 #ifdef CONFIG_PARAVIRT 85 #include <asm/paravirt.h> 86 #endif 87 88 extern int setup_profiling_timer(unsigned int); 89 90 static inline void native_apic_mem_write(u32 reg, u32 v) 91 { 92 volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg); 93 94 alternative_io("movl %0, %1", "xchgl %0, %1", X86_BUG_11AP, 95 ASM_OUTPUT2("=r" (v), "=m" (*addr)), 96 ASM_OUTPUT2("0" (v), "m" (*addr))); 97 } 98 99 static inline u32 native_apic_mem_read(u32 reg) 100 { 101 return *((volatile u32 *)(APIC_BASE + reg)); 102 } 103 104 extern void native_apic_wait_icr_idle(void); 105 extern u32 native_safe_apic_wait_icr_idle(void); 106 extern void native_apic_icr_write(u32 low, u32 id); 107 extern u64 native_apic_icr_read(void); 108 109 static inline bool apic_is_x2apic_enabled(void) 110 { 111 u64 msr; 112 113 if (rdmsrl_safe(MSR_IA32_APICBASE, &msr)) 114 return false; 115 return msr & X2APIC_ENABLE; 116 } 117 118 #ifdef CONFIG_X86_X2APIC 119 /* 120 * Make previous memory operations globally visible before 121 * sending the IPI through x2apic wrmsr. We need a serializing instruction or 122 * mfence for this. 123 */ 124 static inline void x2apic_wrmsr_fence(void) 125 { 126 asm volatile("mfence" : : : "memory"); 127 } 128 129 static inline void native_apic_msr_write(u32 reg, u32 v) 130 { 131 if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR || 132 reg == APIC_LVR) 133 return; 134 135 wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0); 136 } 137 138 static inline void native_apic_msr_eoi_write(u32 reg, u32 v) 139 { 140 wrmsr(APIC_BASE_MSR + (APIC_EOI >> 4), APIC_EOI_ACK, 0); 141 } 142 143 static inline u32 native_apic_msr_read(u32 reg) 144 { 145 u64 msr; 146 147 if (reg == APIC_DFR) 148 return -1; 149 150 rdmsrl(APIC_BASE_MSR + (reg >> 4), msr); 151 return (u32)msr; 152 } 153 154 static inline void native_x2apic_wait_icr_idle(void) 155 { 156 /* no need to wait for icr idle in x2apic */ 157 return; 158 } 159 160 static inline u32 native_safe_x2apic_wait_icr_idle(void) 161 { 162 /* no need to wait for icr idle in x2apic */ 163 return 0; 164 } 165 166 static inline void native_x2apic_icr_write(u32 low, u32 id) 167 { 168 wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low); 169 } 170 171 static inline u64 native_x2apic_icr_read(void) 172 { 173 unsigned long val; 174 175 rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val); 176 return val; 177 } 178 179 extern int x2apic_mode; 180 extern int x2apic_phys; 181 extern void __init check_x2apic(void); 182 extern void enable_x2apic(void); 183 static inline int x2apic_enabled(void) 184 { 185 return cpu_has_x2apic && apic_is_x2apic_enabled(); 186 } 187 188 #define x2apic_supported() (cpu_has_x2apic) 189 static inline void x2apic_force_phys(void) 190 { 191 x2apic_phys = 1; 192 } 193 #else 194 static inline void disable_x2apic(void) 195 { 196 } 197 static inline void check_x2apic(void) 198 { 199 } 200 static inline void enable_x2apic(void) 201 { 202 } 203 static inline int x2apic_enabled(void) 204 { 205 return 0; 206 } 207 static inline void x2apic_force_phys(void) 208 { 209 } 210 211 #define x2apic_mode (0) 212 #define x2apic_supported() (0) 213 #endif 214 215 extern void enable_IR_x2apic(void); 216 217 extern int get_physical_broadcast(void); 218 219 extern int lapic_get_maxlvt(void); 220 extern void clear_local_APIC(void); 221 extern void connect_bsp_APIC(void); 222 extern void disconnect_bsp_APIC(int virt_wire_setup); 223 extern void disable_local_APIC(void); 224 extern void lapic_shutdown(void); 225 extern int verify_local_APIC(void); 226 extern void sync_Arb_IDs(void); 227 extern void init_bsp_APIC(void); 228 extern void setup_local_APIC(void); 229 extern void end_local_APIC_setup(void); 230 extern void bsp_end_local_APIC_setup(void); 231 extern void init_apic_mappings(void); 232 void register_lapic_address(unsigned long address); 233 extern void setup_boot_APIC_clock(void); 234 extern void setup_secondary_APIC_clock(void); 235 extern int APIC_init_uniprocessor(void); 236 extern int apic_force_enable(unsigned long addr); 237 238 /* 239 * On 32bit this is mach-xxx local 240 */ 241 #ifdef CONFIG_X86_64 242 extern int apic_is_clustered_box(void); 243 #else 244 static inline int apic_is_clustered_box(void) 245 { 246 return 0; 247 } 248 #endif 249 250 extern int setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask); 251 252 #else /* !CONFIG_X86_LOCAL_APIC */ 253 static inline void lapic_shutdown(void) { } 254 #define local_apic_timer_c2_ok 1 255 static inline void init_apic_mappings(void) { } 256 static inline void disable_local_APIC(void) { } 257 # define setup_boot_APIC_clock x86_init_noop 258 # define setup_secondary_APIC_clock x86_init_noop 259 #endif /* !CONFIG_X86_LOCAL_APIC */ 260 261 #ifdef CONFIG_X86_64 262 #define SET_APIC_ID(x) (apic->set_apic_id(x)) 263 #else 264 265 #endif 266 267 /* 268 * Copyright 2004 James Cleverdon, IBM. 269 * Subject to the GNU Public License, v.2 270 * 271 * Generic APIC sub-arch data struct. 272 * 273 * Hacked for x86-64 by James Cleverdon from i386 architecture code by 274 * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and 275 * James Cleverdon. 276 */ 277 struct apic { 278 char *name; 279 280 int (*probe)(void); 281 int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id); 282 int (*apic_id_valid)(int apicid); 283 int (*apic_id_registered)(void); 284 285 u32 irq_delivery_mode; 286 u32 irq_dest_mode; 287 288 const struct cpumask *(*target_cpus)(void); 289 290 int disable_esr; 291 292 int dest_logical; 293 unsigned long (*check_apicid_used)(physid_mask_t *map, int apicid); 294 295 void (*vector_allocation_domain)(int cpu, struct cpumask *retmask, 296 const struct cpumask *mask); 297 void (*init_apic_ldr)(void); 298 299 void (*ioapic_phys_id_map)(physid_mask_t *phys_map, physid_mask_t *retmap); 300 301 void (*setup_apic_routing)(void); 302 int (*cpu_present_to_apicid)(int mps_cpu); 303 void (*apicid_to_cpu_present)(int phys_apicid, physid_mask_t *retmap); 304 int (*check_phys_apicid_present)(int phys_apicid); 305 int (*phys_pkg_id)(int cpuid_apic, int index_msb); 306 307 unsigned int (*get_apic_id)(unsigned long x); 308 unsigned long (*set_apic_id)(unsigned int id); 309 unsigned long apic_id_mask; 310 311 int (*cpu_mask_to_apicid_and)(const struct cpumask *cpumask, 312 const struct cpumask *andmask, 313 unsigned int *apicid); 314 315 /* ipi */ 316 void (*send_IPI_mask)(const struct cpumask *mask, int vector); 317 void (*send_IPI_mask_allbutself)(const struct cpumask *mask, 318 int vector); 319 void (*send_IPI_allbutself)(int vector); 320 void (*send_IPI_all)(int vector); 321 void (*send_IPI_self)(int vector); 322 323 /* wakeup_secondary_cpu */ 324 int (*wakeup_secondary_cpu)(int apicid, unsigned long start_eip); 325 326 bool wait_for_init_deassert; 327 void (*inquire_remote_apic)(int apicid); 328 329 /* apic ops */ 330 u32 (*read)(u32 reg); 331 void (*write)(u32 reg, u32 v); 332 /* 333 * ->eoi_write() has the same signature as ->write(). 334 * 335 * Drivers can support both ->eoi_write() and ->write() by passing the same 336 * callback value. Kernel can override ->eoi_write() and fall back 337 * on write for EOI. 338 */ 339 void (*eoi_write)(u32 reg, u32 v); 340 u64 (*icr_read)(void); 341 void (*icr_write)(u32 low, u32 high); 342 void (*wait_icr_idle)(void); 343 u32 (*safe_wait_icr_idle)(void); 344 345 #ifdef CONFIG_X86_32 346 /* 347 * Called very early during boot from get_smp_config(). It should 348 * return the logical apicid. x86_[bios]_cpu_to_apicid is 349 * initialized before this function is called. 350 * 351 * If logical apicid can't be determined that early, the function 352 * may return BAD_APICID. Logical apicid will be configured after 353 * init_apic_ldr() while bringing up CPUs. Note that NUMA affinity 354 * won't be applied properly during early boot in this case. 355 */ 356 int (*x86_32_early_logical_apicid)(int cpu); 357 #endif 358 }; 359 360 /* 361 * Pointer to the local APIC driver in use on this system (there's 362 * always just one such driver in use - the kernel decides via an 363 * early probing process which one it picks - and then sticks to it): 364 */ 365 extern struct apic *apic; 366 367 /* 368 * APIC drivers are probed based on how they are listed in the .apicdrivers 369 * section. So the order is important and enforced by the ordering 370 * of different apic driver files in the Makefile. 371 * 372 * For the files having two apic drivers, we use apic_drivers() 373 * to enforce the order with in them. 374 */ 375 #define apic_driver(sym) \ 376 static const struct apic *__apicdrivers_##sym __used \ 377 __aligned(sizeof(struct apic *)) \ 378 __section(.apicdrivers) = { &sym } 379 380 #define apic_drivers(sym1, sym2) \ 381 static struct apic *__apicdrivers_##sym1##sym2[2] __used \ 382 __aligned(sizeof(struct apic *)) \ 383 __section(.apicdrivers) = { &sym1, &sym2 } 384 385 extern struct apic *__apicdrivers[], *__apicdrivers_end[]; 386 387 /* 388 * APIC functionality to boot other CPUs - only used on SMP: 389 */ 390 #ifdef CONFIG_SMP 391 extern atomic_t init_deasserted; 392 extern int wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip); 393 #endif 394 395 #ifdef CONFIG_X86_LOCAL_APIC 396 397 static inline u32 apic_read(u32 reg) 398 { 399 return apic->read(reg); 400 } 401 402 static inline void apic_write(u32 reg, u32 val) 403 { 404 apic->write(reg, val); 405 } 406 407 static inline void apic_eoi(void) 408 { 409 apic->eoi_write(APIC_EOI, APIC_EOI_ACK); 410 } 411 412 static inline u64 apic_icr_read(void) 413 { 414 return apic->icr_read(); 415 } 416 417 static inline void apic_icr_write(u32 low, u32 high) 418 { 419 apic->icr_write(low, high); 420 } 421 422 static inline void apic_wait_icr_idle(void) 423 { 424 apic->wait_icr_idle(); 425 } 426 427 static inline u32 safe_apic_wait_icr_idle(void) 428 { 429 return apic->safe_wait_icr_idle(); 430 } 431 432 extern void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)); 433 434 #else /* CONFIG_X86_LOCAL_APIC */ 435 436 static inline u32 apic_read(u32 reg) { return 0; } 437 static inline void apic_write(u32 reg, u32 val) { } 438 static inline void apic_eoi(void) { } 439 static inline u64 apic_icr_read(void) { return 0; } 440 static inline void apic_icr_write(u32 low, u32 high) { } 441 static inline void apic_wait_icr_idle(void) { } 442 static inline u32 safe_apic_wait_icr_idle(void) { return 0; } 443 static inline void apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) {} 444 445 #endif /* CONFIG_X86_LOCAL_APIC */ 446 447 static inline void ack_APIC_irq(void) 448 { 449 /* 450 * ack_APIC_irq() actually gets compiled as a single instruction 451 * ... yummie. 452 */ 453 apic_eoi(); 454 } 455 456 static inline unsigned default_get_apic_id(unsigned long x) 457 { 458 unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR)); 459 460 if (APIC_XAPIC(ver) || boot_cpu_has(X86_FEATURE_EXTD_APICID)) 461 return (x >> 24) & 0xFF; 462 else 463 return (x >> 24) & 0x0F; 464 } 465 466 /* 467 * Warm reset vector position: 468 */ 469 #define TRAMPOLINE_PHYS_LOW 0x467 470 #define TRAMPOLINE_PHYS_HIGH 0x469 471 472 #ifdef CONFIG_X86_64 473 extern void apic_send_IPI_self(int vector); 474 475 DECLARE_PER_CPU(int, x2apic_extra_bits); 476 477 extern int default_cpu_present_to_apicid(int mps_cpu); 478 extern int default_check_phys_apicid_present(int phys_apicid); 479 #endif 480 481 extern void generic_bigsmp_probe(void); 482 483 484 #ifdef CONFIG_X86_LOCAL_APIC 485 486 #include <asm/smp.h> 487 488 #define APIC_DFR_VALUE (APIC_DFR_FLAT) 489 490 static inline const struct cpumask *default_target_cpus(void) 491 { 492 #ifdef CONFIG_SMP 493 return cpu_online_mask; 494 #else 495 return cpumask_of(0); 496 #endif 497 } 498 499 static inline const struct cpumask *online_target_cpus(void) 500 { 501 return cpu_online_mask; 502 } 503 504 DECLARE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid); 505 506 507 static inline unsigned int read_apic_id(void) 508 { 509 unsigned int reg; 510 511 reg = apic_read(APIC_ID); 512 513 return apic->get_apic_id(reg); 514 } 515 516 static inline int default_apic_id_valid(int apicid) 517 { 518 return (apicid < 255); 519 } 520 521 extern int default_acpi_madt_oem_check(char *, char *); 522 523 extern void default_setup_apic_routing(void); 524 525 extern struct apic apic_noop; 526 527 #ifdef CONFIG_X86_32 528 529 static inline int noop_x86_32_early_logical_apicid(int cpu) 530 { 531 return BAD_APICID; 532 } 533 534 /* 535 * Set up the logical destination ID. 536 * 537 * Intel recommends to set DFR, LDR and TPR before enabling 538 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel 539 * document number 292116). So here it goes... 540 */ 541 extern void default_init_apic_ldr(void); 542 543 static inline int default_apic_id_registered(void) 544 { 545 return physid_isset(read_apic_id(), phys_cpu_present_map); 546 } 547 548 static inline int default_phys_pkg_id(int cpuid_apic, int index_msb) 549 { 550 return cpuid_apic >> index_msb; 551 } 552 553 #endif 554 555 static inline int 556 flat_cpu_mask_to_apicid_and(const struct cpumask *cpumask, 557 const struct cpumask *andmask, 558 unsigned int *apicid) 559 { 560 unsigned long cpu_mask = cpumask_bits(cpumask)[0] & 561 cpumask_bits(andmask)[0] & 562 cpumask_bits(cpu_online_mask)[0] & 563 APIC_ALL_CPUS; 564 565 if (likely(cpu_mask)) { 566 *apicid = (unsigned int)cpu_mask; 567 return 0; 568 } else { 569 return -EINVAL; 570 } 571 } 572 573 extern int 574 default_cpu_mask_to_apicid_and(const struct cpumask *cpumask, 575 const struct cpumask *andmask, 576 unsigned int *apicid); 577 578 static inline void 579 flat_vector_allocation_domain(int cpu, struct cpumask *retmask, 580 const struct cpumask *mask) 581 { 582 /* Careful. Some cpus do not strictly honor the set of cpus 583 * specified in the interrupt destination when using lowest 584 * priority interrupt delivery mode. 585 * 586 * In particular there was a hyperthreading cpu observed to 587 * deliver interrupts to the wrong hyperthread when only one 588 * hyperthread was specified in the interrupt desitination. 589 */ 590 cpumask_clear(retmask); 591 cpumask_bits(retmask)[0] = APIC_ALL_CPUS; 592 } 593 594 static inline void 595 default_vector_allocation_domain(int cpu, struct cpumask *retmask, 596 const struct cpumask *mask) 597 { 598 cpumask_copy(retmask, cpumask_of(cpu)); 599 } 600 601 static inline unsigned long default_check_apicid_used(physid_mask_t *map, int apicid) 602 { 603 return physid_isset(apicid, *map); 604 } 605 606 static inline void default_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mask_t *retmap) 607 { 608 *retmap = *phys_map; 609 } 610 611 static inline int __default_cpu_present_to_apicid(int mps_cpu) 612 { 613 if (mps_cpu < nr_cpu_ids && cpu_present(mps_cpu)) 614 return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu); 615 else 616 return BAD_APICID; 617 } 618 619 static inline int 620 __default_check_phys_apicid_present(int phys_apicid) 621 { 622 return physid_isset(phys_apicid, phys_cpu_present_map); 623 } 624 625 #ifdef CONFIG_X86_32 626 static inline int default_cpu_present_to_apicid(int mps_cpu) 627 { 628 return __default_cpu_present_to_apicid(mps_cpu); 629 } 630 631 static inline int 632 default_check_phys_apicid_present(int phys_apicid) 633 { 634 return __default_check_phys_apicid_present(phys_apicid); 635 } 636 #else 637 extern int default_cpu_present_to_apicid(int mps_cpu); 638 extern int default_check_phys_apicid_present(int phys_apicid); 639 #endif 640 641 #endif /* CONFIG_X86_LOCAL_APIC */ 642 extern void irq_enter(void); 643 extern void irq_exit(void); 644 645 static inline void entering_irq(void) 646 { 647 irq_enter(); 648 exit_idle(); 649 } 650 651 static inline void entering_ack_irq(void) 652 { 653 ack_APIC_irq(); 654 entering_irq(); 655 } 656 657 static inline void exiting_irq(void) 658 { 659 irq_exit(); 660 } 661 662 static inline void exiting_ack_irq(void) 663 { 664 irq_exit(); 665 /* Ack only at the end to avoid potential reentry */ 666 ack_APIC_irq(); 667 } 668 669 extern void ioapic_zap_locks(void); 670 671 #endif /* _ASM_X86_APIC_H */ 672